sys/dev/eisa/ahbreg.h

   1 /*      $NetBSD: ahbreg.h,v 1.15 2005/12/11 12:21:20 christos Exp $     */
   2
   3 /*-
   4  * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc.
   5  * All rights reserved.
   6  *
   7  * This code is derived from software contributed to The NetBSD Foundation
   8  * by Charles M. Hannum and by Jason R. Thorpe of the Numerical Aerospace
   9  * Simulation Facility, NASA Ames Research Center.
  10  *
  11  * Redistribution and use in source and binary forms, with or without
  12  * modification, are permitted provided that the following conditions
  13  * are met:
  14  * 1. Redistributions of source code must retain the above copyright
  15  *    notice, this list of conditions and the following disclaimer.
  16  * 2. Redistributions in binary form must reproduce the above copyright
  17  *    notice, this list of conditions and the following disclaimer in the
  18  *    documentation and/or other materials provided with the distribution.
  19  *
  20  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
  21  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  22  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  23  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
  24  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30  * POSSIBILITY OF SUCH DAMAGE.
  31  */
  32
  33 /*
  34  * Originally written by Julian Elischer (julian@tfs.com)
  35  * for TRW Financial Systems for use under the MACH(2.5) operating system.
  36  *
  37  * TRW Financial Systems, in accordance with their agreement with Carnegie
  38  * Mellon University, makes this software available to CMU to distribute
  39  * or use in any manner that they see fit as long as this message is kept with
  40  * the software. For this reason TFS also grants any other persons or
  41  * organisations permission to use or modify this software.
  42  *
  43  * TFS supplies this software to be publicly redistributed
  44  * on the understanding that TFS is not responsible for the correct
  45  * functioning of this software in any circumstances.
  46  */
  47
  48 typedef u_int32_t physaddr;
  49 typedef u_int32_t physlen;
  50
  51 /*
  52  * Offset of AHA1740 registers, relative from slot base.
  53  */
  54 #define AHB_EISA_SLOT_OFFSET    0x0c80
  55 #define AHB_EISA_IOSIZE         0x0080
  56
  57 /*
  58  * AHA1740 EISA board mode registers (relative to port offset)
  59  */
  60 #define PORTADDR        0x40
  61 #define  PORTADDR_ENHANCED      0x80
  62 #define BIOSADDR        0x41
  63 #define INTDEF          0x42
  64 #define SCSIDEF         0x43
  65 #define BUSDEF          0x44
  66 /**** bit definitions for INTDEF ****/
  67 #define INT9    0x00
  68 #define INT10   0x01
  69 #define INT11   0x02
  70 #define INT12   0x03
  71 #define INT14   0x05
  72 #define INT15   0x06
  73 #define INTHIGH 0x08            /* int high=ACTIVE (else edge) */
  74 #define INTEN   0x10
  75 /**** bit definitions for SCSIDEF ****/
  76 #define HSCSIID 0x0F            /* our SCSI ID */
  77 #define RSTPWR  0x10            /* reset scsi bus on power up or reset */
  78 /**** bit definitions for BUSDEF ****/
  79 #define B0uS    0x00            /* give up bus immediatly */
  80 #define B4uS    0x01            /* delay 4uSec. */
  81 #define B8uS    0x02
  82
  83 /*
  84  * AHA1740 ENHANCED mode mailbox control regs (relative to port offset)
  85  */
  86 #define MBOXOUT0        0x50
  87 #define MBOXOUT1        0x51
  88 #define MBOXOUT2        0x52
  89 #define MBOXOUT3        0x53
  90
  91 #define ATTN            0x54
  92 #define G2CNTRL         0x55
  93 #define G2INTST         0x56
  94 #define G2STAT          0x57
  95
  96 #define MBOXIN0         0x58
  97 #define MBOXIN1         0x59
  98 #define MBOXIN2         0x5A
  99 #define MBOXIN3         0x5B
 100
 101 #define G2STAT2         0x5C
 102
 103 /*
 104  * Bit definitions for the 5 control/status registers
 105  */
 106 #define ATTN_TARGET             0x0F
 107 #define ATTN_OPCODE             0xF0
 108 #define  OP_IMMED               0x10
 109 #define   AHB_TARG_RESET        0x80
 110 #define  OP_START_ECB           0x40
 111 #define  OP_ABORT_ECB           0x50
 112
 113 #define G2CNTRL_SET_HOST_READY  0x20
 114 #define G2CNTRL_CLEAR_EISA_INT  0x40
 115 #define G2CNTRL_HARD_RESET      0x80
 116
 117 #define G2INTST_TARGET          0x0F
 118 #define G2INTST_INT_STAT        0xF0
 119 #define  AHB_ECB_OK             0x10
 120 #define  AHB_ECB_RECOVERED      0x50
 121 #define  AHB_HW_ERR             0x70
 122 #define  AHB_IMMED_OK           0xA0
 123 #define  AHB_ECB_ERR            0xC0
 124 #define  AHB_ASN                0xD0    /* for target mode */
 125 #define  AHB_IMMED_ERR          0xE0
 126
 127 #define G2STAT_BUSY             0x01
 128 #define G2STAT_INT_PEND         0x02
 129 #define G2STAT_MBOX_EMPTY       0x04
 130
 131 #define G2STAT2_HOST_READY      0x01
 132
 133 #define AHB_NSEG        33      /* number of DMA segments supported */
 134
 135 struct ahb_dma_seg {
 136         physaddr seg_addr;
 137         physlen seg_len;
 138 };
 139
 140 struct ahb_ecb_status {
 141         u_short status;
 142 #define ST_DON  0x0001
 143 #define ST_DU   0x0002
 144 #define ST_QF   0x0008
 145 #define ST_SC   0x0010
 146 #define ST_DO   0x0020
 147 #define ST_CH   0x0040
 148 #define ST_INT  0x0080
 149 #define ST_ASA  0x0100
 150 #define ST_SNS  0x0200
 151 #define ST_INI  0x0800
 152 #define ST_ME   0x1000
 153 #define ST_ECA  0x4000
 154         u_char  host_stat;
 155 #define HS_OK                   0x00
 156 #define HS_CMD_ABORTED_HOST     0x04
 157 #define HS_CMD_ABORTED_ADAPTER  0x05
 158 #define HS_TIMED_OUT            0x11
 159 #define HS_HARDWARE_ERR         0x20
 160 #define HS_SCSI_RESET_ADAPTER   0x22
 161 #define HS_SCSI_RESET_INCOMING  0x23
 162         u_char  target_stat;
 163         u_int32_t  resid_count;
 164         u_int32_t  resid_addr;
 165         u_short addit_status;
 166         u_char  sense_len;
 167         u_char  unused[9];
 168         u_char  cdb[6];
 169 };
 170
 171 struct ahb_ecb {
 172         u_char  opcode;
 173 #define ECB_SCSI_OP     0x01
 174                 u_char:4;
 175         u_char  options:3;
 176                 u_char:1;
 177         short   opt1;
 178 #define ECB_CNE 0x0001
 179 #define ECB_DI  0x0080
 180 #define ECB_SES 0x0400
 181 #define ECB_S_G 0x1000
 182 #define ECB_DSB 0x4000
 183 #define ECB_ARS 0x8000
 184         short   opt2;
 185 #define ECB_LUN 0x0007
 186 #define ECB_TAG 0x0008
 187 #define ECB_TT  0x0030
 188 #define ECB_ND  0x0040
 189 #define ECB_DAT 0x0100
 190 #define ECB_DIR 0x0200
 191 #define ECB_ST  0x0400
 192 #define ECB_CHK 0x0800
 193 #define ECB_REC 0x4000
 194 #define ECB_NRB 0x8000
 195         u_short unused1;
 196         physaddr data_addr;
 197         physlen  data_length;
 198         physaddr status;
 199         physaddr link_addr;
 200         short   unused2;
 201         short   unused3;
 202         physaddr sense_ptr;
 203         u_char  req_sense_length;
 204         u_char  scsi_cmd_length;
 205         short   cksum;
 206         u_char  scsi_cmd[12];
 207
 208         /*-----------------end of hardware supported fields----------------*/
 209
 210         struct ahb_dma_seg ahb_dma[AHB_NSEG];
 211         struct ahb_ecb_status ecb_status;
 212         struct scsi_sense_data ecb_sense;
 213
 214         TAILQ_ENTRY(ahb_ecb) chain;
 215         struct ahb_ecb *nexthash;
 216         int32_t hashkey;
 217         struct scsipi_xfer *xs; /* the scsipi_xfer for this cmd */
 218         int flags;
 219 #define ECB_ALLOC       0x01
 220 #define ECB_ABORT       0x02
 221 #define ECB_IMMED       0x04
 222 #define ECB_IMMED_FAIL  0x08
 223         int timeout;
 224
 225         /*
 226          * This DMA map maps the buffer involved in the transfer.
 227          * Its contents are loaded into "ahb_dma" above.
 228          */
 229         bus_dmamap_t    dmamap_xfer;
 230 };