1 /* $NetBSD: aic6915reg.h,v 1.4 2005/12/11 12:21:25 christos Exp $ */
4 * Copyright (c) 2001 The NetBSD Foundation, Inc.
7 * This code is derived from software contributed to The NetBSD Foundation
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
32 #ifndef _DEV_IC_AIC6915REG_H_
33 #define _DEV_IC_AIC6915REG_H_
36 * Register description for the Adaptec AIC-6915 (``Starfire'')
37 * 10/100 Ethernet controller.
41 * Receive Buffer Descriptor (One-size, 32-bit addressing)
44 uint32_t rbd32_addr
; /* address, flags */
48 * Receive Buffer Descriptor (One-size, 64-bit addressing)
51 uint32_t rbd64_addr_lo
; /* address (LSD), flags */
52 uint32_t rbd64_addr_hi
; /* address (MDS) */
55 #define RBD_V (1U << 0) /* valid descriptor */
56 #define RBD_E (1U << 1) /* end of ring */
59 * Short (Type 0) Completion Descriptor
62 uint32_t rcd_word0
; /* length, end index, status1 */
66 * Basic (Type 1) Completion Descriptor
69 uint32_t rcd_word0
; /* length, end index, status1 */
70 uint32_t rcd_word1
; /* VLAN ID, status2 */
74 * Checksum (Type 2) Completion Descriptor
76 struct sf_rcd_checksum
{
77 uint32_t rcd_word0
; /* length, end index, status1 */
78 uint32_t rcd_word1
; /* partial TCP/UDP checksum, status2 */
82 * Full (Type 3) Completion Descriptor
85 uint32_t rcd_word0
; /* length, end index, status1 */
86 uint32_t rcd_word1
; /* start index, status3, status2 */
87 uint32_t rcd_word2
; /* VLAN ID + priority, TCP/UDP csum */
88 uint32_t rcd_timestamp
; /* timestamp */
91 #define RCD_W0_ID (1U << 30)
93 #define RCD_W0_Length(x) ((x) & 0xffff)
94 #define RCD_W0_EndIndex(x) (((x) >> 16) & 0x7ff)
95 #define RCD_W0_BufferQueue (1U << 27) /* 1 == Queue 2 */
96 #define RCD_W0_FifoFull (1U << 28) /* FIFO full */
97 #define RCD_W0_OK (1U << 29) /* packet is OK */
100 #define RCD_W1_FrameType (7U << 16)
101 #define RCD_W1_FrameType_Unknown (0 << 16)
102 #define RCD_W1_FrameType_IPv4 (1U << 16)
103 #define RCD_W1_FrameType_IPv6 (2U << 16)
104 #define RCD_W1_FrameType_IPX (3U << 16)
105 #define RCD_W1_FrameType_ICMP (4U << 16)
106 #define RCD_W1_FrameType_Unsupported (5U << 16)
107 #define RCD_W1_UdpFrame (1U << 19)
108 #define RCD_W1_TcpFrame (1U << 20)
109 #define RCD_W1_Fragmented (1U << 21)
110 #define RCD_W1_PartialChecksumValid (1U << 22)
111 #define RCD_W1_ChecksumBad (1U << 23)
112 #define RCD_W1_ChecksumOk (1U << 24)
113 #define RCD_W1_VlanFrame (1U << 25)
114 #define RCD_W1_ReceiveCodeViolation (1U << 26)
115 #define RCD_W1_Dribble (1U << 27)
116 #define RCD_W1_ISLCRCerror (1U << 28)
117 #define RCD_W1_CRCerror (1U << 29)
118 #define RCD_W1_Hash (1U << 30)
119 #define RCD_W1_Perfect (1U << 31)
121 #define RCD_W1_VLANID(x) ((x) & 0xffff)
122 #define RCD_W1_TCP_UDP_Checksum(x) ((x) & 0xffff)
125 #define RCD_W1_Trailer (1U << 11)
126 #define RCD_W1_Header (1U << 12)
127 #define RCD_W1_ControlFrame (1U << 13)
128 #define RCD_W1_PauseFrame (1U << 14)
129 #define RCD_W1_IslFrame (1U << 15)
131 #define RCD_W1_StartIndex(x) ((x) & 0x7ff)
133 #define RCD_W2_TCP_UDP_Checksum(x) ((x) >> 16)
134 #define RCD_W2_VLANID(x) ((x) & 0xffff)
137 * Number of transmit buffer fragments we use. This is arbitrary, but
138 * we choose it carefully; see blow.
140 #define SF_NTXFRAGS 15
143 * Type 0, 32-bit addressing mode (Frame Descriptor) Transmit Descriptor
145 * NOTE: The total length of this structure is: 8 + (15 * 8) == 128
146 * This means 16 Tx indices per Type 0 descriptor. This is important later
151 uint32_t td_word0
; /* ID, flags */
152 uint32_t td_word1
; /* Tx buffer count */
154 uint32_t fr_addr
; /* address */
155 uint32_t fr_len
; /* length */
156 } td_frags
[SF_NTXFRAGS
];
159 #define TD_W1_NTXBUFS (0xff << 0)
162 * Type 1, 32-bit addressing mode (Buffer Descriptor) Transmit Descriptor
166 uint32_t td_word0
; /* ID, flags */
167 uint32_t td_addr
; /* buffer address */
170 #define TD_W0_ID (0xb << 28)
171 #define TD_W0_INTR (1U << 27)
172 #define TD_W0_END (1U << 26)
173 #define TD_W0_CALTCP (1U << 25)
174 #define TD_W0_CRCEN (1U << 24)
175 #define TD_W0_LEN (0xffff << 0)
176 #define TD_W0_NTXBUFS (0xff << 16)
177 #define TD_W0_NTXBUFS_SHIFT 16
180 * Type 2, 64-bit addressing mode (Buffer Descriptor) Transmit Descriptor
184 uint32_t td_word0
; /* ID, flags */
185 uint32_t td_reserved
;
186 uint32_t td_addr_lo
; /* buffer address (LSD) */
187 uint32_t td_addr_hi
; /* buffer address (MSD) */
191 * Transmit Completion Descriptor.
194 uint32_t tcd_word0
; /* index, priority, flags */
197 #define TCD_DMA_ID (0x4 << 29)
198 #define TCD_INDEX(x) ((x) & 0x7fff)
199 #define TCD_PR (1U << 15)
200 #define TCD_TIMESTAMP(x) (((x) >> 16) & 0x1fff)
202 #define TCD_TX_ID (0x5 << 29)
203 #define TCD_CRCerror (1U << 16)
204 #define TCD_FieldLengthCkError (1U << 17)
205 #define TCD_FieldLengthRngError (1U << 18)
206 #define TCD_PacketTxOk (1U << 19)
207 #define TCD_Deferred (1U << 20)
208 #define TCD_ExDeferral (1U << 21)
209 #define TCD_ExCollisions (1U << 22)
210 #define TCD_LateCollision (1U << 23)
211 #define TCD_LongFrame (1U << 24)
212 #define TCD_FIFOUnderrun (1U << 25)
213 #define TCD_ControlTx (1U << 26)
214 #define TCD_PauseTx (1U << 27)
215 #define TCD_TxPaused (1U << 28)
218 * The Tx indices are in units of 8 bytes, and since we are using
219 * Tx descriptors that are 128 bytes long, we need to divide by 16
220 * to get the actual index that we care about.
222 #define SF_TXDINDEX_TO_HOST(x) ((x) >> 4)
223 #define SF_TXDINDEX_TO_CHIP(x) ((x) << 4)
226 * To make matters worse, the manual lies about the indices in the
227 * completion queue entires. It claims they are in 8-byte units,
228 * but they're actually *BYTES*, which means we need to divide by
229 * 128 to get the actual index.
231 #define SF_TCD_INDEX_TO_HOST(x) ((x) >> 7)
234 * PCI configuration space addresses.
236 #define SF_PCI_MEMBA (PCI_MAPREG_START + 0x00)
237 #define SF_PCI_IOBA (PCI_MAPREG_START + 0x08)
239 #define SF_GENREG_OFFSET 0x50000
240 #define SF_FUNCREG_SIZE 0x100
243 * PCI functional registers.
245 #define SF_PciDeviceConfig 0x40
246 #define PDC_EnDpeInt (1U << 31) /* enable DPE PCIint */
247 #define PDC_EnSseInt (1U << 30) /* enable SSE PCIint */
248 #define PDC_EnRmaInt (1U << 29) /* enable RMA PCIint */
249 #define PDC_EnRtaInt (1U << 28) /* enable RTA PCIint */
250 #define PDC_EnStaInt (1U << 27) /* enable STA PCIint */
251 #define PDC_EnDprInt (1U << 24) /* enable DPR PCIint */
252 #define PDC_IntEnable (1U << 23) /* enable PCI_INTA_ */
253 #define PDC_ExternalRegCsWidth (7U << 20) /* external chip-sel width */
254 #define PDC_StopMWrOnCacheLineDis (1U << 19)
255 #define PDC_EpromCsWidth (7U << 16)
256 #define PDC_EnBeLogic (1U << 15)
257 #define PDC_LatencyStopOnCacheLine (1U << 14)
258 #define PDC_PCIMstDmaEn (1U << 13)
259 #define PDC_StopOnCachelineEn (1U << 12)
260 #define PDC_FifoThreshold (0xf << 8)
261 #define PDC_FifoThreshold_SHIFT 8
262 #define PDC_MemRdCmdEn (1U << 7)
263 #define PDC_StopOnPerr (1U << 6)
264 #define PDC_AbortOnAddrParityErr (1U << 5)
265 #define PDC_EnIncrement (1U << 4)
266 #define PDC_System64 (1U << 2)
267 #define PDC_Force64 (1U << 1)
268 #define PDC_SoftReset (1U << 0)
270 #define SF_BacControl 0x44
271 #define BC_DescSwapMode (0x3 << 6)
272 #define BC_DataSwapMode (0x3 << 4)
273 #define BC_SingleDmaMode (1U << 3)
274 #define BC_PreferTxDmaReq (1U << 2)
275 #define BC_PreferRxDmaReq (1U << 1)
276 #define BC_BacDmaEn (1U << 0)
278 #define SF_PciMonitor1 0x48
280 #define SF_PciMonitor2 0x4c
284 #define SF_PMCSR 0x54
286 #define SF_PMEvent 0x58
288 #define SF_SerialEpromControl 0x60
289 #define SEC_InitDone (1U << 3)
290 #define SEC_Idle (1U << 2)
291 #define SEC_WriteEnable (1U << 1)
292 #define SEC_WriteDisable (1U << 0)
294 #define SF_PciComplianceTesting 0x64
296 #define SF_IndirectIoAccess 0x68
298 #define SF_IndirectIoDataPort 0x6c
301 * Ethernet functional registers.
303 #define SF_GeneralEthernetCtrl 0x70
304 #define GEC_SetSoftInt (1U << 8)
305 #define GEC_TxGfpEn (1U << 5)
306 #define GEC_RxGfpEn (1U << 4)
307 #define GEC_TxDmaEn (1U << 3)
308 #define GEC_RxDmaEn (1U << 2)
309 #define GEC_TransmitEn (1U << 1)
310 #define GEC_ReceiveEn (1U << 0)
312 #define SF_TimersControl 0x74
313 #define TC_EarlyRxQ1IntDelayDisable (1U << 31)
314 #define TC_RxQ1DoneIntDelayDisable (1U << 30)
315 #define TC_EarlyRxQ2IntDelayDisable (1U << 29)
316 #define TC_RxQ2DoneIntDelayDisable (1U << 28)
317 #define TC_TimeStampResolution (1U << 26)
318 #define TC_GeneralTimerResolution (1U << 25)
319 #define TC_OneShotMode (1U << 24)
320 #define TC_GeneralTimerInterval (0xff << 16)
321 #define TC_GeneralTimerInterval_SHIFT 16
322 #define TC_TxFrameCompleteIntDelayDisable (1U << 15)
323 #define TC_TxQueueDoneIntDelayDisable (1U << 14)
324 #define TC_TxDmaDoneIntDelayDisable (1U << 13)
325 #define TC_RxHiPrBypass (1U << 12)
326 #define TC_Timer10X (1U << 11)
327 #define TC_SmallRxFrame (3U << 9)
328 #define TC_SmallFrameBypass (1U << 8)
329 #define TC_IntMaskMode (3U << 5)
330 #define TC_IntMaskPeriod (0x1f << 0)
332 #define SF_CurrentTime 0x78
334 #define SF_InterruptStatus 0x80
335 #define IS_GPIO3 (1U << 31)
336 #define IS_GPIO2 (1U << 30)
337 #define IS_GPIO1 (1U << 29)
338 #define IS_GPIO0 (1U << 28)
339 #define IS_StatisticWrapInt (1U << 27)
340 #define IS_AbnormalInterrupt (1U << 25)
341 #define IS_GeneralTimerInt (1U << 24)
342 #define IS_SoftInt (1U << 23)
343 #define IS_RxCompletionQueue1Int (1U << 22)
344 #define IS_TxCompletionQueueInt (1U << 21)
345 #define IS_PCIInt (1U << 20)
346 #define IS_DmaErrInt (1U << 19)
347 #define IS_TxDataLowInt (1U << 18)
348 #define IS_RxCompletionQueue2Int (1U << 17)
349 #define IS_RxQ1LowBuffersInt (1U << 16)
350 #define IS_NormalInterrupt (1U << 15)
351 #define IS_TxFrameCompleteInt (1U << 14)
352 #define IS_TxDmaDoneInt (1U << 13)
353 #define IS_TxQueueDoneInt (1U << 12)
354 #define IS_EarlyRxQ2Int (1U << 11)
355 #define IS_EarlyRxQ1Int (1U << 10)
356 #define IS_RxQ2DoneInt (1U << 9)
357 #define IS_RxQ1DoneInt (1U << 8)
358 #define IS_RxGfpNoResponseInt (1U << 7)
359 #define IS_RxQ2LowBuffersInt (1U << 6)
360 #define IS_NoTxChecksumInt (1U << 5)
361 #define IS_TxLowPrMismatchInt (1U << 4)
362 #define IS_TxHiPrMismatchInt (1U << 3)
363 #define IS_GfpRxInt (1U << 2)
364 #define IS_GfpTxInt (1U << 1)
365 #define IS_PCIPadInt (1U << 0)
367 #define SF_ShadowInterruptStatus 0x84
369 #define SF_InterruptEn 0x88
372 #define GPIOCtrl(x) (1U << (24 + (x)))
373 #define GPIOOutMode(x) (1U << (16 + (x)))
374 #define GPIOInpMode(x, y) ((y) << (8 + ((x) * 2)))
375 #define GPIOData(x) (1U << (x))
377 #define SF_TxDescQueueCtrl 0x90
378 #define TDQC_TxHighPriorityFifoThreshold(x) ((x) << 24)
379 #define TDQC_SkipLength(x) ((x) << 16)
380 #define TDQC_TxDmaBurstSize(x) ((x) << 8)
381 #define TDQC_TxDescQueue64bitAddr (1U << 7)
382 #define TDQC_MinFrameSpacing(x) ((x) << 4)
383 #define TDQC_DisableTxDmaCompletion (1U << 3)
384 #define TDQC_TxDescType(x) ((x) << 0)
386 #define SF_HiPrTxDescQueueBaseAddr 0x94
388 #define SF_LoPrTxDescQueueBaseAddr 0x98
390 #define SF_TxDescQueueHighAddr 0x9c
392 #define SF_TxDescQueueProducerIndex 0xa0
393 #define TDQPI_HiPrTxProducerIndex(x) ((x) << 16)
394 #define TDQPI_LoPrTxProducerIndex(x) ((x) << 0)
395 #define TDQPI_HiPrTxProducerIndex_get(x) (((x) >> 16) & 0x7ff)
396 #define TDQPI_LoPrTxProducerIndex_get(x) (((x) >> 0) & 0x7ff)
398 #define SF_TxDescQueueConsumerIndex 0xa4
399 #define TDQCI_HiPrTxConsumerIndex(x) (((x) >> 16) & 0x7ff)
400 #define TDQCI_LoPrTxConsumerIndex(s) (((x) >> 0) & 0x7ff)
402 #define SF_TxDmaStatus1 0xa8
404 #define SF_TxDmaStatus2 0xac
406 #define SF_TransmitFrameCSR 0xb0
407 #define TFCSR_TxFrameStatus (0xff << 16)
408 #define TFCSR_TxDebugConfigBits (0x7f << 9)
409 #define TFCSR_DmaCompletionAfterTransmitComplete (1U << 8)
410 #define TFCSR_TransmitThreshold(x) ((x) << 0)
412 #define SF_CompletionQueueHighAddr 0xb4
414 #define SF_TxCompletionQueueCtrl 0xb8
415 #define TCQC_TxCompletionBaseAddress 0xffffff00
416 #define TCQC_TxCompletion64bitAddress (1U << 7)
417 #define TCQC_TxCompletionProducerWe (1U << 6)
418 #define TCQC_TxCompletionSize (1U << 5)
419 #define TCQC_CommonQueueMode (1U << 4)
420 #define TCQC_TxCompletionQueueThreshold ((x) << 0)
422 #define SF_RxCompletionQueue1Ctrl 0xbc
423 #define RCQ1C_RxCompletionQ1BaseAddress 0xffffff00
424 #define RCQ1C_RxCompletionQ164bitAddress (1U << 7)
425 #define RCQ1C_RxCompletionQ1ProducerWe (1U << 6)
426 #define RCQ1C_RxCompletionQ1Type(x) ((x) << 4)
427 #define RCQ1C_RxCompletionQ1Threshold(x) ((x) << 0)
429 #define SF_RxCompletionQueue2Ctrl 0xc0
430 #define RCQ1C_RxCompletionQ2BaseAddress 0xffffff00
431 #define RCQ1C_RxCompletionQ264bitAddress (1U << 7)
432 #define RCQ1C_RxCompletionQ2ProducerWe (1U << 6)
433 #define RCQ1C_RxCompletionQ2Type(x) ((x) << 4)
434 #define RCQ1C_RxCompletionQ2Threshold(x) ((x) << 0)
436 #define SF_CompletionQueueConsumerIndex 0xc4
437 #define CQCI_TxCompletionThresholdMode (1U << 31)
438 #define CQCI_TxCompletionConsumerIndex(x) ((x) << 16)
439 #define CQCI_TxCompletionConsumerIndex_get(x) (((x) >> 16) & 0x7ff)
440 #define CQCI_RxCompletionQ1ThresholdMode (1U << 15)
441 #define CQCI_RxCompletionQ1ConsumerIndex(x) ((x) << 0)
442 #define CQCI_RxCompletionQ1ConsumerIndex_get(x) ((x) & 0x7ff)
444 #define SF_CompletionQueueProducerIndex 0xc8
445 #define CQPI_TxCompletionProducerIndex(x) ((x) << 16)
446 #define CQPI_TxCompletionProducerIndex_get(x) (((x) >> 16) & 0x7ff)
447 #define CQPI_RxCompletionQ1ProducerIndex(x) ((x) << 0)
448 #define CQPI_RxCompletionQ1ProducerIndex_get(x) ((x) & 0x7ff)
450 #define SF_RxHiPrCompletionPtrs 0xcc
451 #define RHPCP_RxCompletionQ2ProducerIndex(x) ((x) << 16)
452 #define RHPCP_RxCompletionQ2ThresholdMode (1U << 15)
453 #define RHPCP_RxCompletionQ2ConsumerIndex(x) ((x) << 0)
455 #define SF_RxDmaCtrl 0xd0
456 #define RDC_RxReportBadFrames (1U << 31)
457 #define RDC_RxDmaShortFrames (1U << 30)
458 #define RDC_RxDmaBadFrames (1U << 29)
459 #define RDC_RxDmaCrcErrorFrames (1U << 28)
460 #define RDC_RxDmaControlFrame (1U << 27)
461 #define RDC_RxDmaPauseFrame (1U << 26)
462 #define RDC_RxChecksumMode(x) ((x) << 24)
463 #define RDC_RxCompletionQ2Enable (1U << 23)
464 #define RDC_RxDmaQueueMode(x) ((x) << 20)
465 #define RDC_RxUseBackupQueue (1U << 19)
466 #define RDC_RxDmaCrc (1U << 18)
467 #define RDC_RxEarlyIntThreshold(x) ((x) << 12)
468 #define RDC_RxHighPriorityThreshold(x) ((x) << 8)
469 #define RDC_RxBurstSize(x) ((x) << 0)
471 #define SF_RxDescQueue1Ctrl 0xd4
472 #define RDQ1C_RxQ1BufferLength(x) ((x) << 16)
473 #define RDQ1C_RxPrefetchDescriptorsMode (1U << 15)
474 #define RDQ1C_RxDescQ1Entries (1U << 14)
475 #define RDQ1C_RxVariableSizeQueues (1U << 13)
476 #define RDQ1C_Rx64bitBufferAddresses (1U << 12)
477 #define RDQ1C_Rx64bitDescQueueAddress (1U << 11)
478 #define RDQ1C_RxDescSpacing(x) ((x) << 8)
479 #define RDQ1C_RxQ1ConsumerWe (1U << 7)
480 #define RDQ1C_RxQ1MinDescriptorsThreshold(x) ((x) << 0)
482 #define SF_RxDescQueue2Ctrl 0xd8
483 #define RDQ2C_RxQ2BufferLength(x) ((x) << 16)
484 #define RDQ2C_RxDescQ2Entries (1U << 14)
485 #define RDQ2C_RxQ2MinDescriptorsThreshold(x) ((x) << 0)
487 #define SF_RxDescQueueHighAddress 0xdc
489 #define SF_RxDescQueue1LowAddress 0xe0
491 #define SF_RxDescQueue2LowAddress 0xe4
493 #define SF_RxDescQueue1Ptrs 0xe8
494 #define RXQ1P_RxDescQ1Consumer(x) ((x) << 16)
495 #define RXQ1P_RxDescQ1Producer(x) ((x) << 0)
496 #define RXQ1P_RxDescQ1Producer_get(x) ((x) & 0x7ff)
498 #define SF_RxDescQueue2Ptrs 0xec
499 #define RXQ2P_RxDescQ2Consumer(x) ((x) << 16)
500 #define RXQ2P_RxDescQ2Producer(x) ((x) << 0)
502 #define SF_RxDmaStatus 0xf0
503 #define RDS_RxFramesLostCount(x) ((x) & 0xffff)
505 #define SF_RxAddressFilteringCtl 0xf4
506 #define RAFC_PerfectAddressPriority(x) (1U << ((x) + 16))
507 #define RAFC_MinVlanPriority(x) ((x) << 13)
508 #define RAFC_PassMulticastExceptBroadcast (1U << 12)
509 #define RAFC_WakeupMode(x) ((x) << 10)
510 #define RAFC_VlanMode(x) ((x) << 8)
511 #define RAFC_PerfectFilteringMode(x) ((x) << 6)
512 #define RAFC_HashFilteringMode(x) ((x) << 4)
513 #define RAFC_HashPriorityEnable (1U << 3)
514 #define RAFC_PassBroadcast (1U << 2)
515 #define RAFC_PassMulticast (1U << 1)
516 #define RAFC_PromiscuousMode (1U << 0)
518 #define SF_RxFrameTestOut 0xf8
521 * Additional PCI registers. To access these registers via I/O space,
522 * indirect access must be used.
524 #define SF_PciTargetStatus 0x100
526 #define SF_PciMasterStatus1 0x104
528 #define SF_PciMasterStatus2 0x108
530 #define SF_PciDmaLowHostAddr 0x10c
532 #define SF_BacDmaDiagnostic0 0x110
534 #define SF_BacDmaDiagnostic1 0x114
536 #define SF_BacDmaDiagnostic2 0x118
538 #define SF_BacDmaDiagnostic3 0x11c
540 #define SF_MacAddr1 0x120
542 #define SF_MacAddr2 0x124
544 #define SF_FunctionEvent 0x130
546 #define SF_FunctionEventMask 0x134
548 #define SF_FunctionPresentState 0x138
550 #define SF_ForceFunction 0x13c
552 #define SF_EEPROM_BASE 0x1000
554 #define SF_MII_BASE 0x2000
555 #define MiiDataValid (1U << 31)
556 #define MiiBusy (1U << 30)
557 #define MiiRegDataPort(x) ((x) & 0xffff)
559 #define SF_MII_PHY_REG(p, r) (SF_MII_BASE + \
560 ((p) * 32 * sizeof(uint32_t)) + \
561 ((r) * sizeof(uint32_t)))
563 #define SF_TestMode 0x4000
565 #define SF_RxFrameProcessorCtrl 0x4004
567 #define SF_TxFrameProcessorCtrl 0x4008
569 #define SF_MacConfig1 0x5000
570 #define MC1_SoftRst (1U << 15)
571 #define MC1_MiiLoopBack (1U << 14)
572 #define MC1_TestMode(x) ((x) << 12)
573 #define MC1_TxFlowEn (1U << 11)
574 #define MC1_RxFlowEn (1U << 10)
575 #define MC1_PreambleDetectCount (1U << 9)
576 #define MC1_PassAllRxPackets (1U << 8)
577 #define MC1_PurePreamble (1U << 7)
578 #define MC1_LengthCheck (1U << 6)
579 #define MC1_NoBackoff (1U << 5)
580 #define MC1_DelayCRC (1U << 4)
581 #define MC1_TxHalfDuplexJam (1U << 3)
582 #define MC1_PadEn (1U << 2)
583 #define MC1_FullDuplex (1U << 1)
584 #define MC1_HugeFrame (1U << 0)
586 #define SF_MacConfig2 0x5004
587 #define MC2_TxCRCerr (1U << 15)
588 #define MC2_TxIslCRCerr (1U << 14)
589 #define MC2_RxCRCerr (1U << 13)
590 #define MC2_RxIslCRCerr (1U << 12)
591 #define MC2_TXCF (1U << 11)
592 #define MC2_CtlSoftRst (1U << 10)
593 #define MC2_RxSoftRst (1U << 9)
594 #define MC2_TxSoftRst (1U << 8)
595 #define MC2_RxISLEn (1U << 7)
596 #define MC2_BackPressureNoBackOff (1U << 6)
597 #define MC2_AutoVlanPad (1U << 5)
598 #define MC2_MandatoryVLANPad (1U << 4)
599 #define MC2_TxISLAppen (1U << 3)
600 #define MC2_TxISLEn (1U << 2)
601 #define MC2_SimuRst (1U << 1)
602 #define MC2_TxXmtEn (1U << 0)
604 #define SF_BkToBkIPG 0x5008
606 #define SF_NonBkToBkIPG 0x500c
608 #define SF_ColRetry 0x5010
610 #define SF_MaxLength 0x5014
612 #define SF_TxNibbleCnt 0x5018
614 #define SF_TxByteCnt 0x501c
616 #define SF_ReTxCnt 0x5020
618 #define SF_RandomNumGen 0x5024
620 #define SF_MskRandomNum 0x5028
622 #define SF_TotalTxCnt 0x5034
624 #define SF_RxByteCnt 0x5040
626 #define SF_TxPauseTimer 0x5060
628 #define SF_VLANType 0x5064
630 #define SF_MiiStatus 0x5070
632 #define SF_PERFECT_BASE 0x6000
633 #define SF_PERFECT_SIZE 0x100
635 #define SF_HASH_BASE 0x6100
636 #define SF_HASH_SIZE 0x200
638 #define SF_STATS_BASE 0x7000
640 uint32_t TransmitOKFrames
;
641 uint32_t SingleCollisionFrames
;
642 uint32_t MultipleCollisionFrames
;
643 uint32_t TransmitCRCErrors
;
644 uint32_t TransmitOKOctets
;
645 uint32_t TransmitDeferredFrames
;
646 uint32_t TransmitLateCollisionCount
;
647 uint32_t TransmitPauseControlFrames
;
648 uint32_t TransmitControlFrames
;
649 uint32_t TransmitAbortDueToExcessiveCollisions
;
650 uint32_t TransmitAbortDueToExcessingDeferral
;
651 uint32_t MulticastFramesTransmittedOK
;
652 uint32_t BroadcastFramesTransmittedOK
;
653 uint32_t FramesLostDueToInternalTransmitErrors
;
654 uint32_t ReceiveOKFrames
;
655 uint32_t ReceiveCRCErrors
;
656 uint32_t AlignmentErrors
;
657 uint32_t ReceiveOKOctets
;
658 uint32_t PauseFramesReceivedOK
;
659 uint32_t ControlFramesReceivedOK
;
660 uint32_t ControlFramesReceivedWithUnsupportedOpcode
;
661 uint32_t ReceiveFramesTooLong
;
662 uint32_t ReceiveFramesTooShort
;
663 uint32_t ReceiveFramesJabbersError
;
664 uint32_t ReceiveFramesFragments
;
665 uint32_t ReceivePackets64Bytes
;
666 uint32_t ReceivePackets127Bytes
;
667 uint32_t ReceivePackets255Bytes
;
668 uint32_t ReceivePackets511Bytes
;
669 uint32_t ReceivePackets1023Bytes
;
670 uint32_t ReceivePackets1518Bytes
;
671 uint32_t FramesLostDueToInternalReceiveErrors
;
672 uint32_t TransmitFifoUnderflowCounts
;
675 #define SF_TxGfpMem 0x8000
677 #define SF_RxGfpMem 0xa000
679 #endif /* _DEV_IC_AIC6915REG_H_ */