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[netbsd-mini2440.git] / sys / dev / ic / aic79xxvar.h
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1 /*
2 * Core definitions and data structures sharable across OS platforms.
3 *
4 * Copyright (c) 1994-2002 Justin T. Gibbs.
5 * Copyright (c) 2000-2002 Adaptec Inc.
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions, and the following disclaimer,
13 * without modification.
14 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
15 * substantially similar to the "NO WARRANTY" disclaimer below
16 * ("Disclaimer") and any redistribution must be conditioned upon
17 * including a substantially similar Disclaimer requirement for further
18 * binary redistribution.
19 * 3. Neither the names of the above-listed copyright holders nor the names
20 * of any contributors may be used to endorse or promote products derived
21 * from this software without specific prior written permission.
22 *
23 * Alternatively, this software may be distributed under the terms of the
24 * GNU General Public License ("GPL") version 2 as published by the Free
25 * Software Foundation.
26 *
27 * NO WARRANTY
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
37 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
38 * POSSIBILITY OF SUCH DAMAGES.
39 *
40 * Id: //depot/aic7xxx/aic7xxx/aic79xx.h#94 $
41 *
42 * $FreeBSD: src/sys/dev/aic7xxx/aic79xx.h,v 1.15 2003/06/28 04:45:25 gibbs Exp $
43 */
44 /*
45 * Ported from FreeBSD by Pascal Renauld, Network Storage Solutions, Inc. - April 2003
46 */
47
48 #ifndef _AIC79XXVAR_H_
49 #define _AIC79XXVAR_H_
50
51 /* Register Definitions */
52 #include <dev/microcode/aic7xxx/aic79xx_reg.h>
53
54 /************************* Forward Declarations *******************************/
55 struct ahd_platform_data;
56 struct scb_platform_data;
57
58 /****************************** Useful Macros *********************************/
59 #ifndef MAX
60 #define MAX(a,b) (((a) > (b)) ? (a) : (b))
61 #endif
62
63 #ifndef MIN
64 #define MIN(a,b) (((a) < (b)) ? (a) : (b))
65 #endif
66
67 #ifndef TRUE
68 #define TRUE 1
69 #endif
70 #ifndef FALSE
71 #define FALSE 0
72 #endif
73
74 #define NUM_ELEMENTS(array) (sizeof(array) / sizeof(*array))
75
76 #define ALL_CHANNELS '\0'
77 #define ALL_TARGETS_MASK 0xFFFF
78 #define INITIATOR_WILDCARD (~0)
79 #define SCB_LIST_NULL 0xFF00
80 #define SCB_LIST_NULL_LE (ahd_htole16(SCB_LIST_NULL))
81 #define QOUTFIFO_ENTRY_VALID 0x8000
82 #define QOUTFIFO_ENTRY_VALID_LE (ahd_htole16(0x8000))
83 #define SCBID_IS_NULL(scbid) (((scbid) & 0xFF00 ) == SCB_LIST_NULL)
84
85 #define SCSIID_TARGET(ahd, scsiid) \
86 (((scsiid) & TID) >> TID_SHIFT)
87 #define SCSIID_OUR_ID(scsiid) \
88 ((scsiid) & OID)
89 #define SCSIID_CHANNEL(ahd, scsiid) ('A')
90 #define SCB_IS_SCSIBUS_B(ahd, scb) (0)
91 #define SCB_GET_OUR_ID(scb) \
92 SCSIID_OUR_ID((scb)->hscb->scsiid)
93 #define SCB_GET_TARGET(ahd, scb) \
94 SCSIID_TARGET((ahd), (scb)->hscb->scsiid)
95 #define SCB_GET_CHANNEL(ahd, scb) \
96 SCSIID_CHANNEL(ahd, (scb)->hscb->scsiid)
97 #define SCB_GET_LUN(scb) \
98 ((scb)->hscb->lun)
99 #define SCB_GET_TARGET_OFFSET(ahd, scb) \
100 SCB_GET_TARGET(ahd, scb)
101 #define SCB_GET_TARGET_MASK(ahd, scb) \
102 (0x01 << (SCB_GET_TARGET_OFFSET(ahd, scb)))
103 #ifdef AHD_DEBUG
104 #define SCB_IS_SILENT(scb) \
105 ((ahd_debug & AHD_SHOW_MASKED_ERRORS) == 0 \
106 && (((scb)->flags & SCB_SILENT) != 0))
107 #else
108 #define SCB_IS_SILENT(scb) \
109 (((scb)->flags & SCB_SILENT) != 0)
110 #endif
111 /*
112 * TCLs have the following format: TTTTLLLLLLLL
113 */
114 #define TCL_TARGET_OFFSET(tcl) \
115 ((((tcl) >> 4) & TID) >> 4)
116 #define TCL_LUN(tcl) \
117 (tcl & (AHD_NUM_LUNS - 1))
118 #define BUILD_TCL(scsiid, lun) \
119 ((lun) | (((scsiid) & TID) << 4))
120 #define BUILD_TCL_RAW(target, channel, lun) \
121 ((lun) | ((target) << 8))
122
123 #define SCB_GET_TAG(scb) \
124 ahd_le16toh(scb->hscb->tag)
125
126 #ifndef AHD_TARGET_MODE
127 #undef AHD_TMODE_ENABLE
128 #define AHD_TMODE_ENABLE 0
129 #endif
130
131 #define AHD_BUILD_COL_IDX(target, lun) \
132 (((lun) << 4) | target)
133
134 #define AHD_GET_SCB_COL_IDX(ahd, scb) \
135 ((SCB_GET_LUN(scb) << 4) | SCB_GET_TARGET(ahd, scb))
136
137 #define AHD_SET_SCB_COL_IDX(scb, col_idx) \
138 do { \
139 (scb)->hscb->scsiid = ((col_idx) << TID_SHIFT) & TID; \
140 (scb)->hscb->lun = ((col_idx) >> 4) & (AHD_NUM_LUNS_NONPKT-1); \
141 } while (0)
142
143 #define AHD_COPY_SCB_COL_IDX(dst, src) \
144 do { \
145 dst->hscb->scsiid = src->hscb->scsiid; \
146 dst->hscb->lun = src->hscb->lun; \
147 } while (0)
148
149 #define AHD_NEVER_COL_IDX 0xFFFF
150
151 /**************************** Driver Constants ********************************/
152 /*
153 * The maximum number of supported targets.
154 */
155 #define AHD_NUM_TARGETS 16
156
157 /*
158 * The maximum number of supported luns.
159 * The identify message only supports 64 luns in non-packetized transfers.
160 * You can have 2^64 luns when information unit transfers are enabled,
161 * but until we see a need to support that many, we support 256.
162 */
163 #define AHD_NUM_LUNS_NONPKT 64
164 #define AHD_NUM_LUNS 256
165
166 /*
167 * The maximum transfer per S/G segment.
168 * Limited by MAXPHYS or a 24bit counter.
169 */
170 #define AHD_MAXTRANSFER_SIZE MIN(MAXPHYS,0x00ffffff)
171
172 /*
173 * The maximum amount of SCB storage in hardware on a controller.
174 * This value represents an upper bound. Due to software design,
175 * we may not be able to use this number.
176 */
177 #define AHD_SCB_MAX 512
178
179 /*
180 * The maximum number of concurrent transactions supported per driver instance.
181 * Sequencer Control Blocks (SCBs) store per-transaction information.
182 */
183 #define AHD_MAX_QUEUE AHD_SCB_MAX
184
185 /*
186 * Define the size of our QIN and QOUT FIFOs. They must be a power of 2
187 * in size and accommodate as many transactions as can be queued concurrently.
188 */
189 #define AHD_QIN_SIZE AHD_MAX_QUEUE
190 #define AHD_QOUT_SIZE AHD_MAX_QUEUE
191
192 #define AHD_QIN_WRAP(x) ((x) & (AHD_QIN_SIZE-1))
193 /*
194 * The maximum amount of SCB storage we allocate in host memory.
195 */
196 #define AHD_SCB_MAX_ALLOC AHD_MAX_QUEUE
197
198 /*
199 * Ring Buffer of incoming target commands.
200 * We allocate 256 to simplify the logic in the sequencer
201 * by using the natural wrap point of an 8bit counter.
202 */
203 #define AHD_TMODE_CMDS 256
204
205 /* Reset line assertion time in us */
206 #define AHD_BUSRESET_DELAY 25
207
208 /******************* Chip Characteristics/Operating Settings *****************/
209 /*
210 * Chip Type
211 * The chip order is from least sophisticated to most sophisticated.
212 */
213 typedef enum {
214 AHD_NONE = 0x0000,
215 AHD_CHIPID_MASK = 0x00FF,
216 AHD_AIC7901 = 0x0001,
217 AHD_AIC7902 = 0x0002,
218 AHD_AIC7901A = 0x0003,
219 AHD_PCI = 0x0100, /* Bus type PCI */
220 AHD_PCIX = 0x0200, /* Bus type PCIX */
221 AHD_BUS_MASK = 0x0F00
222 } ahd_chip;
223
224 /*
225 * Features available in each chip type.
226 */
227 typedef enum {
228 AHD_FENONE = 0x00000,
229 AHD_WIDE = 0x00001,/* Wide Channel */
230 AHD_MULTI_FUNC = 0x00100,/* Multi-Function/Channel Device */
231 AHD_TARGETMODE = 0x01000,/* Has tested target mode support */
232 AHD_MULTIROLE = 0x02000,/* Space for two roles at a time */
233 AHD_RTI = 0x04000,/* Retained Training Support */
234 AHD_NEW_IOCELL_OPTS = 0x08000,/* More Signal knobs in the IOCELL */
235 AHD_NEW_DFCNTRL_OPTS = 0x10000,/* SCSIENWRDIS bit */
236 AHD_REMOVABLE = 0x00000,/* Hot-Swap supported - None so far*/
237 AHD_AIC7901_FE = AHD_FENONE,
238 AHD_AIC7901A_FE = AHD_FENONE,
239 AHD_AIC7902_FE = AHD_MULTI_FUNC
240 } ahd_feature;
241
242 /*
243 * Bugs in the silicon that we work around in software.
244 */
245 typedef enum {
246 AHD_BUGNONE = 0x0000,
247 /*
248 * Rev A hardware fails to update LAST/CURR/NEXTSCB
249 * correctly in certain packetized selection cases.
250 */
251 AHD_SENT_SCB_UPDATE_BUG = 0x0001,
252 /* The wrong SCB is accessed to check the abort pending bit. */
253 AHD_ABORT_LQI_BUG = 0x0002,
254 /* Packetized bitbucket crosses packet boundaries. */
255 AHD_PKT_BITBUCKET_BUG = 0x0004,
256 /* The selection timer runs twice as long as its setting. */
257 AHD_LONG_SETIMO_BUG = 0x0008,
258 /* The Non-LQ CRC error status is delayed until phase change. */
259 AHD_NLQICRC_DELAYED_BUG = 0x0010,
260 /* The chip must be reset for all outgoing bus resets. */
261 AHD_SCSIRST_BUG = 0x0020,
262 /* Some PCIX fields must be saved and restored across chip reset. */
263 AHD_PCIX_CHIPRST_BUG = 0x0040,
264 /* MMAPIO is not functional in PCI-X mode. */
265 AHD_PCIX_MMAPIO_BUG = 0x0080,
266 /* Reads to SCBRAM fail to reset the discard timer. */
267 AHD_PCIX_SCBRAM_RD_BUG = 0x0100,
268 /* Bug workarounds that can be disabled on non-PCIX busses. */
269 AHD_PCIX_BUG_MASK = AHD_PCIX_CHIPRST_BUG
270 | AHD_PCIX_MMAPIO_BUG
271 | AHD_PCIX_SCBRAM_RD_BUG,
272 /*
273 * LQOSTOP0 status set even for forced selections with ATN
274 * to perform non-packetized message delivery.
275 */
276 AHD_LQO_ATNO_BUG = 0x0200,
277 /* FIFO auto-flush does not always trigger. */
278 AHD_AUTOFLUSH_BUG = 0x0400,
279 /* The CLRLQO registers are not self-clearing. */
280 AHD_CLRLQO_AUTOCLR_BUG = 0x0800,
281 /* The PACKETIZED status bit refers to the previous connection. */
282 AHD_PKTIZED_STATUS_BUG = 0x1000,
283 /* "Short Luns" are not placed into outgoing LQ packets correctly. */
284 AHD_PKT_LUN_BUG = 0x2000,
285 /*
286 * Only the FIFO allocated to the non-packetized connection may
287 * be in use during a non-packetzied connection.
288 */
289 AHD_NONPACKFIFO_BUG = 0x4000,
290 /*
291 * Writing to a DFF SCBPTR register may fail if concurent with
292 * a hardware write to the other DFF SCBPTR register. This is
293 * not currently a concern in our sequencer since all chips with
294 * this bug have the AHD_NONPACKFIFO_BUG and all writes of concern
295 * occur in non-packetized connections.
296 */
297 AHD_MDFF_WSCBPTR_BUG = 0x8000,
298 /* SGHADDR updates are slow. */
299 AHD_REG_SLOW_SETTLE_BUG = 0x10000,
300 /*
301 * Changing the MODE_PTR coincident with an interrupt that
302 * switches to a different mode will cause the interrupt to
303 * be in the mode written outside of interrupt context.
304 */
305 AHD_SET_MODE_BUG = 0x20000,
306 /* Non-packetized busfree revision does not work. */
307 AHD_BUSFREEREV_BUG = 0x40000,
308 /*
309 * Paced transfers are indicated with a non-standard PPR
310 * option bit in the neg table, 160MHz is indicated by
311 * sync factor 0x7, and the offset if off by a factor of 2.
312 */
313 AHD_PACED_NEGTABLE_BUG = 0x80000,
314 /* LQOOVERRUN false positives. */
315 AHD_LQOOVERRUN_BUG = 0x100000,
316 /*
317 * Controller write to INTSTAT will lose to a host
318 * write to CLRINT.
319 */
320 AHD_INTCOLLISION_BUG = 0x200000,
321 /*
322 * The GEM318 violates the SCSI spec by not waiting
323 * the mandated bus settle delay between phase changes
324 * in some situations. Some aic79xx chip revs. are more
325 * strict in this regard and will treat REQ assertions
326 * that fall within the bus settle delay window as
327 * glitches. This flag tells the firmware to tolerate
328 * early REQ assertions.
329 */
330 AHD_EARLY_REQ_BUG = 0x400000,
331 /*
332 * The LED does not stay on long enough in packetized modes.
333 */
334 AHD_FAINT_LED_BUG = 0x800000
335 } ahd_bug;
336
337 /*
338 * Configuration specific settings.
339 * The driver determines these settings by probing the
340 * chip/controller's configuration.
341 */
342 typedef enum {
343 AHD_FNONE = 0x00000,
344 AHD_BOOT_CHANNEL = 0x00001,/* We were set as the boot channel. */
345 AHD_USEDEFAULTS = 0x00004,/*
346 * For cards without an seeprom
347 * or a BIOS to initialize the chip's
348 * SRAM, we use the default target
349 * settings.
350 */
351 AHD_SEQUENCER_DEBUG = 0x00008,
352 AHD_RESET_BUS_A = 0x00010,
353 AHD_EXTENDED_TRANS_A = 0x00020,
354 AHD_TERM_ENB_A = 0x00040,
355 AHD_SPCHK_ENB_A = 0x00080,
356 AHD_STPWLEVEL_A = 0x00100,
357 AHD_INITIATORROLE = 0x00200,/*
358 * Allow initiator operations on
359 * this controller.
360 */
361 AHD_TARGETROLE = 0x00400,/*
362 * Allow target operations on this
363 * controller.
364 */
365 AHD_RESOURCE_SHORTAGE = 0x00800,
366 AHD_TQINFIFO_BLOCKED = 0x01000,/* Blocked waiting for ATIOs */
367 AHD_INT50_SPEEDFLEX = 0x02000,/*
368 * Internal 50pin connector
369 * sits behind an aic3860
370 */
371 AHD_BIOS_ENABLED = 0x04000,
372 AHD_ALL_INTERRUPTS = 0x08000,
373 AHD_39BIT_ADDRESSING = 0x10000,/* Use 39 bit addressing scheme. */
374 AHD_64BIT_ADDRESSING = 0x20000,/* Use 64 bit addressing scheme. */
375 AHD_CURRENT_SENSING = 0x40000,
376 AHD_SCB_CONFIG_USED = 0x80000,/* No SEEPROM but SCB had info. */
377 AHD_HP_BOARD = 0x100000,
378 AHD_RESET_POLL_ACTIVE = 0x200000,
379 AHD_UPDATE_PEND_CMDS = 0x400000,
380 AHD_RUNNING_QOUTFIFO = 0x800000,
381 AHD_HAD_FIRST_SEL = 0x1000000
382 } ahd_flag;
383
384 /************************* Hardware SCB Definition ***************************/
385
386 /*
387 * The driver keeps up to MAX_SCB scb structures per card in memory. The SCB
388 * consists of a "hardware SCB" mirroring the fields available on the card
389 * and additional information the kernel stores for each transaction.
390 *
391 * To minimize space utilization, a portion of the hardware scb stores
392 * different data during different portions of a SCSI transaction.
393 * As initialized by the host driver for the initiator role, this area
394 * contains the SCSI cdb (or a pointer to the cdb) to be executed. After
395 * the cdb has been presented to the target, this area serves to store
396 * residual transfer information and the SCSI status byte.
397 * For the target role, the contents of this area do not change, but
398 * still serve a different purpose than for the initiator role. See
399 * struct target_data for details.
400 */
401
402 /*
403 * Status information embedded in the shared portion of
404 * an SCB after passing the cdb to the target. The kernel
405 * driver will only read this data for transactions that
406 * complete abnormally.
407 */
408 struct initiator_status {
409 uint32_t residual_datacnt; /* Residual in the current S/G seg */
410 uint32_t residual_sgptr; /* The next S/G for this transfer */
411 uint8_t scsi_status; /* Standard SCSI status byte */
412 };
413
414 struct target_status {
415 uint32_t residual_datacnt; /* Residual in the current S/G seg */
416 uint32_t residual_sgptr; /* The next S/G for this transfer */
417 uint8_t scsi_status; /* SCSI status to give to initiator */
418 uint8_t target_phases; /* Bitmap of phases to execute */
419 uint8_t data_phase; /* Data-In or Data-Out */
420 uint8_t initiator_tag; /* Initiator's transaction tag */
421 };
422
423 /*
424 * Initiator mode SCB shared data area.
425 * If the embedded CDB is 12 bytes or less, we embed
426 * the sense buffer address in the SCB. This allows
427 * us to retrieve sense information without interrupting
428 * the host in packetized mode.
429 */
430 typedef uint32_t sense_addr_t;
431 #define MAX_CDB_LEN 16
432 #define MAX_CDB_LEN_WITH_SENSE_ADDR (MAX_CDB_LEN - sizeof(sense_addr_t))
433 union initiator_data {
434 struct {
435 uint64_t cdbptr;
436 uint8_t cdblen;
437 } cdb_from_host;
438 uint8_t cdb[MAX_CDB_LEN];
439 struct {
440 uint8_t cdb[MAX_CDB_LEN_WITH_SENSE_ADDR];
441 sense_addr_t sense_addr;
442 } cdb_plus_saddr;
443 };
444
445 /*
446 * Target mode version of the shared data SCB segment.
447 */
448 struct target_data {
449 uint32_t spare[2];
450 uint8_t scsi_status; /* SCSI status to give to initiator */
451 uint8_t target_phases; /* Bitmap of phases to execute */
452 uint8_t data_phase; /* Data-In or Data-Out */
453 uint8_t initiator_tag; /* Initiator's transaction tag */
454 };
455
456 struct hardware_scb {
457 /*0*/ union {
458 union initiator_data idata;
459 struct target_data tdata;
460 struct initiator_status istatus;
461 struct target_status tstatus;
462 } shared_data;
463 /*
464 * A word about residuals.
465 * The scb is presented to the sequencer with the dataptr and datacnt
466 * fields initialized to the contents of the first S/G element to
467 * transfer. The sgptr field is initialized to the bus address for
468 * the S/G element that follows the first in the in core S/G array
469 * or'ed with the SG_FULL_RESID flag. Sgptr may point to an invalid
470 * S/G entry for this transfer (single S/G element transfer with the
471 * first elements address and length preloaded in the dataptr/datacnt
472 * fields). If no transfer is to occur, sgptr is set to SG_LIST_NULL.
473 * The SG_FULL_RESID flag ensures that the residual will be correctly
474 * noted even if no data transfers occur. Once the data phase is entered,
475 * the residual sgptr and datacnt are loaded from the sgptr and the
476 * datacnt fields. After each S/G element's dataptr and length are
477 * loaded into the hardware, the residual sgptr is advanced. After
478 * each S/G element is expired, its datacnt field is checked to see
479 * if the LAST_SEG flag is set. If so, SG_LIST_NULL is set in the
480 * residual sg ptr and the transfer is considered complete. If the
481 * sequencer determines that there is a residual in the transfer, or
482 * there is non-zero status, it will set the SG_STATUS_VALID flag in
483 * sgptr and DMA the scb back into host memory. To summarize:
484 *
485 * Sequencer:
486 * o A residual has occurred if SG_FULL_RESID is set in sgptr,
487 * or residual_sgptr does not have SG_LIST_NULL set.
488 *
489 * o We are transfering the last segment if residual_datacnt has
490 * the SG_LAST_SEG flag set.
491 *
492 * Host:
493 * o A residual can only have occurred if a completed scb has the
494 * SG_STATUS_VALID flag set. Inspection of the SCSI status field,
495 * the residual_datacnt, and the residual_sgptr field will tell
496 * for sure.
497 *
498 * o residual_sgptr and sgptr refer to the "next" sg entry
499 * and so may point beyond the last valid sg entry for the
500 * transfer.
501 */
502 #define SG_PTR_MASK 0xFFFFFFF8
503 /*16*/ uint16_t tag; /* Reused by Sequencer. */
504 /*18*/ uint8_t control; /* See SCB_CONTROL in aic79xx.reg for details */
505 /*19*/ uint8_t scsiid; /*
506 * Selection out Id
507 * Our Id (bits 0-3) Their ID (bits 4-7)
508 */
509 /*20*/ uint8_t lun;
510 /*21*/ uint8_t task_attribute;
511 /*22*/ uint8_t cdb_len;
512 /*23*/ uint8_t task_management;
513 /*24*/ uint64_t dataptr;
514 /*32*/ uint32_t datacnt; /* Byte 3 is spare. */
515 /*36*/ uint32_t sgptr;
516 /*40*/ uint32_t hscb_busaddr;
517 /*44*/ uint32_t next_hscb_busaddr;
518 /********** Long lun field only downloaded for full 8 byte lun support ********/
519 /*48*/ uint8_t pkt_long_lun[8];
520 /******* Fields below are not Downloaded (Sequencer may use for scratch) ******/
521 /*56*/ uint8_t spare[8];
522 };
523
524 /************************ Kernel SCB Definitions ******************************/
525 /*
526 * Some fields of the SCB are OS dependent. Here we collect the
527 * definitions for elements that all OS platforms need to include
528 * in there SCB definition.
529 */
530
531 /*
532 * Definition of a scatter/gather element as transferred to the controller.
533 * The aic7xxx chips only support a 24bit length. We use the top byte of
534 * the length to store additional address bits and a flag to indicate
535 * that a given segment terminates the transfer. This gives us an
536 * addressable range of 512GB on machines with 64bit PCI or with chips
537 * that can support dual address cycles on 32bit PCI busses.
538 */
539 struct ahd_dma_seg {
540 uint32_t addr;
541 uint32_t len;
542 #define AHD_DMA_LAST_SEG 0x80000000
543 #define AHD_SG_HIGH_ADDR_MASK 0x7F000000
544 #define AHD_SG_LEN_MASK 0x00FFFFFF
545 };
546
547 struct ahd_dma64_seg {
548 uint64_t addr;
549 uint32_t len;
550 uint32_t pad;
551 };
552
553 struct map_node {
554 bus_dmamap_t dmamap;
555 bus_addr_t physaddr;
556 uint8_t *vaddr;
557 bus_dma_segment_t dmasegs;
558 int nseg;
559 SLIST_ENTRY(map_node) links;
560 };
561
562 struct ahd_pci_busdata {
563 pci_chipset_tag_t pc;
564 pcitag_t tag;
565 u_int dev;
566 u_int func;
567 int pcix_off;
568 };
569
570 /*
571 * The current state of this SCB.
572 */
573 typedef enum {
574 SCB_FLAG_NONE = 0x00000,
575 SCB_TRANSMISSION_ERROR = 0x00001,/*
576 * We detected a parity or CRC
577 * error that has effected the
578 * payload of the command. This
579 * flag is checked when normal
580 * status is returned to catch
581 * the case of a target not
582 * responding to our attempt
583 * to report the error.
584 */
585 SCB_OTHERTCL_TIMEOUT = 0x00002,/*
586 * Another device was active
587 * during the first timeout for
588 * this SCB so we gave ourselves
589 * an additional timeout period
590 * in case it was hogging the
591 * bus.
592 */
593 SCB_DEVICE_RESET = 0x00004,
594 SCB_SENSE = 0x00008,
595 SCB_CDB32_PTR = 0x00010,
596 SCB_RECOVERY_SCB = 0x00020,
597 SCB_AUTO_NEGOTIATE = 0x00040,/* Negotiate to achieve goal. */
598 SCB_NEGOTIATE = 0x00080,/* Negotiation forced for command. */
599 SCB_ABORT = 0x00100,
600 SCB_ACTIVE = 0x00200,
601 SCB_TARGET_IMMEDIATE = 0x00400,
602 SCB_PACKETIZED = 0x00800,
603 SCB_EXPECT_PPR_BUSFREE = 0x01000,
604 SCB_PKT_SENSE = 0x02000,
605 SCB_CMDPHASE_ABORT = 0x04000,
606 SCB_ON_COL_LIST = 0x08000,
607 SCB_SILENT = 0x10000,/*
608 * Be quiet about transmission type
609 * errors. They are expected and we
610 * don't want to upset the user. This
611 * flag is typically used during DV.
612 */
613 SCB_FREEZE_QUEUE = 0x20000,
614 SCB_REQUEUE = 0x40000,
615 } scb_flag;
616
617 struct scb {
618 struct hardware_scb *hscb;
619 union {
620 SLIST_ENTRY(scb) sle;
621 LIST_ENTRY(scb) le;
622 TAILQ_ENTRY(scb) tqe;
623 } links;
624 union {
625 SLIST_ENTRY(scb) sle;
626 LIST_ENTRY(scb) le;
627 TAILQ_ENTRY(scb) tqe;
628 } links2;
629 #define pending_links links2.le
630 #define collision_links links2.le
631 struct scb *col_scb;
632 struct scsipi_xfer *xs;
633
634 struct ahd_softc *ahd_softc;
635 scb_flag flags;
636 bus_dmamap_t dmamap;
637 struct scb_platform_data *platform_data;
638 struct map_node *hscb_map;
639 struct map_node *sg_map;
640 struct map_node *sense_map;
641 void *sg_list;
642 uint8_t *sense_data;
643 bus_addr_t sg_list_busaddr;
644 bus_addr_t sense_busaddr;
645 u_int sg_count;/* How full ahd_dma_seg is */
646 #define AHD_MAX_LQ_CRC_ERRORS 5
647 u_int crc_retry_count;
648 };
649
650 TAILQ_HEAD(scb_tailq, scb);
651 LIST_HEAD(scb_list, scb);
652
653 struct scb_data {
654 /*
655 * TAILQ of lists of free SCBs grouped by device
656 * collision domains.
657 */
658 struct scb_tailq free_scbs;
659
660 /*
661 * Per-device lists of SCBs whose tag ID would collide
662 * with an already active tag on the device.
663 */
664 struct scb_list free_scb_lists[AHD_NUM_TARGETS * AHD_NUM_LUNS_NONPKT];
665
666 /*
667 * SCBs that will not collide with any active device.
668 */
669 struct scb_list any_dev_free_scb_list;
670
671 /*
672 * Mapping from tag to SCB.
673 */
674 struct scb *scbindex[AHD_SCB_MAX];
675
676 SLIST_HEAD(, map_node) hscb_maps;
677 SLIST_HEAD(, map_node) sg_maps;
678 SLIST_HEAD(, map_node) sense_maps;
679
680 int scbs_left; /* unallocated scbs in head map_node */
681 int sgs_left; /* unallocated sgs in head map_node */
682 int sense_left; /* unallocated sense in head map_node */
683 uint16_t numscbs;
684 uint16_t maxhscbs; /* Number of SCBs on the card */
685 uint8_t init_level; /*
686 * How far we've initialized
687 * this structure.
688 */
689 };
690
691 /************************ Target Mode Definitions *****************************/
692
693 /*
694 * Connection desciptor for select-in requests in target mode.
695 */
696 struct target_cmd {
697 uint8_t scsiid; /* Our ID and the initiator's ID */
698 uint8_t identify; /* Identify message */
699 uint8_t bytes[22]; /*
700 * Bytes contains any additional message
701 * bytes terminated by 0xFF. The remainder
702 * is the cdb to execute.
703 */
704 uint8_t cmd_valid; /*
705 * When a command is complete, the firmware
706 * will set cmd_valid to all bits set.
707 * After the host has seen the command,
708 * the bits are cleared. This allows us
709 * to just peek at host memory to determine
710 * if more work is complete. cmd_valid is on
711 * an 8 byte boundary to simplify setting
712 * it on aic7880 hardware which only has
713 * limited direct access to the DMA FIFO.
714 */
715 uint8_t pad[7];
716 };
717
718 /*
719 * Number of events we can buffer up if we run out
720 * of immediate notify ccbs.
721 */
722 #define AHD_TMODE_EVENT_BUFFER_SIZE 8
723 struct ahd_tmode_event {
724 uint8_t initiator_id;
725 uint8_t event_type; /* MSG type or EVENT_TYPE_BUS_RESET */
726 #define EVENT_TYPE_BUS_RESET 0xFF
727 uint8_t event_arg;
728 };
729
730 /*
731 * Per enabled lun target mode state.
732 * As this state is directly influenced by the host OS'es target mode
733 * environment, we let the OS module define it. Forward declare the
734 * structure here so we can store arrays of them, etc. in OS neutral
735 * data structures.
736 */
737 #ifdef AHD_TARGET_MODE
738 struct ahd_tmode_lstate {
739 struct cam_path *path;
740 struct ccb_hdr_slist accept_tios;
741 struct ccb_hdr_slist immed_notifies;
742 struct ahd_tmode_event event_buffer[AHD_TMODE_EVENT_BUFFER_SIZE];
743 uint8_t event_r_idx;
744 uint8_t event_w_idx;
745 };
746 #else
747 struct ahd_tmode_lstate;
748 #endif
749
750 /******************** Transfer Negotiation Datastructures *********************/
751 #define AHD_TRANS_CUR 0x01 /* Modify current negotiation status */
752 #define AHD_TRANS_ACTIVE 0x03 /* Assume this target is on the bus */
753 #define AHD_TRANS_GOAL 0x04 /* Modify negontiation goal */
754 #define AHD_TRANS_USER 0x08 /* Modify user negotiation settings */
755 #define AHD_PERIOD_10MHz 0x19
756
757 #define AHD_WIDTH_UNKNOWN 0xFF
758 #define AHD_PERIOD_UNKNOWN 0xFF
759 #define AHD_OFFSET_UNKNOWN 0xFF
760 #define AHD_PPR_OPTS_UNKNOWN 0xFF
761
762 /*
763 * Transfer Negotiation Information.
764 */
765 struct ahd_transinfo {
766 uint8_t protocol_version; /* SCSI Revision level */
767 uint8_t transport_version; /* SPI Revision level */
768 uint8_t width; /* Bus width */
769 uint8_t period; /* Sync rate factor */
770 uint8_t offset; /* Sync offset */
771 uint8_t ppr_options; /* Parallel Protocol Request options */
772 };
773
774 /*
775 * Per-initiator current, goal and user transfer negotiation information. */
776 struct ahd_initiator_tinfo {
777 struct ahd_transinfo curr;
778 struct ahd_transinfo goal;
779 struct ahd_transinfo user;
780 };
781
782 /*
783 * Per enabled target ID state.
784 * Pointers to lun target state as well as sync/wide negotiation information
785 * for each initiator<->target mapping. For the initiator role we pretend
786 * that we are the target and the targets are the initiators since the
787 * negotiation is the same regardless of role.
788 */
789 struct ahd_tmode_tstate {
790 struct ahd_tmode_lstate* enabled_luns[AHD_NUM_LUNS];
791 struct ahd_initiator_tinfo transinfo[AHD_NUM_TARGETS];
792
793 /*
794 * Per initiator state bitmasks.
795 */
796 uint16_t auto_negotiate;/* Auto Negotiation Required */
797 uint16_t discenable; /* Disconnection allowed */
798 uint16_t tagenable; /* Tagged Queuing allowed */
799 };
800
801 /*
802 * Points of interest along the negotiated transfer scale.
803 */
804 #define AHD_SYNCRATE_160 0x8
805 #define AHD_SYNCRATE_PACED 0x8
806 #define AHD_SYNCRATE_DT 0x9
807 #define AHD_SYNCRATE_ULTRA2 0xa
808 #define AHD_SYNCRATE_ULTRA 0xc
809 #define AHD_SYNCRATE_FAST 0x19
810 #define AHD_SYNCRATE_MIN_DT AHD_SYNCRATE_FAST
811 #define AHD_SYNCRATE_SYNC 0x32
812 #define AHD_SYNCRATE_MIN 0x60
813 #define AHD_SYNCRATE_ASYNC 0xFF
814 #define AHD_SYNCRATE_MAX AHD_SYNCRATE_160
815
816 /* Safe and valid period for async negotiations. */
817 #define AHD_ASYNC_XFER_PERIOD 0x44
818
819 /*
820 * In RevA, the synctable uses a 120MHz rate for the period
821 * factor 8 and 160MHz for the period factor 7. The 120MHz
822 * rate never made it into the official SCSI spec, so we must
823 * compensate when setting the negotiation table for Rev A
824 * parts.
825 */
826 #define AHD_SYNCRATE_REVA_120 0x8
827 #define AHD_SYNCRATE_REVA_160 0x7
828
829 /***************************** Lookup Tables **********************************/
830 /*
831 * Phase -> name and message out response
832 * to parity errors in each phase table.
833 */
834 struct ahd_phase_table_entry {
835 uint8_t phase;
836 uint8_t mesg_out; /* Message response to parity errors */
837 const char *phasemsg;
838 };
839
840 /************************** Serial EEPROM Format ******************************/
841
842 struct seeprom_config {
843 /*
844 * Per SCSI ID Configuration Flags
845 */
846 uint16_t device_flags[16]; /* words 0-15 */
847 #define CFXFER 0x003F /* synchronous transfer rate */
848 #define CFXFER_ASYNC 0x3F
849 #define CFQAS 0x0040 /* Negotiate QAS */
850 #define CFPACKETIZED 0x0080 /* Negotiate Packetized Transfers */
851 #define CFSTART 0x0100 /* send start unit SCSI command */
852 #define CFINCBIOS 0x0200 /* include in BIOS scan */
853 #define CFDISC 0x0400 /* enable disconnection */
854 #define CFMULTILUNDEV 0x0800 /* Probe multiple luns in BIOS scan */
855 #define CFWIDEB 0x1000 /* wide bus device */
856 #define CFHOSTMANAGED 0x8000 /* Managed by a RAID controller */
857
858 /*
859 * BIOS Control Bits
860 */
861 uint16_t bios_control; /* word 16 */
862 #define CFSUPREM 0x0001 /* support all removable drives */
863 #define CFSUPREMB 0x0002 /* support removable boot drives */
864 #define CFBIOSSTATE 0x000C /* BIOS Action State */
865 #define CFBS_DISABLED 0x00
866 #define CFBS_ENABLED 0x04
867 #define CFBS_DISABLED_SCAN 0x08
868 #define CFENABLEDV 0x0010 /* Perform Domain Validation */
869 #define CFCTRL_A 0x0020 /* BIOS displays Ctrl-A message */
870 #define CFSPARITY 0x0040 /* SCSI parity */
871 #define CFEXTEND 0x0080 /* extended translation enabled */
872 #define CFBOOTCD 0x0100 /* Support Bootable CD-ROM */
873 #define CFMSG_LEVEL 0x0600 /* BIOS Message Level */
874 #define CFMSG_VERBOSE 0x0000
875 #define CFMSG_SILENT 0x0200
876 #define CFMSG_DIAG 0x0400
877 #define CFRESETB 0x0800 /* reset SCSI bus at boot */
878 /* UNUSED 0xf000 */
879
880 /*
881 * Host Adapter Control Bits
882 */
883 uint16_t adapter_control; /* word 17 */
884 #define CFAUTOTERM 0x0001 /* Perform Auto termination */
885 #define CFSTERM 0x0002 /* SCSI low byte termination */
886 #define CFWSTERM 0x0004 /* SCSI high byte termination */
887 #define CFSEAUTOTERM 0x0008 /* Ultra2 Perform secondary Auto Term*/
888 #define CFSELOWTERM 0x0010 /* Ultra2 secondary low term */
889 #define CFSEHIGHTERM 0x0020 /* Ultra2 secondary high term */
890 #define CFSTPWLEVEL 0x0040 /* Termination level control */
891 #define CFBIOSAUTOTERM 0x0080 /* Perform Auto termination */
892 #define CFTERM_MENU 0x0100 /* BIOS displays termination menu */
893 #define CFCLUSTERENB 0x8000 /* Cluster Enable */
894
895 /*
896 * Bus Release Time, Host Adapter ID
897 */
898 uint16_t brtime_id; /* word 18 */
899 #define CFSCSIID 0x000f /* host adapter SCSI ID */
900 /* UNUSED 0x00f0 */
901 #define CFBRTIME 0xff00 /* bus release time/PCI Latency Time */
902
903 /*
904 * Maximum targets
905 */
906 uint16_t max_targets; /* word 19 */
907 #define CFMAXTARG 0x00ff /* maximum targets */
908 #define CFBOOTLUN 0x0f00 /* Lun to boot from */
909 #define CFBOOTID 0xf000 /* Target to boot from */
910 uint16_t res_1[10]; /* words 20-29 */
911 uint16_t signature; /* BIOS Signature */
912 #define CFSIGNATURE 0x400
913 uint16_t checksum; /* word 31 */
914 };
915
916 /*
917 * Vital Product Data used during POST and by the BIOS.
918 */
919 struct vpd_config {
920 uint8_t bios_flags;
921 #define VPDMASTERBIOS 0x0001
922 #define VPDBOOTHOST 0x0002
923 uint8_t reserved_1[21];
924 uint8_t resource_type;
925 uint8_t resource_len[2];
926 uint8_t resource_data[8];
927 uint8_t vpd_tag;
928 uint16_t vpd_len;
929 uint8_t vpd_keyword[2];
930 uint8_t length;
931 uint8_t revision;
932 uint8_t device_flags;
933 uint8_t termnation_menus[2];
934 uint8_t fifo_threshold;
935 uint8_t end_tag;
936 uint8_t vpd_checksum;
937 uint16_t default_target_flags;
938 uint16_t default_bios_flags;
939 uint16_t default_ctrl_flags;
940 uint8_t default_irq;
941 uint8_t pci_lattime;
942 uint8_t max_target;
943 uint8_t boot_lun;
944 uint16_t signature;
945 uint8_t reserved_2;
946 uint8_t checksum;
947 uint8_t reserved_3[4];
948 };
949
950 /****************************** Flexport Logic ********************************/
951 #define FLXADDR_TERMCTL 0x0
952 #define FLX_TERMCTL_ENSECHIGH 0x8
953 #define FLX_TERMCTL_ENSECLOW 0x4
954 #define FLX_TERMCTL_ENPRIHIGH 0x2
955 #define FLX_TERMCTL_ENPRILOW 0x1
956 #define FLXADDR_ROMSTAT_CURSENSECTL 0x1
957 #define FLX_ROMSTAT_SEECFG 0xF0
958 #define FLX_ROMSTAT_EECFG 0x0F
959 #define FLX_ROMSTAT_SEE_93C66 0x00
960 #define FLX_ROMSTAT_SEE_NONE 0xF0
961 #define FLX_ROMSTAT_EE_512x8 0x0
962 #define FLX_ROMSTAT_EE_1MBx8 0x1
963 #define FLX_ROMSTAT_EE_2MBx8 0x2
964 #define FLX_ROMSTAT_EE_4MBx8 0x3
965 #define FLX_ROMSTAT_EE_16MBx8 0x4
966 #define CURSENSE_ENB 0x1
967 #define FLXADDR_FLEXSTAT 0x2
968 #define FLX_FSTAT_BUSY 0x1
969 #define FLXADDR_CURRENT_STAT 0x4
970 #define FLX_CSTAT_SEC_HIGH 0xC0
971 #define FLX_CSTAT_SEC_LOW 0x30
972 #define FLX_CSTAT_PRI_HIGH 0x0C
973 #define FLX_CSTAT_PRI_LOW 0x03
974 #define FLX_CSTAT_MASK 0x03
975 #define FLX_CSTAT_SHIFT 2
976 #define FLX_CSTAT_OKAY 0x0
977 #define FLX_CSTAT_OVER 0x1
978 #define FLX_CSTAT_UNDER 0x2
979 #define FLX_CSTAT_INVALID 0x3
980
981 int ahd_read_seeprom(struct ahd_softc *, uint16_t *, u_int, u_int,
982 int);
983
984 int ahd_write_seeprom(struct ahd_softc *, uint16_t *, u_int, u_int);
985 int ahd_wait_seeprom(struct ahd_softc *);
986 int ahd_verify_vpd_cksum(struct vpd_config *);
987 int ahd_verify_cksum(struct seeprom_config *);
988 int ahd_acquire_seeprom(struct ahd_softc *);
989 void ahd_release_seeprom(struct ahd_softc *);
990
991 /**************************** Message Buffer *********************************/
992 typedef enum {
993 MSG_FLAG_NONE = 0x00,
994 MSG_FLAG_EXPECT_PPR_BUSFREE = 0x01,
995 MSG_FLAG_IU_REQ_CHANGED = 0x02,
996 MSG_FLAG_EXPECT_IDE_BUSFREE = 0x04,
997 MSG_FLAG_EXPECT_QASREJ_BUSFREE = 0x08,
998 MSG_FLAG_PACKETIZED = 0x10
999 } ahd_msg_flags;
1000
1001 typedef enum {
1002 MSG_TYPE_NONE = 0x00,
1003 MSG_TYPE_INITIATOR_MSGOUT = 0x01,
1004 MSG_TYPE_INITIATOR_MSGIN = 0x02,
1005 MSG_TYPE_TARGET_MSGOUT = 0x03,
1006 MSG_TYPE_TARGET_MSGIN = 0x04
1007 } ahd_msg_type;
1008
1009 typedef enum {
1010 MSGLOOP_IN_PROG,
1011 MSGLOOP_MSGCOMPLETE,
1012 MSGLOOP_TERMINATED
1013 } msg_loop_stat;
1014
1015 /*********************** Software Configuration Structure *********************/
1016 struct ahd_suspend_channel_state {
1017 uint8_t scsiseq;
1018 uint8_t sxfrctl0;
1019 uint8_t sxfrctl1;
1020 uint8_t simode0;
1021 uint8_t simode1;
1022 uint8_t seltimer;
1023 uint8_t seqctl;
1024 };
1025
1026 struct ahd_suspend_state {
1027 struct ahd_suspend_channel_state channel[2];
1028 uint8_t optionmode;
1029 uint8_t dscommand0;
1030 uint8_t dspcistatus;
1031 /* hsmailbox */
1032 uint8_t crccontrol1;
1033 uint8_t scbbaddr;
1034 /* Host and sequencer SCB counts */
1035 uint8_t dff_thrsh;
1036 uint8_t *scratch_ram;
1037 uint8_t *btt;
1038 };
1039
1040 typedef int (*ahd_bus_intr_t)(struct ahd_softc *);
1041
1042 typedef enum {
1043 AHD_MODE_DFF0,
1044 AHD_MODE_DFF1,
1045 AHD_MODE_CCHAN,
1046 AHD_MODE_SCSI,
1047 AHD_MODE_CFG,
1048 AHD_MODE_UNKNOWN
1049 } ahd_mode;
1050
1051 #define AHD_MK_MSK(x) (0x01 << (x))
1052 #define AHD_MODE_DFF0_MSK AHD_MK_MSK(AHD_MODE_DFF0)
1053 #define AHD_MODE_DFF1_MSK AHD_MK_MSK(AHD_MODE_DFF1)
1054 #define AHD_MODE_CCHAN_MSK AHD_MK_MSK(AHD_MODE_CCHAN)
1055 #define AHD_MODE_SCSI_MSK AHD_MK_MSK(AHD_MODE_SCSI)
1056 #define AHD_MODE_CFG_MSK AHD_MK_MSK(AHD_MODE_CFG)
1057 #define AHD_MODE_UNKNOWN_MSK AHD_MK_MSK(AHD_MODE_UNKNOWN)
1058 #define AHD_MODE_ANY_MSK (~0)
1059
1060 typedef uint8_t ahd_mode_state;
1061
1062 typedef void ahd_callback_t (void *);
1063
1064 struct ahd_softc {
1065 device_t sc_dev;
1066
1067 struct scsipi_channel sc_channel;
1068 device_t sc_child;
1069 struct scsipi_adapter sc_adapter;
1070
1071 bus_space_tag_t tags[2];
1072 bus_space_handle_t bshs[2];
1073
1074 struct scb_data scb_data;
1075
1076 struct hardware_scb *next_queued_hscb;
1077 struct map_node *next_queued_hscb_map;
1078
1079 /*
1080 * SCBs that have been sent to the controller
1081 */
1082 LIST_HEAD(, scb) pending_scbs;
1083
1084 /*
1085 * Current register window mode information.
1086 */
1087 ahd_mode dst_mode;
1088 ahd_mode src_mode;
1089
1090 /*
1091 * Saved register window mode information
1092 * used for restore on next unpause.
1093 */
1094 ahd_mode saved_dst_mode;
1095 ahd_mode saved_src_mode;
1096
1097 /*
1098 * Platform specific data.
1099 */
1100 struct ahd_platform_data *platform_data;
1101
1102 /*
1103 * Bus specific device information.
1104 */
1105 ahd_bus_intr_t bus_intr;
1106
1107 /*
1108 * Target mode related state kept on a per enabled lun basis.
1109 * Targets that are not enabled will have null entries.
1110 * As an initiator, we keep one target entry for our initiator
1111 * ID to store our sync/wide transfer settings.
1112 */
1113 struct ahd_tmode_tstate *enabled_targets[AHD_NUM_TARGETS];
1114
1115 char inited_target[AHD_NUM_TARGETS];
1116
1117 /*
1118 * The black hole device responsible for handling requests for
1119 * disabled luns on enabled targets.
1120 */
1121 struct ahd_tmode_lstate *black_hole;
1122
1123 /*
1124 * Device instance currently on the bus awaiting a continue TIO
1125 * for a command that was not given the disconnect priviledge.
1126 */
1127 struct ahd_tmode_lstate *pending_device;
1128
1129 /*
1130 * Timer handles for timer driven callbacks.
1131 */
1132 ahd_timer_t reset_timer;
1133 ahd_timer_t stat_timer;
1134
1135 /*
1136 * Statistics.
1137 */
1138 #define AHD_STAT_UPDATE_US 250000 /* 250ms */
1139 #define AHD_STAT_BUCKETS 4
1140 u_int cmdcmplt_bucket;
1141 uint32_t cmdcmplt_counts[AHD_STAT_BUCKETS];
1142 uint32_t cmdcmplt_total;
1143
1144 /*
1145 * Card characteristics
1146 */
1147 ahd_chip chip;
1148 ahd_feature features;
1149 ahd_bug bugs;
1150 ahd_flag flags;
1151 struct seeprom_config *seep_config;
1152
1153 /* Values to store in the SEQCTL register for pause and unpause */
1154 uint8_t unpause;
1155 uint8_t pause;
1156
1157 /* Command Queues */
1158 uint16_t qoutfifonext;
1159 uint16_t qoutfifonext_valid_tag;
1160 uint16_t qinfifonext;
1161 uint16_t qinfifo[AHD_SCB_MAX];
1162 uint16_t *qoutfifo;
1163
1164 /* Critical Section Data */
1165 struct cs *critical_sections;
1166 u_int num_critical_sections;
1167
1168 /* Buffer for handling packetized bitbucket. */
1169 uint8_t *overrun_buf;
1170
1171 /* Links for chaining softcs */
1172 TAILQ_ENTRY(ahd_softc) links;
1173
1174 /* Channel Names ('A', 'B', etc.) */
1175 char channel;
1176
1177 /* Initiator Bus ID */
1178 uint8_t our_id;
1179
1180 /*
1181 * Target incoming command FIFO.
1182 */
1183 struct target_cmd *targetcmds;
1184 uint8_t tqinfifonext;
1185
1186 /*
1187 * Cached verson of the hs_mailbox so we can avoid
1188 * pausing the sequencer during mailbox updates.
1189 */
1190 uint8_t hs_mailbox;
1191
1192 /*
1193 * Incoming and outgoing message handling.
1194 */
1195 uint8_t send_msg_perror;
1196 ahd_msg_flags msg_flags;
1197 ahd_msg_type msg_type;
1198 uint8_t msgout_buf[12];/* Message we are sending */
1199 uint8_t msgin_buf[12];/* Message we are receiving */
1200 u_int msgout_len; /* Length of message to send */
1201 u_int msgout_index; /* Current index in msgout */
1202 u_int msgin_index; /* Current index in msgin */
1203
1204 /*
1205 * Mapping information for data structures shared
1206 * between the sequencer and kernel.
1207 */
1208 bus_dma_tag_t parent_dmat;
1209 bus_dma_tag_t shared_data_dmat;
1210 struct map_node shared_data_map;
1211 int shared_data_size;
1212 int sc_dmaflags;
1213
1214 /* Information saved through suspend/resume cycles */
1215 struct ahd_suspend_state suspend_state;
1216
1217 /* Number of enabled target mode device on this card */
1218 u_int enabled_luns;
1219
1220 /* Initialization level of this data structure */
1221 u_int init_level;
1222
1223 /* PCI cacheline size. */
1224 u_int pci_cachesize;
1225
1226 /* IO Cell Parameters */
1227 uint8_t iocell_opts[AHD_NUM_PER_DEV_ANNEXCOLS];
1228
1229 u_int stack_size;
1230 uint16_t *saved_stack;
1231
1232 /* Per-Unit descriptive information */
1233 const char *description;
1234 const char *bus_description;
1235 const char *name;
1236 int unit;
1237
1238 /* Selection Timer settings */
1239 int seltime;
1240
1241 /*
1242 * Interrupt coalescing settings.
1243 */
1244 #define AHD_INT_COALESCING_TIMER_DEFAULT 250 /*us*/
1245 #define AHD_INT_COALESCING_MAXCMDS_DEFAULT 10
1246 #define AHD_INT_COALESCING_MAXCMDS_MAX 127
1247 #define AHD_INT_COALESCING_MINCMDS_DEFAULT 5
1248 #define AHD_INT_COALESCING_MINCMDS_MAX 127
1249 #define AHD_INT_COALESCING_THRESHOLD_DEFAULT 2000
1250 #define AHD_INT_COALESCING_STOP_THRESHOLD_DEFAULT 1000
1251 u_int int_coalescing_timer;
1252 u_int int_coalescing_maxcmds;
1253 u_int int_coalescing_mincmds;
1254 u_int int_coalescing_threshold;
1255 u_int int_coalescing_stop_threshold;
1256
1257 uint16_t user_discenable;/* Disconnection allowed */
1258 uint16_t user_tagenable;/* Tagged Queuing allowed */
1259
1260 /* Adapter interrupt routine */
1261 void* ih;
1262 struct ahd_pci_busdata *bus_data;
1263 };
1264
1265 TAILQ_HEAD(ahd_softc_tailq, ahd_softc);
1266 extern struct ahd_softc_tailq ahd_tailq;
1267
1268 /*************************** IO Cell Configuration ****************************/
1269 #define AHD_PRECOMP_SLEW_INDEX \
1270 (AHD_ANNEXCOL_PRECOMP_SLEW - AHD_ANNEXCOL_PER_DEV0)
1271
1272 #define AHD_AMPLITUDE_INDEX \
1273 (AHD_ANNEXCOL_AMPLITUDE - AHD_ANNEXCOL_PER_DEV0)
1274
1275 #define AHD_SET_SLEWRATE(ahd, new_slew) \
1276 do { \
1277 (ahd)->iocell_opts[AHD_PRECOMP_SLEW_INDEX] &= ~AHD_SLEWRATE_MASK; \
1278 (ahd)->iocell_opts[AHD_PRECOMP_SLEW_INDEX] |= \
1279 (((new_slew) << AHD_SLEWRATE_SHIFT) & AHD_SLEWRATE_MASK); \
1280 } while (0)
1281
1282 #define AHD_SET_PRECOMP(ahd, new_pcomp) \
1283 do { \
1284 (ahd)->iocell_opts[AHD_PRECOMP_SLEW_INDEX] &= ~AHD_PRECOMP_MASK; \
1285 (ahd)->iocell_opts[AHD_PRECOMP_SLEW_INDEX] |= \
1286 (((new_pcomp) << AHD_PRECOMP_SHIFT) & AHD_PRECOMP_MASK); \
1287 } while (0)
1288
1289 #define AHD_SET_AMPLITUDE(ahd, new_amp) \
1290 do { \
1291 (ahd)->iocell_opts[AHD_AMPLITUDE_INDEX] &= ~AHD_AMPLITUDE_MASK; \
1292 (ahd)->iocell_opts[AHD_AMPLITUDE_INDEX] |= \
1293 (((new_amp) << AHD_AMPLITUDE_SHIFT) & AHD_AMPLITUDE_MASK); \
1294 } while (0)
1295
1296 /************************ Active Device Information ***************************/
1297 typedef enum {
1298 ROLE_UNKNOWN,
1299 ROLE_INITIATOR,
1300 ROLE_TARGET
1301 } role_t;
1302
1303 struct ahd_devinfo {
1304 int our_scsiid;
1305 int target_offset;
1306 uint16_t target_mask;
1307 u_int target;
1308 u_int lun;
1309 char channel;
1310 role_t role; /*
1311 * Only guaranteed to be correct if not
1312 * in the busfree state.
1313 */
1314 };
1315
1316 /****************************** PCI Structures ********************************/
1317 #define AHD_PCI_IOADDR0 PCI_MAPREG_START /* I/O BAR*/
1318 #define AHD_PCI_MEMADDR (PCI_MAPREG_START + 4) /* Memory BAR */
1319 #define AHD_PCI_IOADDR1 (PCI_MAPREG_START + 12)/* Second I/O BAR */
1320
1321 typedef int (ahd_device_setup_t)(struct ahd_softc *, struct pci_attach_args *);
1322
1323 struct ahd_pci_identity {
1324 uint64_t full_id;
1325 uint64_t id_mask;
1326 const char *name;
1327 ahd_device_setup_t *setup;
1328 };
1329
1330 /***************************** VL/EISA Declarations ***************************/
1331 struct aic7770_identity {
1332 uint32_t full_id;
1333 uint32_t id_mask;
1334 const char *name;
1335 ahd_device_setup_t *setup;
1336 };
1337 extern struct aic7770_identity aic7770_ident_table [];
1338 extern const int ahd_num_aic7770_devs;
1339
1340 #define AHD_EISA_SLOT_OFFSET 0xc00
1341 #define AHD_EISA_IOSIZE 0x100
1342
1343 /*************************** Function Declarations ****************************/
1344 /******************************************************************************/
1345 void ahd_reset_cmds_pending(struct ahd_softc *);
1346 u_int ahd_find_busy_tcl(struct ahd_softc *, u_int);
1347 void ahd_busy_tcl(struct ahd_softc *, u_int, u_int);
1348 static __inline void ahd_unbusy_tcl(struct ahd_softc *, u_int);
1349 static __inline void
1350 ahd_unbusy_tcl(struct ahd_softc *ahd, u_int tcl)
1351 {
1352 ahd_busy_tcl(ahd, tcl, SCB_LIST_NULL);
1353 }
1354
1355 /************************** SCB and SCB queue management **********************/
1356 int ahd_probe_scbs(struct ahd_softc *);
1357 void ahd_qinfifo_requeue_tail(struct ahd_softc *,
1358 struct scb *);
1359 int ahd_match_scb(struct ahd_softc *, struct scb *,
1360 int, char, int, u_int, role_t);
1361
1362 /****************************** Initialization ********************************/
1363 /*struct ahd_softc *ahd_alloc(void *, char *);*/
1364 int ahd_softc_init(struct ahd_softc *);
1365 void ahd_controller_info(struct ahd_softc *, char *, size_t);
1366 int ahd_init(struct ahd_softc *);
1367 int ahd_default_config(struct ahd_softc *);
1368 int ahd_parse_vpddata(struct ahd_softc *,
1369 struct vpd_config *);
1370 int ahd_parse_cfgdata(struct ahd_softc *,
1371 struct seeprom_config *);
1372 void ahd_intr_enable(struct ahd_softc *, int);
1373 void ahd_update_coalescing_values(struct ahd_softc *,
1374 u_int, u_int, u_int);
1375 void ahd_enable_coalescing(struct ahd_softc *, int);
1376 void ahd_pause_and_flushwork(struct ahd_softc *);
1377 int ahd_suspend(struct ahd_softc *);
1378 int ahd_resume(struct ahd_softc *);
1379 void ahd_set_unit(struct ahd_softc *, int);
1380 void ahd_set_name(struct ahd_softc *, const char *);
1381 struct scb *ahd_get_scb(struct ahd_softc *, u_int);
1382 void ahd_free_scb(struct ahd_softc *, struct scb *);
1383 int ahd_alloc_scbs(struct ahd_softc *);
1384 void ahd_free(struct ahd_softc *);
1385 int ahd_reset(struct ahd_softc *, int);
1386 void ahd_shutdown(void *);
1387 int ahd_write_flexport(struct ahd_softc *,
1388 u_int, u_int);
1389 int ahd_read_flexport(struct ahd_softc *, u_int,
1390 uint8_t *);
1391 int ahd_wait_flexport(struct ahd_softc *);
1392
1393 /*************************** Interrupt Services *******************************/
1394 void ahd_clear_intstat(struct ahd_softc *);
1395 void ahd_flush_qoutfifo(struct ahd_softc *);
1396 void ahd_run_qoutfifo(struct ahd_softc *);
1397 void ahd_run_post_qoutfifo(struct ahd_softc *);
1398 #ifdef AHD_TARGET_MODE
1399 void ahd_run_tqinfifo(struct ahd_softc *, int);
1400 #endif
1401 void ahd_handle_hwerrint(struct ahd_softc *);
1402 void ahd_handle_seqint(struct ahd_softc *, u_int);
1403 void ahd_handle_scsiint(struct ahd_softc *, u_int);
1404 void ahd_clear_critical_section(struct ahd_softc *);
1405
1406 /***************************** Error Recovery *********************************/
1407 typedef enum {
1408 SEARCH_COMPLETE,
1409 SEARCH_COUNT,
1410 SEARCH_REMOVE,
1411 SEARCH_PRINT
1412 } ahd_search_action;
1413 int ahd_search_qinfifo(struct ahd_softc *, int, char, int,
1414 u_int, role_t, uint32_t, ahd_search_action);
1415 int ahd_search_disc_list(struct ahd_softc *, int, char,
1416 int, u_int, int, int, int);
1417 void ahd_freeze_devq(struct ahd_softc *, struct scb *);
1418 int ahd_reset_channel(struct ahd_softc *, char, int);
1419 int ahd_abort_scbs(struct ahd_softc *, int, char, int,
1420 u_int, role_t, uint32_t);
1421 void ahd_restart(struct ahd_softc *);
1422 void ahd_clear_fifo(struct ahd_softc *, u_int);
1423 void ahd_handle_scb_status(struct ahd_softc *, struct scb *);
1424 void ahd_handle_scsi_status(struct ahd_softc *,
1425 struct scb *);
1426 void ahd_calc_residual(struct ahd_softc *, struct scb *);
1427 /*************************** Utility Functions ********************************/
1428 struct ahd_phase_table_entry*
1429 ahd_lookup_phase_entry(int);
1430 void ahd_compile_devinfo(struct ahd_devinfo *, u_int, u_int,
1431 u_int, char, role_t);
1432 /************************** Transfer Negotiation ******************************/
1433 void ahd_find_syncrate(struct ahd_softc *, u_int *,
1434 u_int *, u_int);
1435 void ahd_validate_offset(struct ahd_softc *,
1436 struct ahd_initiator_tinfo *, u_int, u_int *,
1437 int, role_t);
1438 void ahd_validate_width(struct ahd_softc *,
1439 struct ahd_initiator_tinfo *, u_int *, role_t);
1440 /*
1441 * Negotiation types. These are used to qualify if we should renegotiate
1442 * even if our goal and current transport parameters are identical.
1443 */
1444 typedef enum {
1445 AHD_NEG_TO_GOAL, /* Renegotiate only if goal and curr differ. */
1446 AHD_NEG_IF_NON_ASYNC, /* Renegotiate so long as goal is non-async. */
1447 AHD_NEG_ALWAYS /* Renegotiat even if goal is async. */
1448 } ahd_neg_type;
1449 int ahd_update_neg_request(struct ahd_softc *,
1450 struct ahd_devinfo *, struct ahd_tmode_tstate *,
1451 struct ahd_initiator_tinfo *, ahd_neg_type);
1452 void ahd_set_width(struct ahd_softc *,
1453 struct ahd_devinfo *, u_int, u_int, int);
1454 void ahd_set_syncrate(struct ahd_softc *,
1455 struct ahd_devinfo *, u_int, u_int, u_int,
1456 u_int, int);
1457 typedef enum {
1458 AHD_QUEUE_NONE,
1459 AHD_QUEUE_BASIC,
1460 AHD_QUEUE_TAGGED
1461 } ahd_queue_alg;
1462
1463 void ahd_set_tags(struct ahd_softc *, struct ahd_devinfo *,
1464 ahd_queue_alg);
1465
1466 /**************************** Target Mode *************************************/
1467 #ifdef AHD_TARGET_MODE
1468 void ahd_send_lstate_events(struct ahd_softc *,
1469 struct ahd_tmode_lstate *);
1470 void ahd_handle_en_lun(struct ahd_softc *,
1471 struct cam_sim *, union ccb *);
1472 cam_status ahd_find_tmode_devs(struct ahd_softc *, struct cam_sim *,
1473 union ccb *, struct ahd_tmode_tstate **,
1474 struct ahd_tmode_lstate **, int);
1475 #ifndef AHD_TMODE_ENABLE
1476 #define AHD_TMODE_ENABLE 0
1477 #endif
1478 #endif
1479 /******************************* Debug ***************************************/
1480 #ifdef AHD_DEBUG
1481 extern uint32_t ahd_debug;
1482 #define AHD_SHOW_MISC 0x00001
1483 #define AHD_SHOW_SENSE 0x00002
1484 #define AHD_SHOW_RECOVERY 0x00004
1485 #define AHD_DUMP_SEEPROM 0x00008
1486 #define AHD_SHOW_TERMCTL 0x00010
1487 #define AHD_SHOW_MEMORY 0x00020
1488 #define AHD_SHOW_MESSAGES 0x00040
1489 #define AHD_SHOW_MODEPTR 0x00080
1490 #define AHD_SHOW_SELTO 0x00100
1491 #define AHD_SHOW_FIFOS 0x00200
1492 #define AHD_SHOW_QFULL 0x00400
1493 #define AHD_SHOW_DV 0x00800
1494 #define AHD_SHOW_MASKED_ERRORS 0x01000
1495 #define AHD_SHOW_QUEUE 0x02000
1496 #define AHD_SHOW_TQIN 0x04000
1497 #define AHD_SHOW_SG 0x08000
1498 #define AHD_SHOW_INT_COALESCING 0x10000
1499 #define AHD_DEBUG_SEQUENCER 0x20000
1500 #endif
1501 void ahd_print_scb(struct scb *);
1502 void ahd_print_devinfo(struct ahd_softc *,
1503 struct ahd_devinfo *);
1504 void ahd_dump_sglist(struct scb *);
1505 void ahd_dump_all_cards_state(void);
1506 void ahd_dump_card_state(struct ahd_softc *);
1507 int ahd_print_register(ahd_reg_parse_entry_t *, u_int,
1508 const char *, u_int, u_int, u_int *, u_int);
1509 void ahd_dump_scbs(struct ahd_softc *);
1510 #endif /* _AIC79XXVAR_H_ */
NetBSD on the FriendlyARM MINI2440