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[netbsd-mini2440.git] / sys / dev / ic / aic7xxxvar.h
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1 /*
2 * Core definitions and data structures sharable across OS platforms.
3 *
4 * Copyright (c) 1994-2001 Justin T. Gibbs.
5 * Copyright (c) 2000-2001 Adaptec Inc.
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions, and the following disclaimer,
13 * without modification.
14 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
15 * substantially similar to the "NO WARRANTY" disclaimer below
16 * ("Disclaimer") and any redistribution must be conditioned upon
17 * including a substantially similar Disclaimer requirement for further
18 * binary redistribution.
19 * 3. Neither the names of the above-listed copyright holders nor the names
20 * of any contributors may be used to endorse or promote products derived
21 * from this software without specific prior written permission.
22 *
23 * Alternatively, this software may be distributed under the terms of the
24 * GNU General Public License ("GPL") version 2 as published by the Free
25 * Software Foundation.
26 *
27 * NO WARRANTY
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
37 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
38 * POSSIBILITY OF SUCH DAMAGES.
39 *
40 * $Id: aic7xxxvar.h,v 1.57 2009/05/12 14:25:17 cegger Exp $
41 *
42 * $FreeBSD: /repoman/r/ncvs/src/sys/dev/aic7xxx/aic7xxx.h,v 1.44 2003/01/20 20:44:55 gibbs Exp $
43 */
44 /*
45 * Ported from FreeBSD by Pascal Renauld, Network Storage Solutions, Inc. - April 2003
46 */
47
48 #ifndef _AIC7XXXVAR_H_
49 #define _AIC7XXXVAR_H_
50
51 #undef AHC_DEBUG
52
53 /* Register Definitions */
54 #include <dev/microcode/aic7xxx/aic7xxx_reg.h>
55
56 #include <dev/ic/aic7xxx_cam.h>
57
58 #define AIC_OP_OR 0x0
59 #define AIC_OP_AND 0x1
60 #define AIC_OP_XOR 0x2
61 #define AIC_OP_ADD 0x3
62 #define AIC_OP_ADC 0x4
63 #define AIC_OP_ROL 0x5
64 #define AIC_OP_BMOV 0x6
65
66 #define AIC_OP_JMP 0x8
67 #define AIC_OP_JC 0x9
68 #define AIC_OP_JNC 0xa
69 #define AIC_OP_CALL 0xb
70 #define AIC_OP_JNE 0xc
71 #define AIC_OP_JNZ 0xd
72 #define AIC_OP_JE 0xe
73 #define AIC_OP_JZ 0xf
74
75 /* Pseudo Ops */
76 #define AIC_OP_SHL 0x10
77 #define AIC_OP_SHR 0x20
78 #define AIC_OP_ROR 0x30
79
80 struct ins_format1 {
81 #if BYTE_ORDER == LITTLE_ENDIAN
82 uint32_t immediate : 8,
83 source : 9,
84 destination : 9,
85 ret : 1,
86 opcode : 4,
87 parity : 1;
88 #else
89 uint32_t parity : 1,
90 opcode : 4,
91 ret : 1,
92 destination : 9,
93 source : 9,
94 immediate : 8;
95 #endif
96 };
97
98 struct ins_format2 {
99 #if BYTE_ORDER == LITTLE_ENDIAN
100 uint32_t shift_control : 8,
101 source : 9,
102 destination : 9,
103 ret : 1,
104 opcode : 4,
105 parity : 1;
106 #else
107 uint32_t parity : 1,
108 opcode : 4,
109 ret : 1,
110 destination : 9,
111 source : 9,
112 shift_control : 8;
113 #endif
114 };
115
116 struct ins_format3 {
117 #if BYTE_ORDER == LITTLE_ENDIAN
118 uint32_t immediate : 8,
119 source : 9,
120 address : 10,
121 opcode : 4,
122 parity : 1;
123 #else
124 uint32_t parity : 1,
125 opcode : 4,
126 address : 10,
127 source : 9,
128 immediate : 8;
129 #endif
130 };
131
132 union ins_formats {
133 struct ins_format1 format1;
134 struct ins_format2 format2;
135 struct ins_format3 format3;
136 uint8_t bytes[4];
137 uint32_t integer;
138 };
139
140 /************************* Forward Declarations *******************************/
141 struct ahc_platform_data;
142 struct scb_platform_data;
143 struct seeprom_descriptor;
144
145 /****************************** Useful Macros *********************************/
146 #ifndef MAX
147 #define MAX(a,b) (((a) > (b)) ? (a) : (b))
148 #endif
149
150 #ifndef MIN
151 #define MIN(a,b) (((a) < (b)) ? (a) : (b))
152 #endif
153
154 #ifndef TRUE
155 #define TRUE 1
156 #endif
157 #ifndef FALSE
158 #define FALSE 0
159 #endif
160
161 #define NUM_ELEMENTS(array) (sizeof(array) / sizeof(*array))
162
163 #define ALL_CHANNELS '\0'
164 #define ALL_TARGETS_MASK 0xFFFF
165 #define INITIATOR_WILDCARD (~0)
166
167 #define SCSIID_TARGET(ahc, scsiid) \
168 (((scsiid) & ((((ahc)->features & AHC_TWIN) != 0) ? TWIN_TID : TID)) \
169 >> TID_SHIFT)
170 #define SCSIID_OUR_ID(scsiid) \
171 ((scsiid) & OID)
172 #define SCSIID_CHANNEL(ahc, scsiid) \
173 ((((ahc)->features & AHC_TWIN) != 0) \
174 ? ((((scsiid) & TWIN_CHNLB) != 0) ? 'B' : 'A') \
175 : 'A')
176 #define SCB_IS_SCSIBUS_B(ahc, scb) \
177 (SCSIID_CHANNEL(ahc, (scb)->hscb->scsiid) == 'B')
178 #define SCB_GET_OUR_ID(scb) \
179 SCSIID_OUR_ID((scb)->hscb->scsiid)
180 #define SCB_GET_TARGET(ahc, scb) \
181 SCSIID_TARGET((ahc), (scb)->hscb->scsiid)
182 #define SCB_GET_CHANNEL(ahc, scb) \
183 SCSIID_CHANNEL(ahc, (scb)->hscb->scsiid)
184 #define SCB_GET_LUN(scb) \
185 ((scb)->hscb->lun)
186 #define SCB_GET_TARGET_OFFSET(ahc, scb) \
187 (SCB_GET_TARGET(ahc, scb))
188 #define SCB_GET_TARGET_MASK(ahc, scb) \
189 (0x01 << (SCB_GET_TARGET_OFFSET(ahc, scb)))
190 #ifdef AHC_DEBUG
191 #define SCB_IS_SILENT(scb) \
192 ((ahc_debug & AHC_SHOW_MASKED_ERRORS) == 0 \
193 && (((scb)->flags & SCB_SILENT) != 0))
194 #else
195 #define SCB_IS_SILENT(scb) \
196 (((scb)->flags & SCB_SILENT) != 0)
197 #endif
198 #define TCL_TARGET_OFFSET(tcl) \
199 ((((tcl) >> 4) & TID) >> 4)
200 #define TCL_LUN(tcl) \
201 (tcl & (AHC_NUM_LUNS - 1))
202 #define BUILD_TCL(scsiid, lun) \
203 ((lun) | (((scsiid) & TID) << 4))
204
205 #ifndef AHC_TARGET_MODE
206 #undef AHC_TMODE_ENABLE
207 #define AHC_TMODE_ENABLE 0
208 #endif
209
210 /**************************** Driver Constants ********************************/
211 /*
212 * The maximum number of supported targets.
213 */
214 #define AHC_NUM_TARGETS 16
215
216 /*
217 * The maximum number of supported luns.
218 * The identify message only supports 64 luns in SPI3.
219 * You can have 2^64 luns when information unit transfers are enabled,
220 * but it is doubtful this driver will ever support IUTs.
221 */
222 #define AHC_NUM_LUNS 64
223
224 /*
225 * The maximum transfer per S/G segment.
226 * Limited by MAXPHYS or a 24-bit counter.
227 */
228 #define AHC_MAXTRANSFER_SIZE MIN(MAXPHYS,0x00ffffff)
229
230 /*
231 * The maximum amount of SCB storage in hardware on a controller.
232 * This value represents an upper bound. Controllers vary in the number
233 * they actually support.
234 */
235 #define AHC_SCB_MAX 255
236
237 /*
238 * The maximum number of concurrent transactions supported per driver instance.
239 * Sequencer Control Blocks (SCBs) store per-transaction information. Although
240 * the space for SCBs on the host adapter varies by model, the driver will
241 * page the SCBs between host and controller memory as needed. We are limited
242 * to 253 because:
243 * 1) The 8bit nature of the RISC engine holds us to an 8bit value.
244 * 2) We reserve one value, 255, to represent the invalid element.
245 * 3) Our input queue scheme requires one SCB to always be reserved
246 * in advance of queuing any SCBs. This takes us down to 254.
247 * 4) To handle our output queue correctly on machines that only
248 * support 32bit stores, we must clear the array 4 bytes at a
249 * time. To avoid colliding with a DMA write from the sequencer,
250 * we must be sure that 4 slots are empty when we write to clear
251 * the queue. This reduces us to 253 SCBs: 1 that just completed
252 * and the known three additional empty slots in the queue that
253 * precede it.
254 */
255 #define AHC_MAX_QUEUE 253
256
257 /*
258 * The maximum amount of SCB storage we allocate in host memory. This
259 * number should reflect the 1 additional SCB we require to handle our
260 * qinfifo mechanism.
261 */
262 #define AHC_SCB_MAX_ALLOC (AHC_MAX_QUEUE+1)
263
264 /*
265 * Ring Buffer of incoming target commands.
266 * We allocate 256 to simplify the logic in the sequencer
267 * by using the natural wrap point of an 8bit counter.
268 */
269 #define AHC_TMODE_CMDS 256
270
271 /* Reset line assertion time in us */
272 #define AHC_BUSRESET_DELAY 25
273
274 /******************* Chip Characteristics/Operating Settings *****************/
275 /*
276 * Chip Type
277 * The chip order is from least sophisticated to most sophisticated.
278 */
279 typedef enum {
280 AHC_NONE = 0x0000,
281 AHC_CHIPID_MASK = 0x00FF,
282 AHC_AIC7770 = 0x0001,
283 AHC_AIC7850 = 0x0002,
284 AHC_AIC7855 = 0x0003,
285 AHC_AIC7859 = 0x0004,
286 AHC_AIC7860 = 0x0005,
287 AHC_AIC7870 = 0x0006,
288 AHC_AIC7880 = 0x0007,
289 AHC_AIC7895 = 0x0008,
290 AHC_AIC7895C = 0x0009,
291 AHC_AIC7890 = 0x000a,
292 AHC_AIC7896 = 0x000b,
293 AHC_AIC7892 = 0x000c,
294 AHC_AIC7899 = 0x000d,
295 AHC_VL = 0x0100, /* Bus type VL */
296 AHC_EISA = 0x0200, /* Bus type EISA */
297 AHC_PCI = 0x0400, /* Bus type PCI */
298 AHC_BUS_MASK = 0x0F00
299 } ahc_chip;
300
301 /*
302 * Features available in each chip type.
303 */
304 typedef enum {
305 AHC_FENONE = 0x00000,
306 AHC_ULTRA = 0x00001, /* Supports 20MHz Transfers */
307 AHC_ULTRA2 = 0x00002, /* Supports 40MHz Transfers */
308 AHC_WIDE = 0x00004, /* Wide Channel */
309 AHC_TWIN = 0x00008, /* Twin Channel */
310 AHC_MORE_SRAM = 0x00010, /* 80 bytes instead of 64 */
311 AHC_CMD_CHAN = 0x00020, /* Has a Command DMA Channel */
312 AHC_QUEUE_REGS = 0x00040, /* Has Queue management registers */
313 AHC_SG_PRELOAD = 0x00080, /* Can perform auto-SG preload */
314 AHC_SPIOCAP = 0x00100, /* Has a Serial Port I/O Cap Register */
315 AHC_MULTI_TID = 0x00200, /* Has bitmask of TIDs for select-in */
316 AHC_HS_MAILBOX = 0x00400, /* Has HS_MAILBOX register */
317 AHC_DT = 0x00800, /* Double Transition transfers */
318 AHC_NEW_TERMCTL = 0x01000, /* Newer termination scheme */
319 AHC_MULTI_FUNC = 0x02000, /* Multi-Function Twin Channel Device */
320 AHC_LARGE_SCBS = 0x04000, /* 64byte SCBs */
321 AHC_AUTORATE = 0x08000, /* Automatic update of SCSIRATE/OFFSET*/
322 AHC_AUTOPAUSE = 0x10000, /* Automatic pause on register access */
323 AHC_TARGETMODE = 0x20000, /* Has tested target mode support */
324 AHC_MULTIROLE = 0x40000, /* Space for two roles at a time */
325 AHC_REMOVABLE = 0x80000, /* Hot-Swap supported */
326 AHC_AIC7770_FE = AHC_FENONE,
327 /*
328 * The real 7850 does not support Ultra modes, but there are
329 * several cards that use the generic 7850 PCI ID even though
330 * they are using an Ultra capable chip (7859/7860). We start
331 * out with the AHC_ULTRA feature set and then check the DEVSTATUS
332 * register to determine if the capability is really present.
333 */
334 AHC_AIC7850_FE = AHC_SPIOCAP|AHC_AUTOPAUSE|AHC_TARGETMODE|AHC_ULTRA,
335 AHC_AIC7860_FE = AHC_AIC7850_FE,
336 AHC_AIC7870_FE = AHC_TARGETMODE,
337 AHC_AIC7880_FE = AHC_AIC7870_FE|AHC_ULTRA,
338 /*
339 * Although we have space for both the initiator and
340 * target roles on ULTRA2 chips, we currently disable
341 * the initiator role to allow multi-scsi-id target mode
342 * configurations. We can only respond on the same SCSI
343 * ID as our initiator role if we allow initiator operation.
344 * At some point, we should add a configuration knob to
345 * allow both roles to be loaded.
346 */
347 AHC_AIC7890_FE = AHC_MORE_SRAM|AHC_CMD_CHAN|AHC_ULTRA2
348 |AHC_QUEUE_REGS|AHC_SG_PRELOAD|AHC_MULTI_TID
349 |AHC_HS_MAILBOX|AHC_NEW_TERMCTL|AHC_LARGE_SCBS
350 |AHC_TARGETMODE,
351 AHC_AIC7892_FE = AHC_AIC7890_FE|AHC_DT|AHC_AUTORATE|AHC_AUTOPAUSE,
352 AHC_AIC7895_FE = AHC_AIC7880_FE|AHC_MORE_SRAM|AHC_AUTOPAUSE
353 |AHC_CMD_CHAN|AHC_MULTI_FUNC|AHC_LARGE_SCBS,
354 AHC_AIC7895C_FE = AHC_AIC7895_FE|AHC_MULTI_TID,
355 AHC_AIC7896_FE = AHC_AIC7890_FE|AHC_MULTI_FUNC,
356 AHC_AIC7899_FE = AHC_AIC7892_FE|AHC_MULTI_FUNC
357 } ahc_feature;
358
359 /*
360 * Bugs in the silicon that we work around in software.
361 */
362 typedef enum {
363 AHC_BUGNONE = 0x00,
364 /*
365 * On all chips prior to the U2 product line,
366 * the WIDEODD S/G segment feature does not
367 * work during scsi->HostBus transfers.
368 */
369 AHC_TMODE_WIDEODD_BUG = 0x01,
370 /*
371 * On the aic7890/91 Rev 0 chips, the autoflush
372 * feature does not work. A manual flush of
373 * the DMA FIFO is required.
374 */
375 AHC_AUTOFLUSH_BUG = 0x02,
376 /*
377 * On many chips, cacheline streaming does not work.
378 */
379 AHC_CACHETHEN_BUG = 0x04,
380 /*
381 * On the aic7896/97 chips, cacheline
382 * streaming must be enabled.
383 */
384 AHC_CACHETHEN_DIS_BUG = 0x08,
385 /*
386 * PCI 2.1 Retry failure on non-empty data fifo.
387 */
388 AHC_PCI_2_1_RETRY_BUG = 0x10,
389 /*
390 * Controller does not handle cacheline residuals
391 * properly on S/G segments if PCI MWI instructions
392 * are allowed.
393 */
394 AHC_PCI_MWI_BUG = 0x20,
395 /*
396 * An SCB upload using the SCB channel's
397 * auto array entry copy feature may
398 * corrupt data. This appears to only
399 * occur on 66MHz systems.
400 */
401 AHC_SCBCHAN_UPLOAD_BUG = 0x40
402 } ahc_bug;
403
404 /*
405 * Configuration specific settings.
406 * The driver determines these settings by probing the
407 * chip/controller's configuration.
408 */
409 typedef enum {
410 AHC_FNONE = 0x000,
411 AHC_PRIMARY_CHANNEL = 0x003, /*
412 * The channel that should
413 * be probed first.
414 */
415 AHC_USEDEFAULTS = 0x004, /*
416 * For cards without an seeprom
417 * or a BIOS to initialize the chip's
418 * SRAM, we use the default settings.
419 */
420 AHC_SEQUENCER_DEBUG = 0x008,
421 AHC_SHARED_SRAM = 0x010,
422 AHC_LARGE_SEEPROM = 0x020, /* Uses C56_66 not C46 */
423 AHC_RESET_BUS_A = 0x040,
424 AHC_RESET_BUS_B = 0x080,
425 AHC_EXTENDED_TRANS_A = 0x100,
426 AHC_EXTENDED_TRANS_B = 0x200,
427 AHC_TERM_ENB_A = 0x400,
428 AHC_TERM_ENB_B = 0x800,
429 AHC_INITIATORROLE = 0x1000, /*
430 * Allow initiator operations on
431 * this controller.
432 */
433 AHC_TARGETROLE = 0x2000, /*
434 * Allow target operations on this
435 * controller.
436 */
437 AHC_NEWEEPROM_FMT = 0x4000,
438 AHC_RESOURCE_SHORTAGE = 0x8000,
439 AHC_TQINFIFO_BLOCKED = 0x10000, /* Blocked waiting for ATIOs */
440 AHC_INT50_SPEEDFLEX = 0x20000, /*
441 * Internal 50pin connector
442 * sits behind an aic3860
443 */
444 AHC_SCB_BTT = 0x40000, /*
445 * The busy targets table is
446 * stored in SCB space rather
447 * than SRAM.
448 */
449 AHC_BIOS_ENABLED = 0x80000,
450 AHC_ALL_INTERRUPTS = 0x100000,
451 AHC_PAGESCBS = 0x400000, /* Enable SCB paging */
452 AHC_EDGE_INTERRUPT = 0x800000, /* Device uses edge triggered ints */
453 AHC_39BIT_ADDRESSING = 0x1000000, /* Use 39 bit addressing scheme. */
454 AHC_LSCBS_ENABLED = 0x2000000, /* 64Byte SCBs enabled */
455 AHC_SCB_CONFIG_USED = 0x4000000, /* No SEEPROM but SCB2 had info. */
456 AHC_NO_BIOS_INIT = 0x8000000, /* No BIOS left over settings. */
457 AHC_DISABLE_PCI_PERR = 0x10000000,
458 AHC_USETARGETDEFAULTS = 0x20000000 /*
459 * For cards without an seeprom but
460 * with BIOS which initializes chip's
461 * SRAM with some conservative target
462 * settings, we use the default
463 * SCSI target settings.
464 */
465 } ahc_flag;
466
467 /************************* Hardware SCB Definition ***************************/
468
469 /*
470 * The driver keeps up to MAX_SCB scb structures per card in memory. The SCB
471 * consists of a "hardware SCB" mirroring the fields available on the card
472 * and additional information the kernel stores for each transaction.
473 *
474 * To minimize space utilization, a portion of the hardware scb stores
475 * different data during different portions of a SCSI transaction.
476 * As initialized by the host driver for the initiator role, this area
477 * contains the SCSI cdb (or a pointer to the cdb) to be executed. After
478 * the cdb has been presented to the target, this area serves to store
479 * residual transfer information and the SCSI status byte.
480 * For the target role, the contents of this area do not change, but
481 * still serve a different purpose than for the initiator role. See
482 * struct target_data for details.
483 */
484
485 /*
486 * Status information embedded in the shared portion of
487 * an SCB after passing the cdb to the target. The kernel
488 * driver will only read this data for transactions that
489 * complete abnormally (non-zero status byte).
490 */
491 struct status_pkt {
492 uint32_t residual_datacnt; /* Residual in the current S/G seg */
493 uint32_t residual_sg_ptr; /* The next S/G for this transfer */
494 uint8_t scsi_status; /* Standard SCSI status byte */
495 };
496
497 /*
498 * Target mode version of the shared data SCB segment.
499 */
500 struct target_data {
501 uint32_t residual_datacnt; /* Residual in the current S/G seg */
502 uint32_t residual_sg_ptr; /* The next S/G for this transfer */
503 uint8_t scsi_status; /* SCSI status to give to initiator */
504 uint8_t target_phases; /* Bitmap of phases to execute */
505 uint8_t data_phase; /* Data-In or Data-Out */
506 uint8_t initiator_tag; /* Initiator's transaction tag */
507 };
508
509 struct hardware_scb {
510 /*0*/ union {
511 /*
512 * If the cdb is 12 bytes or less, we embed it directly
513 * in the SCB. For longer cdbs, we embed the address
514 * of the cdb payload as seen by the chip and a DMA
515 * is used to pull it in.
516 */
517 uint8_t cdb[12];
518 uint32_t cdb_ptr;
519 struct status_pkt status;
520 struct target_data tdata;
521 } shared_data;
522 /*
523 * A word about residuals.
524 * The scb is presented to the sequencer with the dataptr and datacnt
525 * fields initialized to the contents of the first S/G element to
526 * transfer. The sgptr field is initialized to the bus address for
527 * the S/G element that follows the first in the in core S/G array
528 * or'ed with the SG_FULL_RESID flag. Sgptr may point to an invalid
529 * S/G entry for this transfer (single S/G element transfer with the
530 * first elements address and length preloaded in the dataptr/datacnt
531 * fields). If no transfer is to occur, sgptr is set to SG_LIST_NULL.
532 * The SG_FULL_RESID flag ensures that the residual will be correctly
533 * noted even if no data transfers occur. Once the data phase is entered,
534 * the residual sgptr and datacnt are loaded from the sgptr and the
535 * datacnt fields. After each S/G element's dataptr and length are
536 * loaded into the hardware, the residual sgptr is advanced. After
537 * each S/G element is expired, its datacnt field is checked to see
538 * if the LAST_SEG flag is set. If so, SG_LIST_NULL is set in the
539 * residual sg ptr and the transfer is considered complete. If the
540 * sequencer determines that there is a residual in the transfer, it
541 * will set the SG_RESID_VALID flag in sgptr and DMA the scb back into
542 * host memory. To summarize:
543 *
544 * Sequencer:
545 * o A residual has occurred if SG_FULL_RESID is set in sgptr,
546 * or residual_sgptr does not have SG_LIST_NULL set.
547 *
548 * o We are transfering the last segment if residual_datacnt has
549 * the SG_LAST_SEG flag set.
550 *
551 * Host:
552 * o A residual has occurred if a completed scb has the
553 * SG_RESID_VALID flag set.
554 *
555 * o residual_sgptr and sgptr refer to the "next" sg entry
556 * and so may point beyond the last valid sg entry for the
557 * transfer.
558 */
559 /*12*/ uint32_t dataptr;
560 /*16*/ uint32_t datacnt; /*
561 * Byte 3 (numbered from 0) of
562 * the datacnt is really the
563 * 4th byte in that data address.
564 */
565 /*20*/ uint32_t sgptr;
566 #define SG_PTR_MASK 0xFFFFFFF8
567 /*24*/ uint8_t control; /* See SCB_CONTROL in aic7xxx.reg for details */
568 /*25*/ uint8_t scsiid; /* what to load in the SCSIID register */
569 /*26*/ uint8_t lun;
570 /*27*/ uint8_t tag; /*
571 * Index into our kernel SCB array.
572 * Also used as the tag for tagged I/O
573 */
574 /*28*/ uint8_t cdb_len;
575 /*29*/ uint8_t scsirate; /* Value for SCSIRATE register */
576 /*30*/ uint8_t scsioffset; /* Value for SCSIOFFSET register */
577 /*31*/ uint8_t next; /*
578 * Used for threading SCBs in the
579 * "Waiting for Selection" and
580 * "Disconnected SCB" lists down
581 * in the sequencer.
582 */
583 /*32*/ uint8_t cdb32[32]; /*
584 * CDB storage for cdbs of size
585 * 13->32. We store them here
586 * because hardware scbs are
587 * allocated from DMA safe
588 * memory so we are guaranteed
589 * the controller can access
590 * this data.
591 */
592 };
593
594 /************************ Kernel SCB Definitions ******************************/
595 /*
596 * Some fields of the SCB are OS dependent. Here we collect the
597 * definitions for elements that all OS platforms need to include
598 * in there SCB definition.
599 */
600
601 /*
602 * Definition of a scatter/gather element as transferred to the controller.
603 * The aic7xxx chips only support a 24bit length. We use the top byte of
604 * the length to store additional address bits and a flag to indicate
605 * that a given segment terminates the transfer. This gives us an
606 * addressable range of 512GB on machines with 64bit PCI or with chips
607 * that can support dual address cycles on 32bit PCI busses.
608 */
609 struct ahc_dma_seg {
610 uint32_t addr;
611 uint32_t len;
612 #define AHC_DMA_LAST_SEG 0x80000000
613 #define AHC_SG_HIGH_ADDR_MASK 0x7F000000
614 #define AHC_SG_LEN_MASK 0x00FFFFFF
615 };
616
617 struct sg_map_node {
618 bus_dmamap_t sg_dmamap;
619 bus_addr_t sg_physaddr;
620 bus_dma_segment_t sg_dmasegs;
621 int sg_nseg;
622 struct ahc_dma_seg* sg_vaddr;
623 SLIST_ENTRY(sg_map_node) links;
624 };
625
626 struct ahc_pci_busdata {
627 pci_chipset_tag_t pc;
628 pcitag_t tag;
629 u_int dev;
630 u_int func;
631 pcireg_t class;
632 };
633
634 /*
635 * The current state of this SCB.
636 */
637 typedef enum {
638 SCB_FREE = 0x0000,
639 SCB_OTHERTCL_TIMEOUT = 0x0002,/*
640 * Another device was active
641 * during the first timeout for
642 * this SCB so we gave ourselves
643 * an additional timeout period
644 * in case it was hogging the
645 * bus.
646 */
647 SCB_DEVICE_RESET = 0x0004,
648 SCB_SENSE = 0x0008,
649 SCB_CDB32_PTR = 0x0010,
650 SCB_RECOVERY_SCB = 0x0020,
651 SCB_AUTO_NEGOTIATE = 0x0040,/* Negotiate to achieve goal. */
652 SCB_NEGOTIATE = 0x0080,/* Negotiation forced for command. */
653 SCB_ABORT = 0x0100,
654 SCB_UNTAGGEDQ = 0x0200,
655 SCB_ACTIVE = 0x0400,
656 SCB_TARGET_IMMEDIATE = 0x0800,
657 SCB_TRANSMISSION_ERROR = 0x1000,/*
658 * We detected a parity or CRC
659 * error that has effected the
660 * payload of the command. This
661 * flag is checked when normal
662 * status is returned to catch
663 * the case of a target not
664 * responding to our attempt
665 * to report the error.
666 */
667 SCB_TARGET_SCB = 0x2000,
668 SCB_SILENT = 0x4000,/*
669 * Be quiet about transmission type
670 * errors. They are expected and we
671 * don't want to upset the user. This
672 * flag is typically used during DV.
673 */
674 SCB_FREEZE_QUEUE = 0x8000
675 } scb_flag;
676
677 struct scb {
678 struct hardware_scb *hscb;
679 union {
680 SLIST_ENTRY(scb) sle;
681 TAILQ_ENTRY(scb) tqe;
682 } links;
683 LIST_ENTRY(scb) pending_links;
684
685 struct scsipi_xfer *xs;
686 struct ahc_softc *ahc_softc;
687 scb_flag flags;
688 #ifndef __linux__
689 bus_dmamap_t dmamap;
690 #endif
691 struct scb_platform_data *platform_data;
692 struct sg_map_node *sg_map;
693 struct ahc_dma_seg *sg_list;
694 bus_addr_t sg_list_phys;
695 u_int sg_count;/* How full ahc_dma_seg is */
696 };
697
698 struct scb_data {
699 SLIST_HEAD(, scb) free_scbs; /*
700 * Pool of SCBs ready to be assigned
701 * commands to execute.
702 */
703 struct scb *scbindex[256]; /*
704 * Mapping from tag to SCB.
705 * As tag identifiers are an
706 * 8bit value, we provide space
707 * for all possible tag values.
708 * Any lookups to entries at or
709 * above AHC_SCB_MAX_ALLOC will
710 * always fail.
711 */
712 struct hardware_scb *hscbs; /* Array of hardware SCBs */
713 struct scb *scbarray; /* Array of kernel SCBs */
714 struct scsi_sense_data *sense; /* Per SCB sense data */
715
716 /*
717 * "Bus" addresses of our data structures.
718 */
719 bus_dmamap_t hscb_dmamap;
720 bus_addr_t hscb_busaddr;
721 bus_dma_segment_t hscb_seg;
722 int hscb_nseg;
723 int hscb_size;
724
725 bus_dmamap_t sense_dmamap;
726 bus_addr_t sense_busaddr;
727 bus_dma_segment_t sense_seg;
728 int sense_nseg;
729 int sense_size;
730
731 SLIST_HEAD(, sg_map_node) sg_maps;
732 uint8_t numscbs;
733 uint8_t maxhscbs; /* Number of SCBs on the card */
734 uint8_t init_level; /*
735 * How far we've initialized
736 * this structure.
737 */
738 };
739
740 /************************ Target Mode Definitions *****************************/
741
742 /*
743 * Connection desciptor for select-in requests in target mode.
744 */
745 struct target_cmd {
746 uint8_t scsiid; /* Our ID and the initiator's ID */
747 uint8_t identify; /* Identify message */
748 uint8_t bytes[22]; /*
749 * Bytes contains any additional message
750 * bytes terminated by 0xFF. The remainder
751 * is the cdb to execute.
752 */
753 uint8_t cmd_valid; /*
754 * When a command is complete, the firmware
755 * will set cmd_valid to all bits set.
756 * After the host has seen the command,
757 * the bits are cleared. This allows us
758 * to just peek at host memory to determine
759 * if more work is complete. cmd_valid is on
760 * an 8 byte boundary to simplify setting
761 * it on aic7880 hardware which only has
762 * limited direct access to the DMA FIFO.
763 */
764 uint8_t pad[7];
765 };
766
767 /*
768 * Number of events we can buffer up if we run out
769 * of immediate notify ccbs.
770 */
771 #define AHC_TMODE_EVENT_BUFFER_SIZE 8
772 struct ahc_tmode_event {
773 uint8_t initiator_id;
774 uint8_t event_type; /* MSG type or EVENT_TYPE_BUS_RESET */
775 #define EVENT_TYPE_BUS_RESET 0xFF
776 uint8_t event_arg;
777 };
778
779 /*
780 * Per enabled lun target mode state.
781 * As this state is directly influenced by the host OS'es target mode
782 * environment, we let the OS module define it. Forward declare the
783 * structure here so we can store arrays of them, etc. in OS neutral
784 * data structures.
785 */
786 #ifdef AHC_TARGET_MODE
787 struct ahc_tmode_lstate {
788 #if 0
789 struct cam_path *path;
790 struct ccb_hdr_slist accept_tios;
791 struct ccb_hdr_slist immed_notifies;
792 #endif
793 struct ahc_tmode_event event_buffer[AHC_TMODE_EVENT_BUFFER_SIZE];
794 uint8_t event_r_idx;
795 uint8_t event_w_idx;
796 };
797 #else
798 struct ahc_tmode_lstate;
799 #endif
800
801 /******************** Transfer Negotiation Datastructures *********************/
802 #define AHC_TRANS_CUR 0x01 /* Modify current negotiation status */
803 #define AHC_TRANS_ACTIVE 0x03 /* Assume this target is on the bus */
804 #define AHC_TRANS_GOAL 0x04 /* Modify negotiation goal */
805 #define AHC_TRANS_USER 0x08 /* Modify user negotiation settings */
806
807 #define AHC_WIDTH_UNKNOWN 0xFF
808 #define AHC_PERIOD_UNKNOWN 0xFF
809 #define AHC_OFFSET_UNKNOWN 0x0
810 #define AHC_PPR_OPTS_UNKNOWN 0xFF
811
812 /*
813 * Transfer Negotiation Information.
814 */
815 struct ahc_transinfo {
816 uint8_t protocol_version; /* SCSI Revision level */
817 uint8_t transport_version; /* SPI Revision level */
818 uint8_t width; /* Bus width */
819 uint8_t period; /* Sync rate factor */
820 uint8_t offset; /* Sync offset */
821 uint8_t ppr_options; /* Parallel Protocol Request options */
822 };
823
824 /*
825 * Per-initiator current, goal and user transfer negotiation information. */
826 struct ahc_initiator_tinfo {
827 uint8_t scsirate; /* Computed value for SCSIRATE reg */
828 struct ahc_transinfo curr;
829 struct ahc_transinfo goal;
830 struct ahc_transinfo user;
831 };
832
833 /*
834 * Per enabled target ID state.
835 * Pointers to lun target state as well as sync/wide negotiation information
836 * for each initiator<->target mapping. For the initiator role we pretend
837 * that we are the target and the targets are the initiators since the
838 * negotiation is the same regardless of role.
839 */
840 struct ahc_tmode_tstate {
841 struct ahc_tmode_lstate* enabled_luns[AHC_NUM_LUNS];
842 struct ahc_initiator_tinfo transinfo[AHC_NUM_TARGETS];
843
844 /*
845 * Per initiator state bitmasks.
846 */
847 uint16_t auto_negotiate;/* Auto Negotiation Required */
848 uint16_t ultraenb; /* Using ultra sync rate */
849 uint16_t discenable; /* Disconnection allowed */
850 uint16_t tagenable; /* Tagged Queuing allowed */
851 };
852
853 /*
854 * Data structure for our table of allowed synchronous transfer rates.
855 */
856 struct ahc_syncrate {
857 u_int sxfr_u2; /* Value of the SXFR parameter for Ultra2+ Chips */
858 u_int sxfr; /* Value of the SXFR parameter for <= Ultra Chips */
859 #define ULTRA_SXFR 0x100 /* Rate Requires Ultra Mode set */
860 #define ST_SXFR 0x010 /* Rate Single Transition Only */
861 #define DT_SXFR 0x040 /* Rate Double Transition Only */
862 uint8_t period; /* Period to send to SCSI target */
863 const char *rate;
864 };
865
866 /* Safe and valid period for async negotiations. */
867 #define AHC_ASYNC_XFER_PERIOD 0x45
868 #define AHC_ULTRA2_XFER_PERIOD 0x0a
869
870 /*
871 * Indexes into our table of syncronous transfer rates.
872 */
873 #define AHC_SYNCRATE_DT 0
874 #define AHC_SYNCRATE_ULTRA2 1
875 #define AHC_SYNCRATE_ULTRA 3
876 #define AHC_SYNCRATE_FAST 6
877 #define AHC_SYNCRATE_MAX AHC_SYNCRATE_DT
878 #define AHC_SYNCRATE_MIN 13
879
880 /***************************** Lookup Tables **********************************/
881 /*
882 * Phase -> name and message out response
883 * to parity errors in each phase table.
884 */
885 struct ahc_phase_table_entry {
886 uint8_t phase;
887 uint8_t mesg_out; /* Message response to parity errors */
888 const char *phasemsg;
889 };
890
891 /************************** Serial EEPROM Format ******************************/
892
893 struct seeprom_config {
894 /*
895 * Per SCSI ID Configuration Flags
896 */
897 uint16_t device_flags[16]; /* words 0-15 */
898 #define CFXFER 0x0007 /* synchronous transfer rate */
899 #define CFSYNCH 0x0008 /* enable synchronous transfer */
900 #define CFDISC 0x0010 /* enable disconnection */
901 #define CFWIDEB 0x0020 /* wide bus device */
902 #define CFSYNCHISULTRA 0x0040 /* CFSYNCH is an ultra offset (2940AU)*/
903 #define CFSYNCSINGLE 0x0080 /* Single-Transition signalling */
904 #define CFSTART 0x0100 /* send start unit SCSI command */
905 #define CFINCBIOS 0x0200 /* include in BIOS scan */
906 #define CFRNFOUND 0x0400 /* report even if not found */
907 #define CFMULTILUNDEV 0x0800 /* Probe multiple luns in BIOS scan */
908 #define CFWBCACHEENB 0x4000 /* Enable W-Behind Cache on disks */
909 #define CFWBCACHENOP 0xc000 /* Don't touch W-Behind Cache */
910
911 /*
912 * BIOS Control Bits
913 */
914 uint16_t bios_control; /* word 16 */
915 #define CFSUPREM 0x0001 /* support all removable drives */
916 #define CFSUPREMB 0x0002 /* support removable boot drives */
917 #define CFBIOSEN 0x0004 /* BIOS enabled */
918 #define CFBIOS_BUSSCAN 0x0008 /* Have the BIOS Scan the Bus */
919 #define CFSM2DRV 0x0010 /* support more than two drives */
920 #define CFSTPWLEVEL 0x0010 /* Termination level control */
921 #define CF284XEXTEND 0x0020 /* extended translation (284x cards) */
922 #define CFCTRL_A 0x0020 /* BIOS displays Ctrl-A message */
923 #define CFTERM_MENU 0x0040 /* BIOS displays termination menu */
924 #define CFEXTEND 0x0080 /* extended translation enabled */
925 #define CFSCAMEN 0x0100 /* SCAM enable */
926 #define CFMSG_LEVEL 0x0600 /* BIOS Message Level */
927 #define CFMSG_VERBOSE 0x0000
928 #define CFMSG_SILENT 0x0200
929 #define CFMSG_DIAG 0x0400
930 #define CFBOOTCD 0x0800 /* Support Bootable CD-ROM */
931 /* UNUSED 0xff00 */
932
933 /*
934 * Host Adapter Control Bits
935 */
936 uint16_t adapter_control; /* word 17 */
937 #define CFAUTOTERM 0x0001 /* Perform Auto termination */
938 #define CFULTRAEN 0x0002 /* Ultra SCSI speed enable */
939 #define CF284XSELTO 0x0003 /* Selection timeout (284x cards) */
940 #define CF284XFIFO 0x000C /* FIFO Threshold (284x cards) */
941 #define CFSTERM 0x0004 /* SCSI low byte termination */
942 #define CFWSTERM 0x0008 /* SCSI high byte termination */
943 #define CFSPARITY 0x0010 /* SCSI parity */
944 #define CF284XSTERM 0x0020 /* SCSI low byte term (284x cards) */
945 #define CFMULTILUN 0x0020
946 #define CFRESETB 0x0040 /* reset SCSI bus at boot */
947 #define CFCLUSTERENB 0x0080 /* Cluster Enable */
948 #define CFBOOTCHAN 0x0300 /* probe this channel first */
949 #define CFBOOTCHANSHIFT 8
950 #define CFSEAUTOTERM 0x0400 /* Ultra2 Perform secondary Auto Term*/
951 #define CFSELOWTERM 0x0800 /* Ultra2 secondary low term */
952 #define CFSEHIGHTERM 0x1000 /* Ultra2 secondary high term */
953 #define CFENABLEDV 0x4000 /* Perform Domain Validation*/
954
955 /*
956 * Bus Release Time, Host Adapter ID
957 */
958 uint16_t brtime_id; /* word 18 */
959 #define CFSCSIID 0x000f /* host adapter SCSI ID */
960 /* UNUSED 0x00f0 */
961 #define CFBRTIME 0xff00 /* bus release time */
962
963 /*
964 * Maximum targets
965 */
966 uint16_t max_targets; /* word 19 */
967 #define CFMAXTARG 0x00ff /* maximum targets */
968 #define CFBOOTLUN 0x0f00 /* Lun to boot from */
969 #define CFBOOTID 0xf000 /* Target to boot from */
970 uint16_t res_1[10]; /* words 20-29 */
971 uint16_t signature; /* Signature == 0x250 */
972 #define CFSIGNATURE 0x250
973 #define CFSIGNATURE2 0x300
974 uint16_t checksum; /* word 31 */
975 };
976
977 /**************************** Message Buffer *********************************/
978 typedef enum {
979 MSG_TYPE_NONE = 0x00,
980 MSG_TYPE_INITIATOR_MSGOUT = 0x01,
981 MSG_TYPE_INITIATOR_MSGIN = 0x02,
982 MSG_TYPE_TARGET_MSGOUT = 0x03,
983 MSG_TYPE_TARGET_MSGIN = 0x04
984 } ahc_msg_type;
985
986 typedef enum {
987 MSGLOOP_IN_PROG,
988 MSGLOOP_MSGCOMPLETE,
989 MSGLOOP_TERMINATED
990 } msg_loop_stat;
991
992 /*********************** Software Configuration Structure *********************/
993 TAILQ_HEAD(scb_tailq, scb);
994
995 struct ahc_suspend_channel_state {
996 uint8_t scsiseq;
997 uint8_t sxfrctl0;
998 uint8_t sxfrctl1;
999 uint8_t simode0;
1000 uint8_t simode1;
1001 uint8_t seltimer;
1002 uint8_t seqctl;
1003 };
1004
1005 struct ahc_suspend_state {
1006 struct ahc_suspend_channel_state channel[2];
1007 uint8_t optionmode;
1008 uint8_t dscommand0;
1009 uint8_t dspcistatus;
1010 /* hsmailbox */
1011 uint8_t crccontrol1;
1012 uint8_t scbbaddr;
1013 /* Host and sequencer SCB counts */
1014 uint8_t dff_thrsh;
1015 uint8_t *scratch_ram;
1016 uint8_t *btt;
1017 };
1018
1019 typedef void (*ahc_bus_intr_t)(struct ahc_softc *);
1020 typedef void ahc_callback_t (void *);
1021
1022 struct ahc_softc {
1023 device_t sc_dev;
1024
1025 struct scsipi_channel sc_channel;
1026 struct scsipi_channel sc_channel_b;
1027 device_t sc_child;
1028 device_t sc_child_b;
1029 struct scsipi_adapter sc_adapter;
1030
1031 bus_space_tag_t tag;
1032 bus_space_handle_t bsh;
1033
1034 #ifndef __linux__
1035 bus_dma_tag_t buffer_dmat; /* dmat for buffer I/O */
1036 #endif
1037 struct scb_data *scb_data;
1038
1039 struct scb *next_queued_scb;
1040
1041 /*
1042 * SCBs that have been sent to the controller
1043 */
1044 LIST_HEAD(, scb) pending_scbs;
1045
1046 /*
1047 * Counting lock for deferring the release of additional
1048 * untagged transactions from the untagged_queues. When
1049 * the lock is decremented to 0, all queues in the
1050 * untagged_queues array are run.
1051 */
1052 u_int untagged_queue_lock;
1053
1054 /*
1055 * Per-target queue of untagged-transactions. The
1056 * transaction at the head of the queue is the
1057 * currently pending untagged transaction for the
1058 * target. The driver only allows a single untagged
1059 * transaction per target.
1060 */
1061 struct scb_tailq untagged_queues[AHC_NUM_TARGETS];
1062
1063 /*
1064 * Platform specific data.
1065 */
1066 struct ahc_platform_data *platform_data;
1067
1068 /*
1069 * Platform specific device information.
1070 */
1071 /* ahc_dev_softc_t dev_softc; */
1072
1073 /*
1074 * Bus specific device information.
1075 */
1076 ahc_bus_intr_t bus_intr;
1077
1078 /*
1079 * Target mode related state kept on a per enabled lun basis.
1080 * Targets that are not enabled will have null entries.
1081 * As an initiator, we keep one target entry for our initiator
1082 * ID to store our sync/wide transfer settings.
1083 */
1084 struct ahc_tmode_tstate *enabled_targets[AHC_NUM_TARGETS];
1085
1086 char inited_target[AHC_NUM_TARGETS];
1087
1088 /*
1089 * The black hole device responsible for handling requests for
1090 * disabled luns on enabled targets.
1091 */
1092 struct ahc_tmode_lstate *black_hole;
1093
1094 /*
1095 * Device instance currently on the bus awaiting a continue TIO
1096 * for a command that was not given the disconnect priviledge.
1097 */
1098 struct ahc_tmode_lstate *pending_device;
1099
1100 /*
1101 * Card characteristics
1102 */
1103 ahc_chip chip;
1104 ahc_feature features;
1105 ahc_bug bugs;
1106 ahc_flag flags;
1107 struct seeprom_config *seep_config;
1108
1109 /* Values to store in the SEQCTL register for pause and unpause */
1110 uint8_t unpause;
1111 uint8_t pause;
1112
1113 /* Command Queues */
1114 uint8_t qoutfifonext;
1115 uint8_t qinfifonext;
1116 uint8_t *qoutfifo;
1117 uint8_t *qinfifo;
1118
1119 /* Critical Section Data */
1120 struct cs *critical_sections;
1121 u_int num_critical_sections;
1122
1123 /* Links for chaining softcs */
1124 TAILQ_ENTRY(ahc_softc) links;
1125
1126 /* Channel Names ('A', 'B', etc.) */
1127 char channel;
1128
1129 /* Initiator Bus ID */
1130 uint8_t our_id;
1131 uint8_t our_id_b;
1132
1133 /*
1134 * PCI error detection.
1135 */
1136 int unsolicited_ints;
1137
1138 /*
1139 * Target incoming command FIFO.
1140 */
1141 struct target_cmd *targetcmds;
1142 uint8_t tqinfifonext;
1143
1144 /*
1145 * Incoming and outgoing message handling.
1146 */
1147 uint8_t send_msg_perror;
1148 ahc_msg_type msg_type;
1149 uint8_t msgout_buf[12];/* Message we are sending */
1150 uint8_t msgin_buf[12];/* Message we are receiving */
1151 u_int msgout_len; /* Length of message to send */
1152 u_int msgout_index; /* Current index in msgout */
1153 u_int msgin_index; /* Current index in msgin */
1154
1155 /* Interrupt routine */
1156 void *ih;
1157
1158 /*
1159 * Mapping information for data structures shared
1160 * between the sequencer and kernel.
1161 */
1162 bus_dma_tag_t parent_dmat;
1163 bus_dmamap_t shared_data_dmamap;
1164 bus_addr_t shared_data_busaddr;
1165
1166 bus_dma_segment_t shared_data_seg;
1167 int shared_data_nseg;
1168 int shared_data_size;
1169 int sc_dmaflags;
1170
1171 /*
1172 * Bus address of the one byte buffer used to
1173 * work-around a DMA bug for chips <= aic7880
1174 * in target mode.
1175 */
1176 bus_addr_t dma_bug_buf;
1177
1178 /* Information saved through suspend/resume cycles */
1179 struct ahc_suspend_state suspend_state;
1180
1181 /* Number of enabled target mode device on this card */
1182 u_int enabled_luns;
1183
1184 /* Initialization level of this data structure */
1185 u_int init_level;
1186
1187 /* PCI cacheline size. */
1188 u_int pci_cachesize;
1189
1190 u_int stack_size;
1191
1192 /* Per-Unit descriptive information */
1193 const char *description;
1194 const char *name;
1195 int unit;
1196
1197 /* Selection Timer settings */
1198 int seltime;
1199 int seltime_b;
1200
1201 uint16_t user_discenable;/* Disconnection allowed */
1202 uint16_t user_tagenable;/* Tagged Queuing allowed */
1203
1204 struct ahc_pci_busdata *bd;
1205 };
1206
1207 TAILQ_HEAD(ahc_softc_tailq, ahc_softc);
1208 extern struct ahc_softc_tailq ahc_tailq;
1209
1210 /************************ Active Device Information ***************************/
1211 typedef enum {
1212 ROLE_UNKNOWN,
1213 ROLE_INITIATOR,
1214 ROLE_TARGET
1215 } role_t;
1216
1217 struct ahc_devinfo {
1218 int our_scsiid;
1219 int target_offset;
1220 uint16_t target_mask;
1221 u_int target;
1222 u_int lun;
1223 char channel;
1224 role_t role; /*
1225 * Only guaranteed to be correct if not
1226 * in the busfree state.
1227 */
1228 };
1229
1230 /****************************** PCI Structures ********************************/
1231 typedef int (ahc_device_setup_t)(struct ahc_softc *);
1232
1233 struct ahc_pci_identity {
1234 uint64_t full_id;
1235 uint64_t id_mask;
1236 const char *name;
1237 ahc_device_setup_t *setup;
1238 };
1239
1240 /***************************** VL/EISA Declarations ***************************/
1241 struct aic7770_identity {
1242 uint32_t full_id;
1243 uint32_t id_mask;
1244 char *name;
1245 ahc_device_setup_t *setup;
1246 };
1247 extern struct aic7770_identity aic7770_ident_table [];
1248 extern const int ahc_num_aic7770_devs;
1249
1250 #define AHC_EISA_SLOT_OFFSET 0xc00
1251 #define AHC_EISA_IOSIZE 0x100
1252
1253 /*************************** Function Declarations ****************************/
1254 /******************************************************************************/
1255 u_int ahc_index_busy_tcl(struct ahc_softc *, u_int);
1256 void ahc_unbusy_tcl(struct ahc_softc *, u_int);
1257 void ahc_busy_tcl(struct ahc_softc *, u_int, u_int);
1258
1259 /*************************** EISA/VL Front End ********************************/
1260 struct aic7770_identity *aic7770_find_device(uint32_t);
1261 int aic7770_config(struct ahc_softc *,
1262 struct aic7770_identity *, u_int);
1263
1264 /************************** SCB and SCB queue management **********************/
1265 int ahc_probe_scbs(struct ahc_softc *);
1266 void ahc_run_untagged_queues(struct ahc_softc *);
1267 void ahc_run_untagged_queue(struct ahc_softc *, struct scb_tailq *);
1268 void ahc_qinfifo_requeue_tail(struct ahc_softc *, struct scb *);
1269 int ahc_match_scb(struct ahc_softc *, struct scb *,
1270 int, char, int, u_int, role_t);
1271
1272 /****************************** Initialization ********************************/
1273 int ahc_softc_init(struct ahc_softc *);
1274 void ahc_controller_info(struct ahc_softc *, char *, size_t);
1275 int ahc_init(struct ahc_softc *);
1276 void ahc_intr_enable(struct ahc_softc *, int);
1277 void ahc_pause_and_flushwork(struct ahc_softc *);
1278 int ahc_suspend(struct ahc_softc *);
1279 int ahc_resume(struct ahc_softc *);
1280 void ahc_softc_insert(struct ahc_softc *);
1281 struct ahc_softc *ahc_find_softc(struct ahc_softc *);
1282 void ahc_set_unit(struct ahc_softc *, int);
1283 void ahc_set_name(struct ahc_softc *, const char *);
1284 int ahc_alloc_scbs(struct ahc_softc *);
1285 void ahc_free(struct ahc_softc *);
1286 int ahc_reset(struct ahc_softc *);
1287 void ahc_shutdown(void *);
1288
1289 /*************************** Interrupt Services *******************************/
1290 void ahc_clear_intstat(struct ahc_softc *);
1291 void ahc_run_qoutfifo(struct ahc_softc *);
1292 #ifdef AHC_TARGET_MODE
1293 void ahc_run_tqinfifo(struct ahc_softc *, int);
1294 #endif
1295 void ahc_handle_brkadrint(struct ahc_softc *);
1296 void ahc_handle_seqint(struct ahc_softc *, u_int);
1297 void ahc_handle_scsiint(struct ahc_softc *, u_int);
1298 void ahc_clear_critical_section(struct ahc_softc *);
1299
1300 /***************************** Error Recovery *********************************/
1301 typedef enum {
1302 SEARCH_COMPLETE,
1303 SEARCH_COUNT,
1304 SEARCH_REMOVE
1305 } ahc_search_action;
1306 int ahc_search_qinfifo(struct ahc_softc *, int, char,
1307 int, u_int, role_t, uint32_t, ahc_search_action);
1308 int ahc_search_untagged_queues(struct ahc_softc *,
1309 struct scsipi_xfer *, int, char, int, uint32_t,
1310 ahc_search_action);
1311 int ahc_search_disc_list(struct ahc_softc *, int, char,
1312 int, u_int, int, int, int);
1313 void ahc_freeze_devq(struct ahc_softc *, struct scb *);
1314 int ahc_reset_channel(struct ahc_softc *, char, int);
1315 int ahc_abort_scbs(struct ahc_softc *, int, char, int,
1316 u_int, role_t, uint32_t);
1317 void ahc_restart(struct ahc_softc *);
1318 void ahc_calc_residual(struct ahc_softc *, struct scb *);
1319 /*************************** Utility Functions ********************************/
1320 struct ahc_phase_table_entry*
1321 ahc_lookup_phase_entry(int);
1322 void ahc_compile_devinfo(struct ahc_devinfo *, u_int, u_int,
1323 u_int, char, role_t);
1324 /************************** Transfer Negotiation ******************************/
1325 struct ahc_syncrate* ahc_find_syncrate(struct ahc_softc *, u_int *,
1326 u_int *, u_int);
1327 u_int ahc_find_period(struct ahc_softc *, u_int, u_int);
1328 void ahc_validate_offset(struct ahc_softc *,
1329 struct ahc_initiator_tinfo *, struct ahc_syncrate *,
1330 u_int *, int, role_t);
1331 void ahc_validate_width(struct ahc_softc *,
1332 struct ahc_initiator_tinfo *, u_int *, role_t);
1333 /*
1334 * Negotiation types. These are used to qualify if we should renegotiate
1335 * even if our goal and current transport parameters are identical.
1336 */
1337 typedef enum {
1338 AHC_NEG_TO_GOAL, /* Renegotiate only if goal and curr differ. */
1339 AHC_NEG_IF_NON_ASYNC, /* Renegotiate so long as goal is non-async. */
1340 AHC_NEG_ALWAYS /* Renegotiat even if goal is async. */
1341 } ahc_neg_type;
1342 int ahc_update_neg_request(struct ahc_softc *,
1343 struct ahc_devinfo *, struct ahc_tmode_tstate *,
1344 struct ahc_initiator_tinfo*, ahc_neg_type);
1345 void ahc_set_width(struct ahc_softc *, struct ahc_devinfo *,
1346 u_int, u_int, int);
1347 void ahc_set_syncrate(struct ahc_softc *,
1348 struct ahc_devinfo *, struct ahc_syncrate *,
1349 u_int, u_int, u_int, u_int, int);
1350 typedef enum {
1351 AHC_QUEUE_NONE,
1352 AHC_QUEUE_BASIC,
1353 AHC_QUEUE_TAGGED
1354 } ahc_queue_alg;
1355
1356 void ahc_set_tags(struct ahc_softc *, struct ahc_devinfo *,
1357 ahc_queue_alg);
1358
1359 /**************************** Target Mode *************************************/
1360 #ifdef AHC_TARGET_MODE
1361 void ahc_send_lstate_events(struct ahc_softc *,
1362 struct ahc_tmode_lstate *);
1363 void ahc_handle_en_lun(struct ahc_softc *, struct scsipi_xfer *);
1364 cam_status ahc_find_tmode_devs(struct ahc_softc *,
1365 struct ahc_tmode_tstate **, struct ahc_tmode_lstate **,
1366 int);
1367 #ifndef AHC_TMODE_ENABLE
1368 #define AHC_TMODE_ENABLE 0
1369 #endif
1370 #endif
1371 /******************************* Debug ***************************************/
1372 #ifdef AHC_DEBUG
1373 extern uint32_t ahc_debug;
1374 #define AHC_SHOW_MISC 0x0001
1375 #define AHC_SHOW_SENSE 0x0002
1376 #define AHC_DUMP_SEEPROM 0x0004
1377 #define AHC_SHOW_TERMCTL 0x0008
1378 #define AHC_SHOW_MEMORY 0x0010
1379 #define AHC_SHOW_MESSAGES 0x0020
1380 #define AHC_SHOW_DV 0x0040
1381 #define AHC_SHOW_SELTO 0x0080
1382 #define AHC_SHOW_QFULL 0x0200
1383 #define AHC_SHOW_QUEUE 0x0400
1384 #define AHC_SHOW_TQIN 0x0800
1385 #define AHC_SHOW_MASKED_ERRORS 0x1000
1386 #define AHC_DEBUG_SEQUENCER 0x2000
1387 #endif
1388 void ahc_print_scb(struct scb *);
1389 void ahc_print_devinfo(struct ahc_softc *,
1390 struct ahc_devinfo *);
1391 void ahc_dump_card_state(struct ahc_softc *);
1392 int ahc_print_register(ahc_reg_parse_entry_t *, u_int,
1393 const char *, u_int, u_int, u_int *, u_int);
1394 /******************************* SEEPROM *************************************/
1395 int ahc_acquire_seeprom(struct ahc_softc *,
1396 struct seeprom_descriptor *);
1397 void ahc_release_seeprom(struct seeprom_descriptor *);
1398
1399 void ahc_check_extport(struct ahc_softc *, u_int *);
1400 #endif /* _AIC7XXXVAR_H_ */
NetBSD on the FriendlyARM MINI2440