sys/dev/ic/atppcvar.h

   1 /* $NetBSD: atppcvar.h,v 1.10 2008/04/15 15:02:28 cegger Exp $ */
   2
   3 /*-
   4  * Copyright (c) 2001 Alcove - Nicolas Souchu
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  17  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  19  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  20  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  21  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  22  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  23  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  24  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  26  * SUCH DAMAGE.
  27  *
  28  * FreeBSD: src/sys/isa/ppcreg.h,v 1.10.2.4 2001/10/02 05:21:45 nsouch Exp
  29  *
  30  */
  31
  32 #ifndef __ATPPCVAR_H
  33 #define __ATPPCVAR_H
  34
  35 #include <sys/bus.h>
  36 #include <machine/types.h>
  37 #include <sys/device.h>
  38 #include <sys/callout.h>
  39 #include <sys/simplelock.h>
  40
  41 #include <dev/ppbus/ppbus_conf.h>
  42
  43
  44 /* Maximum time to wait for device response */
  45 #define MAXBUSYWAIT     (5 * (hz))
  46
  47 /* Poll interval when wating for device to become ready */
  48 #define ATPPC_POLL      ((hz)/10)
  49
  50 /* Interrupt priority level for atppc device */
  51 #define IPL_ATPPC       IPL_TTY
  52 #define splatppc        spltty
  53
  54
  55 /* Diagnostic and verbose printing macros */
  56
  57 #ifdef ATPPC_DEBUG
  58 extern int atppc_debug;
  59 #define ATPPC_DPRINTF(arg) if(atppc_debug) printf arg
  60 #else
  61 #define ATPPC_DPRINTF(arg)
  62 #endif
  63
  64 #ifdef ATPPC_VERBOSE
  65 extern int atppc_verbose;
  66 #define ATPPC_VPRINTF(arg) if(atppc_verbose) printf arg
  67 #else
  68 #define ATPPC_VPRINTF(arg)
  69 #endif
  70
  71
  72 /* Flag used in DMA transfer */
  73 #define ATPPC_DMA_MODE_READ 0x0
  74 #define ATPPC_DMA_MODE_WRITE 0x1
  75
  76
  77 /* Flags passed via config */
  78 #define ATPPC_FLAG_DISABLE_INTR 0x01
  79 #define ATPPC_FLAG_DISABLE_DMA  0x02
  80
  81
  82 /* Locking for atppc device */
  83 #if defined(MULTIPROCESSOR) || defined (LOCKDEBUG)
  84 #include <sys/lock.h>
  85 #define ATPPC_SC_LOCK(sc) (&((sc)->sc_lock))
  86 #define ATPPC_LOCK_INIT(sc) simple_lock_init(ATPPC_SC_LOCK((sc)))
  87 #define ATPPC_LOCK(sc) simple_lock(ATPPC_SC_LOCK((sc)))
  88 #define ATPPC_UNLOCK(sc) simple_unlock(ATPPC_SC_LOCK((sc)))
  89 #else /* !(MULTIPROCESSOR) && !(LOCKDEBUG) */
  90 #define ATPPC_LOCK_INIT(sc)
  91 #define ATPPC_LOCK(sc)
  92 #define ATPPC_UNLOCK(sc)
  93 #define ATPPC_SC_LOCK(sc) NULL
  94 #endif /* MULTIPROCESSOR || LOCKDEBUG */
  95
  96 /* Single softintr callback entry */
  97 struct atppc_handler_node {
  98         void (*func)(void *);
  99         void *arg;
 100         SLIST_ENTRY(atppc_handler_node) entries;
 101 };
 102
 103 /* Generic structure to hold parallel port chipset info. */
 104 struct atppc_softc {
 105         /* Generic device attributes */
 106         device_t sc_dev;
 107
 108 #if defined(MULTIPROCESSOR) || defined(LOCKDEBUG)
 109         /* Simple lock */
 110         struct simplelock sc_lock;
 111 #endif
 112
 113         /* Machine independent bus infrastructure */
 114         bus_space_tag_t sc_iot;
 115         bus_space_handle_t sc_ioh;
 116         bus_dma_tag_t sc_dmat;
 117         bus_dmamap_t sc_dmapt;
 118         bus_size_t sc_dma_maxsize;
 119
 120         /* Child device */
 121         device_t child;
 122
 123         /* Opaque handle used for interrupt handler establishment */
 124         void *sc_ieh;
 125
 126         /* List of soft interrupts to call */
 127         SLIST_HEAD(handler_list, atppc_handler_node) sc_handler_listhead;
 128
 129          /* Input buffer: working pointers, and size in bytes. */
 130         char * sc_inb;
 131         char * sc_inbstart;
 132         u_int32_t sc_inb_nbytes;
 133         int sc_inerr;
 134
 135         /* Output buffer pointer, working pointer, and size in bytes. */
 136         char * sc_outb;
 137         char * sc_outbstart;
 138         u_int32_t sc_outb_nbytes;
 139         int sc_outerr;
 140
 141         /* DMA functions: setup by bus specific attach code */
 142         int (*sc_dma_start)(struct atppc_softc *, void *, u_int, u_int8_t);
 143         int (*sc_dma_finish)(struct atppc_softc *);
 144         int (*sc_dma_abort)(struct atppc_softc *);
 145         int (*sc_dma_malloc)(device_t, void **, bus_addr_t *,
 146                 bus_size_t);
 147         void (*sc_dma_free)(device_t, void **, bus_addr_t *,
 148                 bus_size_t);
 149
 150         /* Microsequence related members */
 151         char * sc_ptr;          /* microseq current pointer */
 152         int sc_accum;           /* microseq accumulator */
 153
 154         /* Device attachment state */
 155 #define ATPPC_ATTACHED 1
 156 #define ATPPC_NOATTACH 0
 157         u_int8_t sc_dev_ok;
 158
 159         /*
 160          * Hardware capabilities flags: standard mode and nibble mode are
 161          * assumed to always be available since if they aren't you don't
 162          * HAVE a parallel port.
 163          */
 164 #define ATPPC_HAS_INTR  0x01    /* Interrupt available */
 165 #define ATPPC_HAS_DMA   0x02    /* DMA available */
 166 #define ATPPC_HAS_FIFO  0x04    /* FIFO available */
 167 #define ATPPC_HAS_PS2   0x08    /* PS2 mode capable */
 168 #define ATPPC_HAS_ECP   0x10    /* ECP mode available */
 169 #define ATPPC_HAS_EPP   0x20    /* EPP mode available */
 170         u_int8_t sc_has;        /* Chipset detected capabilities */
 171
 172         /* Flags specifying mode of chipset operation . */
 173 #define ATPPC_MODE_STD  0x01    /* Use centronics-compatible mode */
 174 #define ATPPC_MODE_PS2  0x02    /* Use PS2 mode */
 175 #define ATPPC_MODE_EPP  0x04    /* Use EPP mode */
 176 #define ATPPC_MODE_ECP  0x08    /* Use ECP mode */
 177 #define ATPPC_MODE_NIBBLE 0x10  /* Use nibble mode */
 178 #define ATPPC_MODE_FAST 0x20    /* Use Fast Centronics mode */
 179         u_int8_t sc_mode;       /* Current operational mode */
 180
 181         /* Flags which further define chipset operation */
 182 #define ATPPC_USE_INTR  0x01    /* Use interrupts */
 183 #define ATPPC_USE_DMA   0x02    /* Use DMA */
 184         u_int8_t sc_use;        /* Capabilities to use */
 185
 186         /* Parallel Port Chipset model. */
 187 #define SMC_LIKE        0
 188 #define SMC_37C665GT    1
 189 #define SMC_37C666GT    2
 190 #define NS_PC87332      3
 191 #define NS_PC87306      4
 192 #define INTEL_820191AA  5       /* XXX not implemented */
 193 #define GENERIC         6
 194 #define WINB_W83877F    7
 195 #define WINB_W83877AF   8
 196 #define WINB_UNKNOWN    9
 197 #define NS_PC87334      10
 198 #define SMC_37C935      11
 199 #define NS_PC87303      12
 200         u_int8_t sc_model;      /* chipset model */
 201
 202         /* EPP mode */
 203 #define ATPPC_EPP_1_9   0x0
 204 #define ATPPC_EPP_1_7   0x1
 205         u_int8_t sc_epp;
 206
 207         /* Parallel Port Chipset Type. SMC versus GENERIC (others) */
 208 #define ATPPC_TYPE_SMCLIKE 0
 209 #define ATPPC_TYPE_GENERIC 1
 210         u_int8_t sc_type;       /* generic or smclike chipset type */
 211
 212         /* Stored register values after an interrupt occurs */
 213         u_int8_t sc_ecr_intr;
 214         u_int8_t sc_ctr_intr;
 215         u_int8_t sc_str_intr;
 216
 217 #define ATPPC_IRQ_NONE  0x0
 218 #define ATPPC_IRQ_nACK  0x1
 219 #define ATPPC_IRQ_DMA   0x2
 220 #define ATPPC_IRQ_FIFO  0x4
 221 #define ATPPC_IRQ_nFAULT        0x8
 222         u_int8_t sc_irqstat;    /* Record irq settings */
 223
 224 #define ATPPC_DMA_INIT          0x01
 225 #define ATPPC_DMA_STARTED       0x02
 226 #define ATPPC_DMA_COMPLETE      0x03
 227 #define ATPPC_DMA_INTERRUPTED   0x04
 228 #define ATPPC_DMA_ERROR         0x05
 229         u_int8_t sc_dmastat;    /* Record dma state */
 230
 231 #define ATPPC_PWORD_MASK        0x30
 232 #define ATPPC_PWORD_16  0x00
 233 #define ATPPC_PWORD_8   0x10
 234 #define ATPPC_PWORD_32  0x20
 235         u_int8_t sc_pword;      /* PWord size: used for FIFO DMA transfers */
 236         u_int8_t sc_fifo;       /* FIFO size */
 237
 238         /* Indicates number of PWords in FIFO queues that generate interrupt */
 239         u_int8_t sc_wthr;       /* writeIntrThresold */
 240         u_int8_t sc_rthr;       /* readIntrThresold */
 241 };
 242
 243
 244
 245 #ifdef _KERNEL
 246
 247 /* Function prototypes */
 248
 249 /* Soft config attach/detach routines */
 250 void atppc_sc_attach(struct atppc_softc *);
 251 int atppc_sc_detach(struct atppc_softc *, int);
 252
 253 /* Detection routines */
 254 int atppc_detect_port(bus_space_tag_t, bus_space_handle_t);
 255
 256 /* Interrupt handler for atppc device */
 257 int atppcintr(void *);
 258
 259 #endif /* _KERNEL */
 260
 261 #endif /* __ATPPCVAR_H */