1 /* $NetBSD: cd18xxreg.h,v 1.3 2005/12/11 12:21:26 christos Exp $ */
4 * Copyright (c) 1998, 2001 Matthew R. Green
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * cirrus-logic CL-CD180/CD1864/CD1865 register definitions, from the
31 * CL-CD1865 data book.
36 * available registers for us.
38 * the cd1865 provides 4 types of registers: global, indexed indirect,
39 * channel, and unavailable. we should never touch the unavailable, as it
40 * may cause the cd1865 to fail. the indexed indirect registers are
41 * really pointers to the correct channel we are currently servicing, and
42 * as such must only be accessed during service-request service routines.
43 * global registers set and provide common functionality between all of
44 * the channels. channel registers only affect the specific channel.
45 * access to channel registers is limited to the current channel, as
46 * specified in the CAR register, ie. to access different channels, the CAR
47 * register must be changed first.
52 * the registers themselves.
55 /* global registers */
56 #define CD18xx_GFRCR 0x6b /* global firmware revision code */
57 #define CD18xx_SRCR 0x66 /* service request configuration */
58 #define CD18xx_PPRH 0x70 /* prescaler period (high) */
59 #define CD18xx_PPRL 0x71 /* prescaler period (low) */
60 #define CD18xx_MSMR 0x61 /* modem service match */
61 #define CD18xx_TSMR 0x62 /* transmit service match */
62 #define CD18xx_RSMR 0x63 /* receive service match */
63 #define CD18xx_GSVR 0x40 /* global service vector */
64 #define CD18xx_SRSR 0x65 /* service request status */
65 #define CD18xx_MRAR 0x75 /* modem request acknowledge */
66 #define CD18xx_TRAR 0x76 /* transmit request acknowledge */
67 #define CD18xx_RRAR 0x77 /* receive request acknowledge */
68 #define CD18xx_GSCR1 0x41 /* global service channel (1) */
69 #define CD18xx_GSCR2 0x42 /* global service channel (2) */
70 #define CD18xx_GSCR3 0x43 /* global service channel (3) */
71 #define CD18xx_CAR 0x64 /* channel access register */
73 /* indexed indirect registers */
74 #define CD18xx_RDCR 0x07 /* receive data count */
75 #define CD18xx_RDR 0x78 /* receiver data register */
76 #define CD18xx_RCSR 0x7a /* receiver channel status */
77 #define CD18xx_TDR 0x7b /* transmit data register */
78 #define CD18xx_EOSRR 0x7f /* end of service request */
80 /* channel registers */
81 #define CD18xx_SRER 0x02 /* service request enable */
82 #define CD18xx_CCR 0x01 /* channel command */
83 #define CD18xx_COR1 0x03 /* channel option (1) */
84 #define CD18xx_COR2 0x04 /* channel option (2) */
85 #define CD18xx_COR3 0x05 /* channel option (3) */
86 #define CD18xx_CCSR 0x06 /* channel control status */
87 #define CD18xx_RBR 0x33 /* receiver bit */
88 #define CD18xx_RTPR 0x18 /* receive time-out period */
89 #define CD18xx_RBPRH 0x31 /* receive bit rate period (high) */
90 #define CD18xx_RBPRL 0x32 /* receive bit rate period (low) */
91 #define CD18xx_TBPRH 0x39 /* transmit bit rate period (high) */
92 #define CD18xx_TBPRL 0x3a /* transmit bit rate period (low) */
93 #define CD18xx_SCHR1 0x09 /* special character (1) */
94 #define CD18xx_SCHR2 0x0a /* special character (2) */
95 #define CD18xx_SCHR3 0x0b /* special character (3) */
96 #define CD18xx_SCHR4 0x0c /* special character (4) */
97 #define CD18xx_MCR 0x10 /* modem change */
98 #define CD18xx_MCOR1 0x10 /* modem change option (1) */
99 #define CD18xx_MCOR2 0x11 /* modem change option (2) */
100 #define CD18xx_MSVR 0x28 /* modem signal value */
101 #define CD18xx_MSVRTS 0x29 /* modem signal value RTS */
102 #define CD18xx_MSVDTR 0x2a /* mdoem signal value DTR */
106 * inside the registers
109 /* global registers */
111 /* global firmware revision code */
112 #define CD180_GFRCR_REV_B 0x81 /* CL-CD180B */
113 #define CD180_GFRCR_REV_C 0x82 /* CL-CD180C */
114 #define CD1864_GFRCR_REVISION_A 0x82 /* CL-CD1864A */
115 #define CD1865_GFRCR_REVISION_A 0x83 /* CL-CD1865A */
116 #define CD1865_GFRCR_REVISION_B 0x84 /* CL-CD1865B */
117 #define CD1865_GFRCR_REVISION_C 0x85 /* CL-CD1865C */
119 /* service request configuration register */
120 #define CD18xx_SRCR_PKGTYP 0x80 /* package type (RO) */
121 #define CD18xx_SRCR_REGACKEN 0x40 /* enable register acks */
122 #define CD18xx_SRCR_DAISYEN 0x20 /* enable daisy-chain */
123 #define CD18xx_SRCR_GLOBPRI 0x10 /* global priority */
124 #define CD18xx_SRCR_UNFAIR 0x08 /* unfair override */
125 #define CD18xx_SRCR_AUTOPRI 0x02 /* auto prioritizing */
126 #define CD18xx_SRCR_PRISEL 0x01 /* priority selection */
128 /* global service vector register */
129 #define CD18xx_GSVR_CLEAR 0x00 /* clear GSVR for reset */
130 #define CD18xx_GSVR_READY 0xff /* modem is ready */
131 #define CD18xx_GSVR_IDMASK 0xf8 /* unique ID per-chip */
132 #define CD18xx_GSVR_SETID(sc) ((((sc)->sc_chip_id & ~1) << 5) | \
133 (((sc)->sc_chip_id & 1) << 3))
134 #define CD18xx_GSVR_GROUPTYPE 0x07 /* group/type */
135 #define CD18xx_GSVR_NOREQPEND 0x00 /* no request pending */
136 #define CD18xx_GSVR_MODEM 0x01 /* modem signal change */
137 #define CD18xx_GSVR_TXDATA 0x02 /* tx data */
138 #define CD18xx_GSVR_RXDATA 0x03 /* rx good data */
139 #define CD18xx_GSVR_RXEXCEPTION 0x07 /* request exception */
140 #define CD18xx_GSVR_RXINTR(x) \
141 (((x) & CD18xx_GSVR_GROUPTYPE) == CD18xx_GSVR_RXDATA || \
142 ((x) & CD18xx_GSVR_GROUPTYPE) == CD18xx_GSVR_RXEXCEPTION)
143 #define CD18xx_GSVR_TXINTR(x) \
144 (((x) & CD18xx_GSVR_GROUPTYPE) == CD18xx_GSVR_TXDATA)
145 #define CD18xx_GSVR_MXINTR(x) \
146 (((x) & CD18xx_GSVR_GROUPTYPE) == CD18xx_GSVR_MODEM)
148 /* service request status register */
149 #define CD18xx_SRSR_CONTEXT 0xc0 /* service request context */
150 #define CD18xx_SRSR_PENDING 0x15 /* get status bits for each */
151 #define CD18xx_SRSR_RxPEND 0x10 /* got a Rx interrupt */
152 #define CD18xx_SRSR_TxPEND 0x04 /* got a Tx interrupt */
153 #define CD18xx_SRSR_MxPEND 0x01 /* got a modem interrupt */
155 /* global service channel registers */
156 #define CD18xx_GSCR_USER1 0xe0 /* 3 bits of user-defined data */
157 #define CD18xx_GSCR_CAR 0x1c /* CAR of current channel */
158 #define CD18xx_GSCR_USER2 0x03 /* 2 bits of user-defined data */
160 /* indexed indirect registers */
162 /* receive data count register */
163 #define CD18xx_RDCR_ZERO 0xf0 /* reserved, must be zero */
164 #define CD18xx_RDCR_GOODBYTES 0x0f /* number of good bytes */
166 /* receive character status register */
167 #define CD18xx_RCSR_TIMEOUT 0x80 /* timeout has occurred on channel */
168 #define CD18xx_RCSR_SCD 0x70 /* special character detect */
169 #define CD18xx_RCSR_BREAK 0x08 /* line break detected */
170 #define CD18xx_RCSR_PARITYERR 0x04 /* parity error detected */
171 #define CD18xx_RCSR_FRAMERR 0x02 /* framing error detected */
172 #define CD18xx_RCSR_OVERRUNERR 0x01 /* overrun error detected */
174 /* transmit data register */
175 #define CD18xx_TDR_ETC_BYTE 0x00 /* first byte of break message */
176 #define CD18xx_TDR_BREAK_BYTE 0x81 /* first byte of break message */
177 #define CD18xx_TDR_NOBREAK_BYTE 0x83 /* first byte of clean break message */
179 /* channel registers */
181 /* service request enable register */
182 #define CD18xx_SRER_DSR 0x80 /* DSR service request */
183 #define CD18xx_SRER_CD 0x40 /* CD service request */
184 #define CD18xx_SRER_CTS 0x20 /* CTS service request */
185 #define CD18xx_SRER_Rx 0x10 /* Rx data service request */
186 #define CD18xx_SRER_RxSC 0x08 /* Rx special char service request */
187 #define CD18xx_SRER_Tx 0x04 /* Tx ready service request */
188 #define CD18xx_SRER_TxEMPTY 0x02 /* Tx empty service request */
189 #define CD18xx_SRER_NNDT 0x01 /* no new data timeout service request */
191 /* channel command register */
192 #define CD18xx_CCR_RESET 0x80 /* reset channel command */
193 #define CD18xx_CCR_CORCHG 0x40 /* COR change command */
194 #define CD18xx_CCR_SENDSC 0x20 /* send special character command */
195 #define CD18xx_CCR_CHANCTL 0x10 /* channel control command */
197 /* bits inside CCR's least significant half-byte */
198 #define CD18xx_CCR_RESET_HARD 0x01 /* full, hard reset */
199 #define CD18xx_CCR_RESET_CHAN 0x00 /* reset only the current channel */
200 #define CD18xx_CCR_CORCHG_COR3 0x08 /* change COR3 command */
201 #define CD18xx_CCR_CORCHG_COR2 0x04 /* change COR2 command */
202 #define CD18xx_CCR_CORCHG_COR1 0x02 /* change COR1 command */
203 #define CD18xx_CCR_SENDSC_SEND1 0x01 /* send SC 1, or 1&3 */
204 #define CD18xx_CCR_SENDSC_SEND2 0x02 /* send SC 2, or 2&4 */
205 #define CD18xx_CCR_SENDSC_SEND3 0x03 /* send SC 3 */
206 #define CD18xx_CCR_SENDSC_SEND4 0x04 /* send SC 4 */
207 /* note that these are slower than enabling/disabling SRER */
208 #define CD18xx_CCR_CHANCTL_TxEN 0x08 /* transmitter enable */
209 #define CD18xx_CCR_CHANCTL_TxDI 0x04 /* transmitter disable */
210 #define CD18xx_CCR_CHANCTL_RxEN 0x02 /* receiver enable */
211 #define CD18xx_CCR_CHANCTL_RxDI 0x01 /* receiver disable */
213 /* channel option register 1 */
214 #define CD18xx_COR1_PARITY 0x80 /* parity */
215 #define CD18xx_COR1_PARITY_ODD 0x80 /* odd parity */
216 #define CD18xx_COR1_PARITY_EVEN 0x00 /* even parity */
217 #define CD18xx_COR1_PARITY_MODE 0x60 /* parity mode */
218 #define CD18xx_COR1_PARITY_NONE 0x00 /* no parity */
219 #define CD18xx_COR1_PARITY_FORCE 0x20 /* force parity */
220 #define CD18xx_COR1_PARITY_NORMAL 0x40 /* normal parity */
221 #define CD18xx_COR1_IGNORE 0x10 /* parity ignore mode */
222 #define CD18xx_COR1_STOPBITLEN 0x0c /* stop bit length */
223 #define CD18xx_COR1_STOPBIT_1 0x00 /* 1 stop bit */
224 #define CD18xx_COR1_STOPBIT_1_5 0x04 /* 1.5 stop bits */
225 #define CD18xx_COR1_STOPBIT_2 0x08 /* 2 stop bits */
226 #define CD18xx_COR1_STOPBIT_2_5 0x0c /* 2.5 stop bits */
227 #define CD18xx_COR1_CHARLEN 0x03 /* character length */
228 #define CD18xx_COR1_CS5 0x00 /* 5 bit chars */
229 #define CD18xx_COR1_CS6 0x01 /* 7 bit chars */
230 #define CD18xx_COR1_CS7 0x02 /* 7 bit chars */
231 #define CD18xx_COR1_CS8 0x03 /* 8 bit chars */
233 /* channel option register 2 */
234 #define CD18xx_COR2_IXM 0x80 /* implied XON mode */
235 #define CD18xx_COR2_TxIBE 0x40 /* Tx inband flow control auto enable */
236 #define CD18xx_COR2_ETC 0x20 /* embedded Tx command enable */
237 #define CD18xx_COR2_LLM 0x10 /* local loopback mode */
238 #define CD18xx_COR2_RLM 0x08 /* remote loopback mode */
239 #define CD18xx_COR2_RTSAOE 0x04 /* RTS auto output enable */
240 #define CD18xx_COR2_CTSAE 0x02 /* CTS auto enable */
241 #define CD18xx_COR2_DSRAE 0x01 /* DSR auto enable */
243 /* channel option register 3 */
244 #define CD18xx_COR3_XONCH 0x80 /* XON character definition */
245 #define CD18xx_COR3_XOFFCH 0x40 /* XOFF character definition */
246 #define CD18xx_COR3_FCTM 0x20 /* flow control transparency mode */
247 #define CD18xx_COR3_SCDE 0x10 /* special character detection enable */
248 #define CD18xx_COR3_FIFOTHRESH 0x08 /* Rx FIFO threshold */
250 /* channel control status register */
251 #define CD18xx_CCSR_RxEN 0x80 /* Rx enable */
252 #define CD18xx_CCSR_RxFLOFF 0x40 /* Rx flow control off enable */
253 #define CD18xx_CCSR_RxFLON 0x20 /* Rx flow control on enable */
254 #define CD18xx_CCSR_TxEN 0x08 /* Tx enable */
255 #define CD18xx_CCSR_TxFLOFF 0x04 /* Tx flow control off enable */
256 #define CD18xx_CCSR_TxFLON 0x02 /* Tx flow control on enable */
258 /* receiver bit register */
259 #define CD18xx_RBR_RxD 0x40 /* last RxD input */
260 #define CD18xx_RBR_STARTHUNT 0x20 /* hunting for a start bit */
262 /* bit rate period resisters */
263 #define CD18xx_xBRPR_TPC 0x10 /* ticks per character */
265 /* mode change register */
266 #define CD18xx_MCR_DSR 0x80 /* DSR changed */
267 #define CD18xx_MCR_CD 0x40 /* CD changed */
268 #define CD18xx_MCR_CTS 0x20 /* CST changed */
270 /* modem change option register 1 */
271 #define CD18xx_MCOR1_DSR 0x80 /* high-to-low on DSR */
272 #define CD18xx_MCOR1_CD 0x40 /* high-to-low on CD */
273 #define CD18xx_MCOR1_CTS 0x20 /* high-to-low on CTS */
274 #define CD18xx_MCOR1_DTR 0x08 /* high-to-low on DSR mode */
276 /* modem change option register 2 */
277 #define CD18xx_MCOR2_DSR 0x80 /* low-to-high on DSR */
278 #define CD18xx_MCOR2_CD 0x40 /* low-to-high on CD */
279 #define CD18xx_MCOR2_CTS 0x20 /* low-to-high on CST */
281 /* modem signal value register */
282 #define CD18xx_MSVR_DSR 0x80 /* current DSR state */
283 #define CD18xx_MSVR_CD 0x40 /* current CD state */
284 #define CD18xx_MSVR_CTS 0x20 /* current CTS state */
285 #define CD18xx_MSVR_DTR 0x02 /* current DTR state */
286 #define CD18xx_MSVR_RTS 0x01 /* current RTS state */
287 #define CD18xx_MSVR_RESET (CD18xx_MSVR_DSR|CD18xx_MSVR_CD| \
288 CD18xx_MSVR_CTS|CD18xx_MSVR_DTR| \
291 /* modem signal value request-to-send register */
292 #define CD18xx_MSVRTS_RTS 0x01 /* change RTS and not DTR */
294 /* modem signal value data-terminal-ready register */
295 #define CD18xx_MSVDTR_DTR 0x01 /* change DTR and not RTS */
