sys/dev/ic/cissreg.h

   1 /*      $NetBSD: cissreg.h,v 1.2 2008/05/25 20:08:34 mhitch Exp $       */
   2 /*      $OpenBSD: cissreg.h,v 1.4 2005/12/13 15:55:59 brad Exp $        */
   3
   4 /*
   5  * Copyright (c) 2005 Michael Shalayeff
   6  * All rights reserved.
   7  *
   8  * Permission to use, copy, modify, and distribute this software for any
   9  * purpose with or without fee is hereby granted, provided that the above
  10  * copyright notice and this permission notice appear in all copies.
  11  *
  12  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  13  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  14  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  15  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  16  * WHATSOEVER RESULTING FROM LOSS OF MIND, USE, DATA OR PROFITS, WHETHER IN
  17  * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
  18  * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  19  */
  20
  21 #define CISS_BIGBIT     0x80    /* texas radio and the big beat! */
  22
  23 #define CISS_IDB        0x20
  24 #define CISS_IDB_CFG    0x01
  25 #define CISS_ISR        0x30
  26 #define CISS_IMR        0x34
  27 #define CISS_READYENAB  4
  28 #define CISS_READYENA   8
  29 #define CISS_INQ        0x40
  30 #define CISS_OUTQ       0x44
  31 #define CISS_CFG_BAR    0xb4
  32 #define CISS_CFG_OFF    0xb8
  33
  34 #define CISS_DRVMAP_SIZE        (128 / 8)
  35
  36 #define CISS_CMD_CTRL_GET       0x26
  37 #define CISS_CMD_CTRL_SET       0x27
  38 /* sub-commands for GET/SET */
  39 #define CISS_CMS_CTRL_LDID      0x10
  40 #define CISS_CMS_CTRL_CTRL      0x11
  41 #define CISS_CMS_CTRL_LDSTAT    0x12
  42 #define CISS_CMS_CTRL_PDID      0x15
  43 #define CISS_CMS_CTRL_PDBLINK   0x16
  44 #define CISS_CMS_CTRL_PDBLSENS  0x17
  45 #define CISS_CMS_CTRL_LDIDEXT   0x18
  46 #define CISS_CMS_CTRL_REDSTAT   0x82
  47 #define CISS_CMS_CTRL_FLUSH     0xc2
  48 #define CISS_CMS_CTRL_ACCEPT    0xe0
  49
  50 #define CISS_CMD_READ   0xc0
  51 #define CISS_CMD_READ_EVENT     0xd0
  52 #define CISS_EVENT_RECENT       0x08    /* ignore previous events */
  53 #define CISS_EVENT_RSTOLD       0x04    /* start w/ the oldest one */
  54 #define CISS_EVENT_ORDER        0x02    /* keep the order */
  55 #define CISS_EVENT_SYNC         0x01    /* sync mode: wait till new come */
  56 #define CISS_CMD_LDMAP  0xc2
  57 #define CISS_CMD_PDMAP  0xc3
  58
  59 #define ciss_bitset(d, v)       ((v)[(d) >> 3] & (1 << ((d) & 7)))
  60
  61 struct ciss_softc;
  62
  63 struct ciss_config {
  64         u_int32_t       signature;
  65 #define CISS_SIGNATURE  (*(const u_int32_t *)"CISS")
  66         u_int32_t       version;
  67         u_int32_t       methods;
  68 #define CISS_METH_READY 0x0001
  69 #define CISS_METH_SIMPL 0x0002
  70 #define CISS_METH_PERF  0x0004
  71 #define CISS_METH_EMQ   0x0008
  72         u_int32_t       amethod;
  73         u_int32_t       rmethod;
  74         u_int32_t       paddr_lim;
  75         u_int32_t       int_delay;
  76         u_int32_t       int_count;
  77         u_int32_t       maxcmd;
  78         u_int32_t       scsibus;
  79 #define CISS_BUS_U2     0x0001
  80 #define CISS_BUS_U3     0x0002
  81 #define CISS_BUS_FC1    0x0100
  82 #define CISS_BUS_FC2    0x0200
  83         u_int32_t       troff;
  84         u_int8_t        hostname[16];
  85         u_int32_t       heartbeat;
  86         u_int32_t       driverf;
  87 #define CISS_DRV_UATT   0x0001
  88 #define CISS_DRV_QINI   0x0002
  89 #define CISS_DRV_LCKINT 0x0004
  90 #define CISS_DRV_QTAGS  0x0008
  91 #define CISS_DRV_ALPHA  0x0010
  92 #define CISS_DRV_LUNS   0x0020
  93 #define CISS_DRV_MSGRQ  0x0080
  94 #define CISS_DRV_DBRD   0x0100
  95 #define CISS_DRV_PRF    0x0200
  96         u_int32_t       maxsg;
  97 } __packed;
  98
  99 struct ciss_inquiry {
 100         u_int8_t        numld;
 101         u_int8_t        sign[4];
 102         u_int8_t        fw_running[4];
 103         u_int8_t        fw_stored[4];
 104         u_int8_t        hw_rev;
 105         u_int8_t        resv0[12];
 106         u_int16_t       pci_vendor;
 107         u_int16_t       pci_product;
 108         u_int8_t        resv1[10];
 109         u_int8_t        market_rev;
 110         u_int8_t        flags;
 111 #define CISS_INQ_WIDE   0x08
 112 #define CISS_INQ_BIGMAP 0x80
 113 #define CISS_INQ_BITS   "\020\04WIDE\010BIGMAP"
 114         u_int8_t        resv2[2];
 115         u_int8_t        nscsi_bus;
 116         u_int8_t        resv3[4];
 117         u_int8_t        clk[4];         /* unaligned dumbness */
 118         u_int8_t        buswidth;
 119         u_int8_t        disks[CISS_DRVMAP_SIZE];
 120         u_int8_t        extdisks[CISS_DRVMAP_SIZE];
 121         u_int8_t        nondisks[CISS_DRVMAP_SIZE];
 122 } __packed;
 123
 124 struct ciss_ldmap {
 125         u_int32_t       size;
 126         u_int32_t       resv;
 127         struct {
 128                 u_int32_t tgt;
 129                 u_int32_t tgt2;
 130         } map[1];
 131 } __packed;
 132
 133 struct ciss_flush {
 134         u_int16_t       flush;
 135 #define CISS_FLUSH_ENABLE       0
 136 #define CISS_FLUSH_DISABLE      1
 137         u_int16_t       resv[255];
 138 } __packed;
 139
 140 struct ciss_blink {
 141         u_int32_t       duration;       /* x100ms */
 142         u_int32_t       elapsed;        /* only for sense */
 143         u_int8_t        pdtab[256];
 144 #define CISS_BLINK_ALL  1
 145 #define CISS_BLINK_TIMED 2
 146         u_int8_t        res[248];
 147 } __packed;
 148
 149 struct ciss_ldid {
 150         u_int16_t       blksize;
 151         u_int16_t       nblocks[2];     /* UNALIGNED! */
 152         u_int8_t        params[16];
 153         u_int8_t        type;
 154 #define CISS_LD_RAID0   0
 155 #define CISS_LD_RAID4   1
 156 #define CISS_LD_RAID1   2
 157 #define CISS_LD_RAID5   3
 158 #define CISS_LD_RAID51  4
 159 #define CISS_LD_RAIDADG 5
 160         u_int8_t        res0;
 161         u_int8_t        bios_dis;
 162         u_int8_t        res1;
 163         u_int32_t       id;
 164         u_int8_t        label[64];
 165         u_int64_t       nbigblocks;
 166         u_int8_t        res2[410];
 167 } __packed;
 168
 169 struct ciss_ldstat {
 170         u_int8_t        stat;
 171 #define CISS_LD_OK      0
 172 #define CISS_LD_FAILED  1
 173 #define CISS_LD_UNCONF  2
 174 #define CISS_LD_DEGRAD  3
 175 #define CISS_LD_RBLDRD  4       /* ready for rebuild */
 176 #define CISS_LD_REBLD   5
 177 #define CISS_LD_PDINV   6       /* wrong phys drive replaced */
 178 #define CISS_LD_PDUNC   7       /* phys drive is not connected proper */
 179 #define CISS_LD_EXPND   10      /* expanding */
 180 #define CISS_LD_NORDY   11      /* volume is not ready */
 181 #define CISS_LD_QEXPND  12      /* queued for expansion */
 182         u_int8_t        failed[4];      /* failed map */
 183         u_int8_t        res0[416];
 184         u_int8_t        prog[4];        /* blocks left to rebuild/expand */
 185         u_int8_t        rebuild;        /* drive that is rebuilding */
 186         u_int16_t       remapcnt[32];   /* count of remapped blocks for pds */
 187         u_int8_t        replaced[4];    /* replaced drives map */
 188         u_int8_t        spare[4];       /* used spares map */
 189         u_int8_t        sparestat;      /* spare status */
 190 #define CISS_LD_CONF    0x01    /* spare configured */
 191 #define CISS_LD_RBLD    0x02    /* spare is used and rebuilding */
 192 #define CISS_LD_DONE    0x04    /* spare rebuild done */
 193 #define CISS_LD_FAIL    0x08    /* at least one spare drive has failed */
 194 #define CISS_LD_USED    0x10    /* at least one spare drive is used */
 195 #define CISS_LD_AVAIL   0x20    /* at least one spare is available */
 196         u_int8_t        sparemap[32];   /* spare->pd replacement map */
 197         u_int8_t        replok[4];      /* replaced failed map */
 198         u_int8_t        readyok;        /* ready to become ok */
 199         u_int8_t        memfail;        /* cache mem failure */
 200         u_int8_t        expfail;        /* expansion failure */
 201         u_int8_t        rebldfail;      /* rebuild failure */
 202 #define CISS_LD_RBLD_READ       0x01    /* read faild */
 203 #define CISS_LD_RBLD_WRITE      0x02    /* write fail */
 204         u_int8_t        bigfailed[16];  /* bigmap vers of same of the above */
 205         u_int8_t        bigremapcnt[256];
 206         u_int8_t        bigreplaced[16];
 207         u_int8_t        bigspare[16];
 208         u_int8_t        bigsparemap[128];
 209         u_int8_t        bigreplok[16];
 210         u_int8_t        bigrebuild;     /* big-number rebuilding driveno */
 211 } __packed;
 212
 213 struct ciss_pdid {
 214         u_int8_t        bus;
 215         u_int8_t        target;
 216         u_int16_t       blksz;
 217         u_int32_t       nblocks;
 218         u_int32_t       resblks;
 219         u_int8_t        model[40];
 220         u_int8_t        serial[40];
 221         u_int8_t        revision[8];
 222         u_int8_t        bits;
 223         u_int8_t        res0[2];
 224         u_int8_t        present;
 225 #define CISS_PD_PRESENT 0x01
 226 #define CISS_PD_NONDSK  0x02
 227 #define CISS_PD_WIDE    0x04
 228 #define CISS_PD_SYNC    0x08
 229 #define CISS_PD_NARROW  0x10
 230 #define CISS_PD_W2NARR  0x20    /* wide downgrade to narrow */
 231 #define CISS_PD_ULTRA   0x40
 232 #define CISS_PD_ULTRA2  0x80
 233         u_int8_t        config;
 234 #define CISS_PD_SMART   0x01
 235 #define CISS_PD_SMERRR  0x02
 236 #define CISS_PD_SMERRE  0x04
 237 #define CISS_PD_SMERRD  0x08
 238 #define CISS_PD_EXT     0x10
 239 #define CISS_PD_CONF    0x20
 240 #define CISS_PD_SPARE   0x40
 241 #define CISS_PD_CASAVE  0x80
 242         u_int8_t        res1;
 243         u_int8_t        cache;
 244 #define CISS_PD_CACHE   0x01
 245 #define CISS_PD_CASAFE  0x01
 246         u_int8_t        res2[5];
 247         u_int8_t        connector[2];
 248         u_int8_t        res3;
 249         u_int8_t        bay;
 250         u_int16_t       rpm;
 251         u_int8_t        type;
 252         u_int8_t        res4[393];
 253 } __packed;
 254
 255 struct ciss_event {
 256         u_int32_t       reltime;        /* time since controller boot */
 257         u_int16_t       event;
 258 #define CISS_EVCLS_PROTO        0
 259 #define CISS_EVCLS_PLUG         1
 260 #define CISS_EVCLS_HW           2
 261 #define CISS_EVCLS_ENV          3
 262 #define CISS_EVCLS_PD           4       /* ciss_evpdchg in details */
 263 #define CISS_EVCLS_LD           5
 264 #define CISS_EVCLS_CTRL         6
 265 #define CISS_EVCLS_CISS         8       /*  funky errors */
 266 #define CISS_EVCLS_RESV         9
 267         u_int16_t       subevent;
 268 #define CISS_EVPROTO_STAT       0
 269 #define CISS_EVPROTO_ERR        1
 270 #define CISS_EVPLUG_PDCHG       0       /* ciss_evpdchg */
 271 #define CISS_EVPLUG_POWER       1       /* ciss_evpschg */
 272 #define CISS_EVPLUG_FAN         2       /* ciss_evfanchg */
 273 #define CISS_EVPLUG_UPS         3       /* ciss_evupschg */
 274 #define CISS_EVPLUG_CTRL        4       /* ciss_evctrlchg: ctrl removed? (; */
 275 #define CISS_EVHW_CABLES        0
 276 #define CISS_EVHW_MEMORY        1
 277 #define CISS_EVHW_FAN           2       /* detail as in CISS_EVPLUG_FAN */
 278 #define CISS_EVHW_VRM           3
 279 #define CISS_EVENV_TEMP         0       /* ciss_evtempchg */
 280 #define CISS_EVENV_PS           1
 281 #define CISS_EVENV_CHASSIS      2
 282 #define CISS_EVENV_AC           3
 283 #define CISS_EVPD_STAT          0
 284 #define CISS_EVLD_STAT          0
 285 #define CISS_EVLD_ERR           1
 286 #define CISS_EVLD_CHECK         2       /* surface check */
 287 #define CISS_EVCTRL_STAT        0
 288         u_int16_t       detail;
 289 #define CISS_EVSTAT_NONE        0
 290 #define CISS_EVSTAT_DISABLE     1
 291 #define CISS_EVSTAT_TMO         2       /* async event poll timeout */
 292 #define CISS_EVERR_OVERFLOW     0       /* event queue overflow */
 293 #define CISS_EVPLUG_REMOVE      0
 294 #define CISS_EVPLUG_INSERT      1
 295 #define CISS_EVFAN_FAULT        0
 296 #define CISS_EVFAN_DEGRADED     1
 297 #define CISS_EVFAN_OK           2
 298 #define CISS_EVVRM_REMOVE       0
 299 #define CISS_EVVRM_INSERT       1
 300 #define CISS_EVVRM_FAILED       2
 301 #define CISS_EVVRM_OK           3
 302 #define CISS_EVTEMP_LIMEX       0       /* limit exceeded */
 303 #define CISS_EVTEMP_WARN        1
 304 #define CISS_EVTEMP_OK          2
 305 #define CISS_EVPS_FAIL          0
 306 #define CISS_EVPS_OK            2
 307 #define CISS_EVCHAS_OPEN        0
 308 #define CISS_EVCHAS_CLOSE       2
 309 #define CISS_EVAC_FAIL          0
 310 #define CISS_EVAC_BATTLOW       1
 311 #define CISS_EVPDSTAT_FAIL      0
 312 #define CISS_EVLDSTAT_CHG       0       /* ciss_evldchg */
 313 #define CISS_EVLDSTAT_EXMEDIA   1       /* untolerant cfg got drive replaced */
 314 #define CISS_EVLDSTAT_RERDERR   2       /* ciss_evldrblderr */
 315 #define CISS_EVLDSTAT_REWRERR   3       /* ciss_evldrblderr */
 316 #define CISS_EVLDERR_FATAL      0       /* ciss_evlderr */
 317 #define CISS_EVCHECK_DONE       0       /* details have onle 16bit ld num */
 318 #define CISS_EVCTRLSTAT_CHG     0       /* ciss_evctrlstat */
 319         u_int8_t        data[64];
 320         u_int8_t        msg[80];
 321         u_int32_t       tag;
 322         u_int16_t       monday;
 323         u_int16_t       year;
 324         u_int32_t       time;
 325         u_int16_t       presec;         /* time for events before boot */
 326         u_int8_t        device[8];
 327         u_int8_t        resv[336];
 328 } __packed;
 329
 330 struct ciss_evpdchg {   /* details pointer */
 331         u_int16_t       pd;
 332         u_int8_t        flag;           /* 1 for configured */
 333         u_int8_t        spare;
 334         u_int8_t        bigpd;          /* big number of the pd */
 335         u_int8_t        baynum;
 336 } __packed;
 337
 338 struct ciss_evpschg {   /* details pointer */
 339         u_int16_t       port;
 340         u_int16_t       psid;
 341         u_int16_t       box;
 342 } __packed;
 343
 344 struct ciss_evfanchg {  /* details pointer */
 345         u_int16_t       port;
 346         u_int16_t       fanid;
 347         u_int16_t       box;
 348 } __packed;
 349
 350 struct ciss_evupschg {  /* details pointer */
 351         u_int16_t       port;
 352         u_int16_t       upsid;
 353 } __packed;
 354
 355 struct ciss_evctrlchg { /* details pointer */
 356         u_int16_t       slot;
 357 } __packed;
 358
 359 struct ciss_evtempchg { /* details pointer */
 360         u_int16_t       port;
 361         u_int16_t       sensid;
 362         u_int16_t       box;
 363 } __packed;
 364
 365 struct ciss_evldchg {   /* details pointer */
 366         u_int16_t       ld;
 367         u_int8_t        prevstat;       /* same as ldstat->state */
 368         u_int8_t        newstat;        /* same as ldstat->state */
 369         u_int8_t        sparestat;
 370 } __packed;
 371
 372 struct ciss_evldrblderr { /* details pointer */
 373         u_int16_t       ld;
 374         u_int8_t        replace;
 375         u_int8_t        errpd;
 376         u_int8_t        bigreplace;
 377         u_int8_t        bigerrpd;
 378 } __packed;
 379
 380 struct ciss_evlderr {   /* details pointer */
 381         u_int16_t       ld;
 382         u_int16_t       blkno[2];       /* unaligned; if >2tb see big later */
 383         u_int16_t       count;
 384         u_int8_t        ldcmd;
 385         u_int8_t        bus;
 386         u_int8_t        target;
 387         u_int8_t        bigblkno[8];    /* unaligned */
 388 } __packed;
 389
 390 struct ciss_evctrlstat { /* details pointer */
 391         u_int8_t        prefctrl;
 392         u_int8_t        currmode;
 393         u_int8_t        redctrl;
 394         u_int8_t        redfail;
 395         u_int8_t        prevctrl;
 396         u_int8_t        prevmode;
 397         u_int8_t        prevred;
 398         u_int8_t        prevfail;
 399 } __packed;
 400
 401 struct ciss_cmd {
 402         u_int8_t        resv0;  /* 00 */
 403         u_int8_t        sgin;   /* 01: #sg in the cmd */
 404         u_int16_t       sglen;  /* 02: #sg total */
 405         u_int32_t       id;     /* 04: cmd id << 2 and status bits */
 406 #define CISS_CMD_ERR    0x02
 407         u_int32_t       id_hi;  /* 08: not used */
 408         u_int32_t       tgt;    /* 0c: tgt:bus:mode or lun:mode */
 409 #define CISS_CMD_MODE_PERIPH    0x00000000
 410 #define CISS_CMD_MODE_LD        0x40000000
 411 #define CISS_CMD_TGT_MASK       0x40ffffff
 412 #define CISS_CMD_BUS_MASK       0x3f000000
 413 #define CISS_CMD_BUS_SHIFT      24
 414         u_int32_t       tgt2;   /* 10: scsi-3 address bytes */
 415
 416         u_int8_t        cdblen; /* 14: valid length of cdb */
 417         u_int8_t        flags;  /* 15 */
 418 #define CISS_CDB_CMD    0x00
 419 #define CISS_CDB_MSG    0x01
 420 #define CISS_CDB_NOTAG  0x00
 421 #define CISS_CDB_SIMPL  0x20
 422 #define CISS_CDB_QHEAD  0x28
 423 #define CISS_CDB_ORDR   0x30
 424 #define CISS_CDB_AUTO   0x38
 425 #define CISS_CDB_IN     0x80
 426 #define CISS_CDB_OUT    0x40
 427         u_int16_t       tmo;    /* 16: timeout in seconds */
 428 #define CISS_MAX_CDB    16
 429         u_int8_t        cdb[16];/* 18 */
 430
 431         u_int64_t       err_pa; /* 28: pa(struct ciss_error *) */
 432         u_int32_t       err_len;/* 30 */
 433
 434         struct {                /* 34 */
 435                 u_int32_t       addr_lo;
 436                 u_int32_t       addr_hi;
 437                 u_int32_t       len;
 438                 u_int32_t       flags;
 439 #define CISS_SG_EXT     0x0001
 440         } sgl[1];
 441 } __packed;
 442
 443 struct ciss_error {
 444         u_int8_t        scsi_stat;      /* SCSI_OK etc */
 445         u_int8_t        senselen;
 446         u_int16_t       cmd_stat;
 447 #define CISS_ERR_OK     0
 448 #define CISS_ERR_TGTST  1       /* target status */
 449 #define CISS_ERR_UNRUN  2
 450 #define CISS_ERR_OVRUN  3
 451 #define CISS_ERR_INVCMD 4
 452 #define CISS_ERR_PROTE  5
 453 #define CISS_ERR_HWERR  6
 454 #define CISS_ERR_CLOSS  7
 455 #define CISS_ERR_ABRT   8
 456 #define CISS_ERR_FABRT  9
 457 #define CISS_ERR_UABRT  10
 458 #define CISS_ERR_TMO    11
 459 #define CISS_ERR_NABRT  12
 460         u_int32_t       resid;
 461         u_int8_t        err_type[4];
 462         u_int32_t       err_info;
 463         u_int8_t        sense[32];
 464 } __packed;
 465
 466 struct ciss_ccb {
 467         TAILQ_ENTRY(ciss_ccb)   ccb_link;
 468         struct ciss_softc       *ccb_sc;
 469         paddr_t                 ccb_cmdpa;
 470         enum {
 471                 CISS_CCB_FREE   = 0x01,
 472                 CISS_CCB_READY  = 0x02,
 473                 CISS_CCB_ONQ    = 0x04,
 474                 CISS_CCB_PREQ   = 0x08,
 475                 CISS_CCB_POLL   = 0x10,
 476                 CISS_CCB_FAIL   = 0x80
 477 #define CISS_CCB_BITS   "\020\01FREE\02READY\03ONQ\04PREQ\05POLL\010FAIL"
 478         } ccb_state;
 479
 480         struct scsipi_xfer      *ccb_xs;
 481         size_t                  ccb_len;
 482         void                    *ccb_data;
 483         bus_dmamap_t            ccb_dmamap;
 484
 485         struct ciss_error       ccb_err;
 486         struct ciss_cmd         ccb_cmd;        /* followed by sgl */
 487 };
 488
 489 typedef TAILQ_HEAD(ciss_queue_head, ciss_ccb)     ciss_queue_head;
 490