sys/dev/ic/dc21040reg.h

   1 /*      $NetBSD: dc21040reg.h,v 1.16.22.4 2005/03/04 16:41:27 skrll Exp $       */
   2
   3 /*-
   4  * Copyright (c) 1994, 1995, 1996 Matt Thomas <matt@3am-software.com>
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. The name of the author may not be used to endorse or promote products
  13  *    derived from this software without specific prior written permission
  14  *
  15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  16  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  17  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  18  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  19  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  20  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  21  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  22  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  23  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  24  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  25  *
  26  * Id: dc21040reg.h,v 1.24 1997/05/16 19:47:09 thomas Exp
  27  */
  28
  29 #if !defined(_DC21040_H)
  30 #define _DC21040_H
  31
  32 #if defined(BYTE_ORDER) && BYTE_ORDER == BIG_ENDIAN
  33 #define TULIP_BITFIELD2(a, b)                 b, a
  34 #define TULIP_BITFIELD3(a, b, c)           c, b, a
  35 #define TULIP_BITFIELD4(a, b, c, d)     d, c, b, a
  36 #else
  37 #define TULIP_BITFIELD2(a, b)           a, b
  38 #define TULIP_BITFIELD3(a, b, c)        a, b, c
  39 #define TULIP_BITFIELD4(a, b, c, d)     a, b, c, d
  40 #endif
  41
  42 typedef struct {
  43     u_int32_t d_status;
  44     u_int32_t TULIP_BITFIELD3(d_length1 : 11,
  45                               d_length2 : 11,
  46                               d_flag : 10);
  47     u_int32_t d_addr1;
  48     u_int32_t d_addr2;
  49 } tulip_desc_t;
  50
  51 #define TULIP_DSTS_OWNER        0x80000000      /* Owner (1 = 21040) */
  52 #define TULIP_DSTS_ERRSUM       0x00008000      /* Error Summary */
  53 /*
  54  * Transmit Status
  55  */
  56 #define TULIP_DSTS_TxBABBLE     0x00004000      /* Transmitter Babbled */
  57 #define TULIP_DSTS_TxCARRLOSS   0x00000800      /* Carrier Loss */
  58 #define TULIP_DSTS_TxNOCARR     0x00000400      /* No Carrier */
  59 #define TULIP_DSTS_TxLATECOLL   0x00000200      /* Late Collision */
  60 #define TULIP_DSTS_TxEXCCOLL    0x00000100      /* Excessive Collisions */
  61 #define TULIP_DSTS_TxNOHRTBT    0x00000080      /* No Heartbeat */
  62 #define TULIP_DSTS_TxCOLLMASK   0x00000078      /* Collision Count (mask) */
  63 #define TULIP_DSTS_V_TxCOLLCNT  0x00000003      /* Collision Count (bit) */
  64 #define TULIP_DSTS_TxLINKFAIL   0x00000004      /* Link Failure */
  65 #define TULIP_DSTS_TxUNDERFLOW  0x00000002      /* Underflow Error */
  66 #define TULIP_DSTS_TxDEFERRED   0x00000001      /* Initially Deferred */
  67 /*
  68  * Receive Status
  69  */
  70 #define TULIP_DSTS_RxBADLENGTH  0x00004000      /* Length Error */
  71 #define TULIP_DSTS_RxDATATYPE   0x00003000      /* Data Type */
  72 #define TULIP_DSTS_RxRUNT       0x00000800      /* Runt Frame */
  73 #define TULIP_DSTS_RxMULTICAST  0x00000400      /* Multicast Frame */
  74 #define TULIP_DSTS_RxFIRSTDESC  0x00000200      /* First Descriptor */
  75 #define TULIP_DSTS_RxLASTDESC   0x00000100      /* Last Descriptor */
  76 #define TULIP_DSTS_RxTOOLONG    0x00000080      /* Frame Too Long */
  77 #define TULIP_DSTS_RxCOLLSEEN   0x00000040      /* Collision Seen */
  78 #define TULIP_DSTS_RxFRAMETYPE  0x00000020      /* Frame Type */
  79 #define TULIP_DSTS_RxWATCHDOG   0x00000010      /* Receive Watchdog */
  80 #define TULIP_DSTS_RxDRBBLBIT   0x00000004      /* Dribble Bit */
  81 #define TULIP_DSTS_RxBADCRC     0x00000002      /* CRC Error */
  82 #define TULIP_DSTS_RxOVERFLOW   0x00000001      /* Overflow */
  83
  84
  85 #define TULIP_DFLAG_ENDRING     0x0008          /* End of Transmit Ring */
  86 #define TULIP_DFLAG_CHAIN       0x0004          /* Chain using d_addr2 */
  87
  88 #define TULIP_DFLAG_TxWANTINTR  0x0200          /* Signal Interrupt on Completion */
  89 #define TULIP_DFLAG_TxLASTSEG   0x0100          /* Last Segment */
  90 #define TULIP_DFLAG_TxFIRSTSEG  0x0080          /* First Segment */
  91 #define TULIP_DFLAG_TxINVRSFILT 0x0040          /* Inverse Filtering */
  92 #define TULIP_DFLAG_TxSETUPPKT  0x0020          /* Setup Packet */
  93 #define TULIP_DFLAG_TxHASCRC    0x0010          /* Don't Append the CRC */
  94 #define TULIP_DFLAG_TxNOPADDING 0x0002          /* Don't AutoPad */
  95 #define TULIP_DFLAG_TxHASHFILT  0x0001          /* Hash/Perfect Filtering */
  96
  97 /*
  98  * The 21040 Registers (IO Space Addresses)
  99  */
 100 #define TULIP_REG_BUSMODE       0x00    /* CSR0  -- Bus Mode */
 101 #define TULIP_REG_TXPOLL        0x08    /* CSR1  -- Transmit Poll Demand */
 102 #define TULIP_REG_RXPOLL        0x10    /* CSR2  -- Receive Poll Demand */
 103 #define TULIP_REG_RXLIST        0x18    /* CSR3  -- Receive List Base Addr */
 104 #define TULIP_REG_TXLIST        0x20    /* CSR4  -- Transmit List Base Addr */
 105 #define TULIP_REG_STATUS        0x28    /* CSR5  -- Status */
 106 #define TULIP_REG_CMD           0x30    /* CSR6  -- Command */
 107 #define TULIP_REG_INTR          0x38    /* CSR7  -- Interrupt Control */
 108 #define TULIP_REG_MISSES        0x40    /* CSR8  -- Missed Frame Counter */
 109 #define TULIP_REG_ADDRROM       0x48    /* CSR9  -- ENET ROM Register */
 110 #define TULIP_REG_RSRVD         0x50    /* CSR10 -- Reserved */
 111 #define TULIP_REG_FULL_DUPLEX   0x58    /* CSR11 -- Full Duplex */
 112 #define TULIP_REG_SIA_STATUS    0x60    /* CSR12 -- SIA Status */
 113 #define TULIP_REG_SIA_CONN      0x68    /* CSR13 -- SIA Connectivity */
 114 #define TULIP_REG_SIA_TXRX      0x70    /* CSR14 -- SIA Tx Rx */
 115 #define TULIP_REG_SIA_GEN       0x78    /* CSR15 -- SIA General */
 116
 117 /*
 118  * CSR5 -- Status Register
 119  * CSR7 -- Interrupt Control
 120  */
 121 #define TULIP_STS_ERRORMASK     0x03800000L             /* ( R)  Error Bits (Valid when SYSERROR is set) */
 122 #define TULIP_STS_ERR_PARITY    0x00000000L             /*        000 - Parity Error (Perform Reset) */
 123 #define TULIP_STS_ERR_MASTER    0x00800000L             /*        001 - Master Abort */
 124 #define TULIP_STS_ERR_TARGET    0x01000000L             /*        010 - Target Abort */
 125 #define TULIP_STS_ERR_SHIFT     23
 126 #define TULIP_STS_TXSTATEMASK   0x00700000L             /* ( R)  Transmission Process State */
 127 #define TULIP_STS_TXS_RESET     0x00000000L             /*        000 - Rset or transmit jabber expired */
 128 #define TULIP_STS_TXS_FETCH     0x00100000L             /*        001 - Fetching transmit descriptor */
 129 #define TULIP_STS_TXS_WAITEND   0x00200000L             /*        010 - Wait for end of transmission */
 130 #define TULIP_STS_TXS_READING   0x00300000L             /*        011 - Read buffer and enqueue data */
 131 #define TULIP_STS_TXS_RSRVD     0x00400000L             /*        100 - Reserved */
 132 #define TULIP_STS_TXS_SETUP     0x00500000L             /*        101 - Setup Packet */
 133 #define TULIP_STS_TXS_SUSPEND   0x00600000L             /*        110 - Transmit FIFO underflow or an
 134                                                                   unavailable transmit descriptor */
 135 #define TULIP_STS_TXS_CLOSE     0x00700000L             /*        111 - Close transmit descriptor */
 136 #define TULIP_STS_RXSTATEMASK   0x000E0000L             /* ( R)  Receive Process State*/
 137 #define TULIP_STS_RXS_STOPPED   0x00000000L             /*        000 - Stopped */
 138 #define TULIP_STS_RXS_FETCH     0x00020000L             /*        001 - Running -- Fetch receive descriptor */
 139 #define TULIP_STS_RXS_ENDCHECK  0x00040000L             /*        010 - Running -- Check for end of receive
 140                                                                   packet before prefetch of next descriptor */
 141 #define TULIP_STS_RXS_WAIT      0x00060000L             /*        011 - Running -- Wait for receive packet */
 142 #define TULIP_STS_RXS_SUSPEND   0x00080000L             /*        100 - Suspended -- As a result of
 143                                                                   unavailable receive buffers */
 144 #define TULIP_STS_RXS_CLOSE     0x000A0000L             /*        101 - Running -- Close receive descriptor */
 145 #define TULIP_STS_RXS_FLUSH     0x000C0000L             /*        110 - Running -- Flush the current frame
 146                                                                   from the receive FIFO as a result of
 147                                                                   an unavailable receive buffer */
 148 #define TULIP_STS_RXS_DEQUEUE   0x000E0000L             /*        111 - Running -- Dequeue the receive frame
 149                                                                   from the receive FIFO into the receive
 150                                                                   buffer. */
 151 #define TULIP_STS_NORMALINTR    0x00010000L             /* (RW)  Normal Interrupt */
 152 #define TULIP_STS_ABNRMLINTR    0x00008000L             /* (RW)  Abnormal Interrupt */
 153 #define TULIP_STS_SYSERROR      0x00002000L             /* (RW)  System Error */
 154 #define TULIP_STS_LINKFAIL      0x00001000L             /* (RW)  Link Failure (21040) */
 155 #define TULIP_STS_FULDPLXSHRT   0x00000800L             /* (RW)  Full Duplex Short Fram Rcvd (21040) */
 156 #define TULIP_STS_GPTIMEOUT     0x00000800L             /* (RW)  General Purpose Timeout (21140) */
 157 #define TULIP_STS_AUI           0x00000400L             /* (RW)  AUI/TP Switch (21040) */
 158 #define TULIP_STS_RXTIMEOUT     0x00000200L             /* (RW)  Receive Watchdog Timeout */
 159 #define TULIP_STS_RXSTOPPED     0x00000100L             /* (RW)  Receive Process Stopped */
 160 #define TULIP_STS_RXNOBUF       0x00000080L             /* (RW)  Receive Buffer Unavailable */
 161 #define TULIP_STS_RXINTR        0x00000040L             /* (RW)  Receive Interrupt */
 162 #define TULIP_STS_TXUNDERFLOW   0x00000020L             /* (RW)  Transmit Underflow */
 163 #define TULIP_STS_LINKPASS      0x00000010L             /* (RW)  LinkPass (21041) */
 164 #define TULIP_STS_TXBABBLE      0x00000008L             /* (RW)  Transmit Jabber Timeout */
 165 #define TULIP_STS_TXNOBUF       0x00000004L             /* (RW)  Transmit Buffer Unavailable */
 166 #define TULIP_STS_TXSTOPPED     0x00000002L             /* (RW)  Transmit Process Stopped */
 167 #define TULIP_STS_TXINTR        0x00000001L             /* (RW)  Transmit Interrupt */
 168
 169 /*
 170  * CSR6 -- Command (Operation Mode) Register
 171  */
 172 #define TULIP_CMD_MUSTBEONE     0x02000000L             /* (RW)  Must Be One (21140) */
 173 #define TULIP_CMD_SCRAMBLER     0x01000000L             /* (RW)  Scrambler Mode (21140) */
 174 #define TULIP_CMD_PCSFUNCTION   0x00800000L             /* (RW)  PCS Function (21140) */
 175 #define TULIP_CMD_TXTHRSHLDCTL  0x00400000L             /* (RW)  Transmit Threshold Mode (21140) */
 176 #define TULIP_CMD_STOREFWD      0x00200000L             /* (RW)  Store and Foward (21140) */
 177 #define TULIP_CMD_NOHEARTBEAT   0x00080000L             /* (RW)  No Heartbeat (21140) */
 178 #define TULIP_CMD_PORTSELECT    0x00040000L             /* (RW)  Post Select (100Mb) (21140) */
 179 #define TULIP_CMD_ENHCAPTEFFCT  0x00040000L             /* (RW)  Enhanced Capture Effect (21041) */
 180 #define TULIP_CMD_CAPTREFFCT    0x00020000L             /* (RW)  Capture Effect (!802.3) */
 181 #define TULIP_CMD_BACKPRESSURE  0x00010000L             /* (RW)  Back Pressure (!802.3) (21040) */
 182 #define TULIP_CMD_THRESHOLDCTL  0x0000C000L             /* (RW)  Threshold Control */
 183 #define TULIP_CMD_THRSHLD72     0x00000000L             /*       00 - 72 Bytes */
 184 #define TULIP_CMD_THRSHLD96     0x00004000L             /*       01 - 96 Bytes */
 185 #define TULIP_CMD_THRSHLD128    0x00008000L             /*       10 - 128 bytes */
 186 #define TULIP_CMD_THRSHLD160    0x0000C000L             /*       11 - 160 Bytes */
 187 #define TULIP_CMD_TXRUN         0x00002000L             /* (RW)  Start/Stop Transmitter */
 188 #define TULIP_CMD_FORCECOLL     0x00001000L             /* (RW)  Force Collisions */
 189 #define TULIP_CMD_OPERMODE      0x00000C00L             /* (RW)  Operating Mode */
 190 #define TULIP_CMD_FULLDUPLEX    0x00000200L             /* (RW)  Full Duplex Mode */
 191 #define TULIP_CMD_FLAKYOSCDIS   0x00000100L             /* (RW)  Flakey Oscillator Disable */
 192 #define TULIP_CMD_ALLMULTI      0x00000080L             /* (RW)  Pass All Multicasts */
 193 #define TULIP_CMD_PROMISCUOUS   0x00000040L             /* (RW)  Promiscuous Mode */
 194 #define TULIP_CMD_BACKOFFCTR    0x00000020L             /* (RW)  Start/Stop Backoff Counter (!802.3) */
 195 #define TULIP_CMD_INVFILTER     0x00000010L             /* (R )  Inverse Filtering */
 196 #define TULIP_CMD_PASSBADPKT    0x00000008L             /* (RW)  Pass Bad Frames  */
 197 #define TULIP_CMD_HASHONLYFLTR  0x00000004L             /* (R )  Hash Only Filtering */
 198 #define TULIP_CMD_RXRUN         0x00000002L             /* (RW)  Start/Stop Receive Filtering */
 199 #define TULIP_CMD_HASHPRFCTFLTR 0x00000001L             /* (R )  Hash/Perfect Receive Filtering */
 200
 201 #define TULIP_SIASTS_OTHERRXACTIVITY    0x00000200L
 202 #define TULIP_SIASTS_RXACTIVITY         0x00000100L
 203 #define TULIP_SIASTS_LINKFAIL           0x00000004L
 204 #define TULIP_SIASTS_LINK100FAIL        0x00000002L
 205 #define TULIP_SIACONN_RESET             0x00000000L
 206
 207 /*
 208  * 21040 SIA definitions
 209  */
 210 #define TULIP_21040_PROBE_10BASET_TIMEOUT       2500
 211 #define TULIP_21040_PROBE_AUIBNC_TIMEOUT        300
 212 #define TULIP_21040_PROBE_EXTSIA_TIMEOUT        300
 213
 214 #define TULIP_21040_SIACONN_10BASET     0x0000EF01L
 215 #define TULIP_21040_SIATXRX_10BASET     0x0000FFFFL
 216 #define TULIP_21040_SIAGEN_10BASET      0x00000000L
 217
 218 #define TULIP_21040_SIACONN_10BASET_FD  0x0000EF01L
 219 #define TULIP_21040_SIATXRX_10BASET_FD  0x0000FFFDL
 220 #define TULIP_21040_SIAGEN_10BASET_FD   0x00000000L
 221
 222 #define TULIP_21040_SIACONN_AUIBNC      0x0000EF09L
 223 #define TULIP_21040_SIATXRX_AUIBNC      0x00000705L
 224 #define TULIP_21040_SIAGEN_AUIBNC       0x00000006L
 225
 226 #define TULIP_21040_SIACONN_EXTSIA      0x00003041L
 227 #define TULIP_21040_SIATXRX_EXTSIA      0x00000000L
 228 #define TULIP_21040_SIAGEN_EXTSIA       0x00000006L
 229
 230 /*
 231  * 21041 SIA definitions
 232  */
 233
 234 #define TULIP_21041_PROBE_10BASET_TIMEOUT       2500
 235 #define TULIP_21041_PROBE_AUIBNC_TIMEOUT        300
 236
 237 #define TULIP_21041_SIACONN_10BASET             0x0000EF01L
 238 #define TULIP_21041_SIATXRX_10BASET             0x0000FF3FL
 239 #define TULIP_21041_SIAGEN_10BASET              0x00000000L
 240
 241 #define TULIP_21041P2_SIACONN_10BASET           0x0000EF01L
 242 #define TULIP_21041P2_SIATXRX_10BASET           0x0000FFFFL
 243 #define TULIP_21041P2_SIAGEN_10BASET            0x00000000L
 244
 245 #define TULIP_21041_SIACONN_10BASET_FD          0x0000EF01L
 246 #define TULIP_21041_SIATXRX_10BASET_FD          0x0000FF3DL
 247 #define TULIP_21041_SIAGEN_10BASET_FD           0x00000000L
 248
 249 #define TULIP_21041P2_SIACONN_10BASET_FD        0x0000EF01L
 250 #define TULIP_21041P2_SIATXRX_10BASET_FD        0x0000FFFFL
 251 #define TULIP_21041P2_SIAGEN_10BASET_FD         0x00000000L
 252
 253 #define TULIP_21041_SIACONN_AUI                 0x0000EF09L
 254 #define TULIP_21041_SIATXRX_AUI                 0x0000F73DL
 255 #define TULIP_21041_SIAGEN_AUI                  0x0000000EL
 256
 257 #define TULIP_21041P2_SIACONN_AUI               0x0000EF09L
 258 #define TULIP_21041P2_SIATXRX_AUI               0x0000F7FDL
 259 #define TULIP_21041P2_SIAGEN_AUI                0x0000000EL
 260
 261 #define TULIP_21041_SIACONN_BNC                 0x0000EF09L
 262 #define TULIP_21041_SIATXRX_BNC                 0x0000F73DL
 263 #define TULIP_21041_SIAGEN_BNC                  0x00000006L
 264
 265 #define TULIP_21041P2_SIACONN_BNC               0x0000EF09L
 266 #define TULIP_21041P2_SIATXRX_BNC               0x0000F7FDL
 267 #define TULIP_21041P2_SIAGEN_BNC                0x00000006L
 268
 269 /*
 270  * 21142 SIA definitions
 271  */
 272
 273 #define TULIP_21142_PROBE_10BASET_TIMEOUT       2500
 274 #define TULIP_21142_PROBE_AUIBNC_TIMEOUT        300
 275
 276 #define TULIP_21142_SIACONN_10BASET             0x00000001L
 277 #define TULIP_21142_SIATXRX_10BASET             0x00007F3FL
 278 #define TULIP_21142_SIAGEN_10BASET              0x00000008L
 279
 280 #define TULIP_21142_SIACONN_10BASET_FD          0x00000001L
 281 #define TULIP_21142_SIATXRX_10BASET_FD          0x00007F3DL
 282 #define TULIP_21142_SIAGEN_10BASET_FD           0x00000008L
 283
 284 #define TULIP_21142_SIACONN_AUI                 0x00000009L
 285 #define TULIP_21142_SIATXRX_AUI                 0x00000705L
 286 #define TULIP_21142_SIAGEN_AUI                  0x0000000EL
 287
 288 #define TULIP_21142_SIACONN_BNC                 0x00000009L
 289 #define TULIP_21142_SIATXRX_BNC                 0x00000705L
 290 #define TULIP_21142_SIAGEN_BNC                  0x00000006L
 291
 292
 293
 294
 295 #define TULIP_WATCHDOG_TXDISABLE        0x00000001L
 296 #define TULIP_WATCHDOG_RXDISABLE        0x00000010L
 297
 298 #define TULIP_BUSMODE_SWRESET           0x00000001L
 299 #define TULIP_BUSMODE_DESCSKIPLEN_MASK  0x0000007CL
 300 #define TULIP_BUSMODE_BIGENDIAN         0x00000080L
 301 #define TULIP_BUSMODE_BURSTLEN_MASK     0x00003F00L
 302 #define TULIP_BUSMODE_BURSTLEN_DEFAULT  0x00000000L
 303 #define TULIP_BUSMODE_BURSTLEN_1LW      0x00000100L
 304 #define TULIP_BUSMODE_BURSTLEN_2LW      0x00000200L
 305 #define TULIP_BUSMODE_BURSTLEN_4LW      0x00000400L
 306 #define TULIP_BUSMODE_BURSTLEN_8LW      0x00000800L
 307 #define TULIP_BUSMODE_BURSTLEN_16LW     0x00001000L
 308 #define TULIP_BUSMODE_BURSTLEN_32LW     0x00002000L
 309 #define TULIP_BUSMODE_CACHE_NOALIGN     0x00000000L
 310 #define TULIP_BUSMODE_CACHE_ALIGN8      0x00004000L
 311 #define TULIP_BUSMODE_CACHE_ALIGN16     0x00008000L
 312 #define TULIP_BUSMODE_CACHE_ALIGN32     0x0000C000L
 313 #define TULIP_BUSMODE_TXPOLL_NEVER      0x00000000L
 314 #define TULIP_BUSMODE_TXPOLL_200000ns   0x00020000L
 315 #define TULIP_BUSMODE_TXPOLL_800000ns   0x00040000L
 316 #define TULIP_BUSMODE_TXPOLL_1600000ns  0x00060000L
 317 #define TULIP_BUSMODE_TXPOLL_12800ns    0x00080000L     /* 21041 only */
 318 #define TULIP_BUSMODE_TXPOLL_25600ns    0x000A0000L     /* 21041 only */
 319 #define TULIP_BUSMODE_TXPOLL_51200ns    0x000C0000L     /* 21041 only */
 320 #define TULIP_BUSMODE_TXPOLL_102400ns   0x000E0000L     /* 21041 only */
 321 #define TULIP_BUSMODE_DESC_BIGENDIAN    0x00100000L     /* 21041 only */
 322 #define TULIP_BUSMODE_READMULTIPLE      0x00200000L     /* */
 323
 324 #define TULIP_REG_CFDA                  0x40
 325 #define TULIP_CFDA_SLEEP                0x80000000L
 326 #define TULIP_CFDA_SNOOZE               0x40000000L
 327
 328 #define TULIP_GP_PINSET                 0x00000100L
 329 /*
 330  * These are the definitions used for the DEC 21140
 331  * evaluation board.
 332  */
 333 #define TULIP_GP_EB_PINS                0x0000001F      /* General Purpose Pin directions */
 334 #define TULIP_GP_EB_OK10                0x00000080      /* 10 Mb/sec Signal Detect gep<7> */
 335 #define TULIP_GP_EB_OK100               0x00000040      /* 100 Mb/sec Signal Detect gep<6> */
 336 #define TULIP_GP_EB_INIT                0x0000000B      /* No loopback --- point-to-point */
 337
 338 /*
 339  * These are the definitions used for the SMC9332 (21140) board.
 340  */
 341 #define TULIP_GP_SMC_9332_PINS          0x0000003F      /* General Purpose Pin directions */
 342 #define TULIP_GP_SMC_9332_OK10          0x00000080      /* 10 Mb/sec Signal Detect gep<7> */
 343 #define TULIP_GP_SMC_9332_OK100         0x00000040      /* 100 Mb/sec Signal Detect gep<6> */
 344 #define TULIP_GP_SMC_9332_INIT          0x00000009      /* No loopback --- point-to-point */
 345
 346 #define TULIP_OUI_SMC_0                 0x00
 347 #define TULIP_OUI_SMC_1                 0x00
 348 #define TULIP_OUI_SMC_2                 0xC0
 349
 350 /*
 351  * There are the definitions used for the DEC DE500
 352  * 10/100 family of boards
 353  */
 354 #define TULIP_GP_DE500_PINS             0x0000001FL
 355 #define TULIP_GP_DE500_LINK_PASS        0x00000080L
 356 #define TULIP_GP_DE500_SYM_LINK         0x00000040L
 357 #define TULIP_GP_DE500_SIGNAL_DETECT    0x00000020L
 358 #define TULIP_GP_DE500_PHY_RESET        0x00000010L
 359 #define TULIP_GP_DE500_HALFDUPLEX       0x00000008L
 360 #define TULIP_GP_DE500_PHY_LOOPBACK     0x00000004L
 361 #define TULIP_GP_DE500_FORCE_LED        0x00000002L
 362 #define TULIP_GP_DE500_FORCE_100        0x00000001L
 363
 364 /*
 365  * These are the definitions used for the Cogent EM100
 366  * 21140 board.
 367  */
 368 #define TULIP_GP_EM100_PINS             0x0000003F      /* General Purpose Pin directions */
 369 #define TULIP_GP_EM100_INIT             0x00000009      /* No loopback --- point-to-point */
 370 #define TULIP_OUI_COGENT_0              0x00
 371 #define TULIP_OUI_COGENT_1              0x00
 372 #define TULIP_OUI_COGENT_2              0x92
 373 #define TULIP_COGENT_EM100TX_ID         0x12
 374 #define TULIP_COGENT_EM100FX_ID         0x15
 375
 376
 377 /*
 378  * These are the definitions used for the Znyx ZX342
 379  * 10/100 board
 380  */
 381 #define TULIP_OUI_ZNYX_0                0x00
 382 #define TULIP_OUI_ZNYX_1                0xC0
 383 #define TULIP_OUI_ZNYX_2                0x95
 384
 385 #define TULIP_ZNYX_ID_ZX312             0x0602
 386 #define TULIP_ZNYX_ID_ZX312T            0x0622
 387 #define TULIP_ZNYX_ID_ZX314_INTA        0x0701
 388 #define TULIP_ZNYX_ID_ZX314             0x0711
 389 #define TULIP_ZNYX_ID_ZX315_INTA        0x0801
 390 #define TULIP_ZNYX_ID_ZX315             0x0811
 391 #define TULIP_ZNYX_ID_ZX342             0x0901
 392 #define TULIP_ZNYX_ID_ZX342B            0x0921
 393 #define TULIP_ZNYX_ID_ZX342_X3          0x0902
 394 #define TULIP_ZNYX_ID_ZX342_X4          0x0903
 395 #define TULIP_ZNYX_ID_ZX344             0x0A01
 396 #define TULIP_ZNYX_ID_ZX351             0x0B01
 397 #define TULIP_ZNYX_ID_ZX345             0x0C01
 398 #define TULIP_ZNYX_ID_ZX311             0x0D01
 399 #define TULIP_ZNYX_ID_ZX346             0x0E01
 400
 401 #define TULIP_GP_ZX34X_PINS             0x0000001F      /* General Purpose Pin directions */
 402 #define TULIP_GP_ZX344_PINS             0x0000000B      /* General Purpose Pin directions */
 403 #define TULIP_GP_ZX345_PINS             0x00000003      /* General Purpose Pin directions */
 404 #define TULIP_GP_ZX346_PINS             0x00000043      /* General Purpose Pin directions */
 405 #define TULIP_GP_ZX34X_LNKFAIL          0x00000080      /* 10Mb/s Link Failure */
 406 #define TULIP_GP_ZX34X_SYMDET           0x00000040      /* 100Mb/s Symbol Detect */
 407 #define TULIP_GP_ZX345_PHYACT           0x00000040      /* PHY Activity */
 408 #define TULIP_GP_ZX34X_SIGDET           0x00000020      /* 100Mb/s Signal Detect */
 409 #define TULIP_GP_ZX346_AUTONEG_ENABLED  0x00000020      /* 802.3u autoneg enabled */
 410 #define TULIP_GP_ZX342_COLENA           0x00000008      /* 10t Ext LB */
 411 #define TULIP_GP_ZX344_ROTINT           0x00000008      /* PPB IRQ rotation */
 412 #define TULIP_GP_ZX345_SPEED10          0x00000008      /* 10Mb speed detect */
 413 #define TULIP_GP_ZX346_SPEED100         0x00000008      /* 100Mb speed detect */
 414 #define TULIP_GP_ZX34X_NCOLENA          0x00000004      /* 10t Int LB */
 415 #define TULIP_GP_ZX34X_RXMATCH          0x00000004      /* RX Match */
 416 #define TULIP_GP_ZX346_FULLDUPLEX       0x00000004      /* Full Duplex Sensed */
 417 #define TULIP_GP_ZX34X_LB102            0x00000002      /* 100tx twister LB */
 418 #define TULIP_GP_ZX34X_NLB101           0x00000001      /* PDT/PDR LB */
 419 #define TULIP_GP_ZX34X_INIT             0x00000009
 420
 421 /*
 422  * Compex's OUI.  We need to twiddle a bit on their 21041 card.
 423  */
 424 #define TULIP_OUI_COMPEX_0              0x00
 425 #define TULIP_OUI_COMPEX_1              0x80
 426 #define TULIP_OUI_COMPEX_2              0x48
 427 #define TULIP_21041_COMPEX_XREGDATA     1
 428
 429 /*
 430  * Asante's OUI and stuff...
 431  */
 432 #define TULIP_OUI_ASANTE_0              0x00
 433 #define TULIP_OUI_ASANTE_1              0x00
 434 #define TULIP_OUI_ASANTE_2              0x94
 435 #define TULIP_GP_ASANTE_PINS            0x000000bf      /* GP pin config */
 436 #define TULIP_GP_ASANTE_PHYRESET        0x00000008      /* Reset PHY */
 437
 438 /*
 439  * ACCTON EN1207 specialties
 440  */
 441
 442 #define TULIP_OUI_EN1207_0              0x00
 443 #define TULIP_OUI_EN1207_1              0x00
 444 #define TULIP_OUI_EN1207_2              0xE8
 445
 446 #define TULIP_CSR8_EN1207               0x08
 447 #define TULIP_CSR9_EN1207               0x00
 448 #define TULIP_CSR10_EN1207              0x03
 449 #define TULIP_CSR11_EN1207              0x1F
 450
 451 #define TULIP_GP_EN1207_BNC_INIT        0x0000011B
 452 #define TULIP_GP_EN1207_UTP_INIT        0x9E00000B
 453 #define TULIP_GP_EN1207_100_INIT        0x6D00031B
 454
 455 /*
 456  * SROM definitions for the 21140 and 21041.
 457  */
 458 #define SROMXREG        0x0400
 459 #define SROMSEL         0x0800
 460 #define SROMRD          0x4000
 461 #define SROMWR          0x2000
 462 #define SROMDIN         0x0008
 463 #define SROMDOUT        0x0004
 464 #define SROMDOUTON      0x0004
 465 #define SROMDOUTOFF     0x0004
 466 #define SROMCLKON       0x0002
 467 #define SROMCLKOFF      0x0002
 468 #define SROMCSON        0x0001
 469 #define SROMCSOFF       0x0001
 470 #define SROMCS          0x0001
 471
 472 #define SROMCMD_MODE    4
 473 #define SROMCMD_WR      5
 474 #define SROMCMD_RD      6
 475
 476 #define SROM_BITWIDTH   6
 477
 478 /*
 479  * MII Definitions for the 21041 and 21140/21140A/21142
 480  */
 481 #define MII_PREAMBLE            (~0)
 482 #define MII_TEST                0xAAAAAAAA
 483 #define MII_RDCMD               0xF6            /* 1111.0110 */
 484 #define MII_WRCMD               0xF5            /* 1111.0101 */
 485 #define MII_DIN                 0x00080000
 486 #define MII_RD                  0x00040000
 487 #define MII_WR                  0x00000000
 488 #define MII_DOUT                0x00020000
 489 #define MII_CLK                 0x00010000
 490 #define MII_CLKON               MII_CLK
 491 #define MII_CLKOFF              MII_CLK
 492
 493 #define PHYREG_CONTROL                  0
 494 #define PHYREG_STATUS                   1
 495 #define PHYREG_IDLOW                    2
 496 #define PHYREG_IDHIGH                   3
 497 #define PHYREG_AUTONEG_ADVERTISEMENT    4
 498 #define PHYREG_AUTONEG_ABILITIES        5
 499 #define PHYREG_AUTONEG_EXPANSION        6
 500 #define PHYREG_AUTONEG_NEXTPAGE         7
 501
 502 #define PHYSTS_100BASET4        0x8000
 503 #define PHYSTS_100BASETX_FD     0x4000
 504 #define PHYSTS_100BASETX        0x2000
 505 #define PHYSTS_10BASET_FD       0x1000
 506 #define PHYSTS_10BASET          0x0800
 507 #define PHYSTS_AUTONEG_DONE     0x0020
 508 #define PHYSTS_REMOTE_FAULT     0x0010
 509 #define PHYSTS_CAN_AUTONEG      0x0008
 510 #define PHYSTS_LINK_UP          0x0004
 511 #define PHYSTS_JABBER_DETECT    0x0002
 512 #define PHYSTS_EXTENDED_REGS    0x0001
 513
 514 #define PHYCTL_RESET            0x8000
 515 #define PHYCTL_SELECT_100MB     0x2000
 516 #define PHYCTL_AUTONEG_ENABLE   0x1000
 517 #define PHYCTL_ISOLATE          0x0400
 518 #define PHYCTL_AUTONEG_RESTART  0x0200
 519 #define PHYCTL_FULL_DUPLEX      0x0100
 520
 521 /*
 522  * Definitions for the DE425.
 523  */
 524 #define DE425_CFID              0x08    /* Configuration Id */
 525 #define DE425_CFCS              0x0C    /* Configuration Command-Status */
 526 #define DE425_CFRV              0x18    /* Configuration Revision */
 527 #define DE425_CFLT              0x1C    /* Configuration Latency Timer */
 528 #define DE425_CBIO              0x28    /* Configuration Base IO Address */
 529 #define DE425_CFDA              0x2C    /* Configuration Driver Area */
 530 #define DE425_ENETROM_OFFSET    0xC90   /* Offset in I/O space for ENETROM */
 531 #define DE425_CFG0              0xC88   /* IRQ register */
 532 #define DE425_EISAID            0x10a34250 /* EISA device id */
 533 #define DE425_EISA_IOSIZE       0x100
 534
 535 #define DEC_VENDORID            0x1011
 536 #define CHIPID_21040            0x0002
 537 #define CHIPID_21140            0x0009
 538 #define CHIPID_21041            0x0014
 539 #define CHIPID_21142            0x0019
 540 #define PCI_VENDORID(x)         ((x) & 0xFFFF)
 541 #define PCI_CHIPID(x)           (((x) >> 16) & 0xFFFF)
 542
 543 /*
 544  * Generic SROM Format
 545  *
 546  *
 547  */
 548
 549 typedef struct {
 550     u_int8_t sh_idbuf[18];
 551     u_int8_t sh_version;
 552     u_int8_t sh_adapter_count;
 553     u_int8_t sh_ieee802_address[6];
 554 } tulip_srom_header_t;
 555
 556 typedef struct {
 557     u_int8_t sai_device;
 558     u_int8_t sai_leaf_offset_lowbyte;
 559     u_int8_t sai_leaf_offset_highbyte;
 560 } tulip_srom_adapter_info_t;
 561
 562 typedef enum {
 563     TULIP_SROM_CONNTYPE_10BASET                 =0x0000,
 564     TULIP_SROM_CONNTYPE_BNC                     =0x0001,
 565     TULIP_SROM_CONNTYPE_AUI                     =0x0002,
 566     TULIP_SROM_CONNTYPE_100BASETX               =0x0003,
 567     TULIP_SROM_CONNTYPE_100BASET4               =0x0006,
 568     TULIP_SROM_CONNTYPE_100BASEFX               =0x0007,
 569     TULIP_SROM_CONNTYPE_MII_10BASET             =0x0009,
 570     TULIP_SROM_CONNTYPE_MII_100BASETX           =0x000D,
 571     TULIP_SROM_CONNTYPE_MII_100BASET4           =0x000F,
 572     TULIP_SROM_CONNTYPE_MII_100BASEFX           =0x0010,
 573     TULIP_SROM_CONNTYPE_10BASET_NWAY            =0x0100,
 574     TULIP_SROM_CONNTYPE_10BASET_FD              =0x0204,
 575     TULIP_SROM_CONNTYPE_MII_10BASET_FD          =0x020A,
 576     TULIP_SROM_CONNTYPE_100BASETX_FD            =0x020E,
 577     TULIP_SROM_CONNTYPE_MII_100BASETX_FD        =0x0211,
 578     TULIP_SROM_CONNTYPE_10BASET_NOLINKPASS      =0x0400,
 579     TULIP_SROM_CONNTYPE_AUTOSENSE               =0x0800,
 580     TULIP_SROM_CONNTYPE_AUTOSENSE_POWERUP       =0x8800,
 581     TULIP_SROM_CONNTYPE_AUTOSENSE_NWAY          =0x9000,
 582     TULIP_SROM_CONNTYPE_NOT_USED                =0xFFFF
 583 } tulip_srom_connection_t;
 584
 585 typedef enum {
 586     TULIP_SROM_MEDIA_10BASET                    =0x0000,
 587     TULIP_SROM_MEDIA_BNC                        =0x0001,
 588     TULIP_SROM_MEDIA_AUI                        =0x0002,
 589     TULIP_SROM_MEDIA_100BASETX                  =0x0003,
 590     TULIP_SROM_MEDIA_10BASET_FD                 =0x0004,
 591     TULIP_SROM_MEDIA_100BASETX_FD               =0x0005,
 592     TULIP_SROM_MEDIA_100BASET4                  =0x0006,
 593     TULIP_SROM_MEDIA_100BASEFX                  =0x0007,
 594     TULIP_SROM_MEDIA_100BASEFX_FD               =0x0008
 595 } tulip_srom_media_t;
 596
 597 #define TULIP_SROM_21041_EXTENDED       0x40
 598
 599 #define TULIP_SROM_2114X_NOINDICATOR    0x8000
 600 #define TULIP_SROM_2114X_DEFAULT        0x4000
 601 #define TULIP_SROM_2114X_POLARITY       0x0080
 602 #define TULIP_SROM_2114X_CMDBITS(n)     (((n) & 0x0071) << 18)
 603 #define TULIP_SROM_2114X_BITPOS(b)      (1 << (((b) & 0x0E) >> 1))
 604
 605
 606
 607 #endif /* !defined(_DC21040_H) */