1 /* $NetBSD: i82365.c,v 1.110 2009/09/14 13:41:15 tsutsui Exp $ */
4 * Copyright (c) 2004 Charles M. Hannum. All rights reserved.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by Charles M. Hannum.
17 * 4. The name of the author may not be used to endorse or promote products
18 * derived from this software without specific prior written permission.
22 * Copyright (c) 2000 Christian E. Hopps. All rights reserved.
23 * Copyright (c) 1997 Marc Horowitz. All rights reserved.
25 * Redistribution and use in source and binary forms, with or without
26 * modification, are permitted provided that the following conditions
28 * 1. Redistributions of source code must retain the above copyright
29 * notice, this list of conditions and the following disclaimer.
30 * 2. Redistributions in binary form must reproduce the above copyright
31 * notice, this list of conditions and the following disclaimer in the
32 * documentation and/or other materials provided with the distribution.
33 * 3. All advertising materials mentioning features or use of this software
34 * must display the following acknowledgement:
35 * This product includes software developed by Marc Horowitz.
36 * 4. The name of the author may not be used to endorse or promote products
37 * derived from this software without specific prior written permission.
39 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
40 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
41 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
42 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
43 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
44 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
45 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
46 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
47 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
48 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
51 #include <sys/cdefs.h>
52 __KERNEL_RCSID(0, "$NetBSD: i82365.c,v 1.110 2009/09/14 13:41:15 tsutsui Exp $");
56 #include <sys/param.h>
57 #include <sys/systm.h>
58 #include <sys/device.h>
59 #include <sys/extent.h>
60 #include <sys/kernel.h>
61 #include <sys/malloc.h>
62 #include <sys/kthread.h>
67 #include <dev/pcmcia/pcmciareg.h>
68 #include <dev/pcmcia/pcmciavar.h>
70 #include <dev/ic/i82365reg.h>
71 #include <dev/ic/i82365var.h>
77 #define DPRINTF(arg) if (pcic_debug) printf arg;
83 * Individual drivers will allocate their own memory and io regions. Memory
84 * regions must be a multiple of 4k, aligned on a 4k boundary.
87 #define PCIC_MEM_ALIGN PCIC_MEM_PAGESIZE
89 void pcic_attach_socket(struct pcic_handle
*);
90 void pcic_attach_socket_finish(struct pcic_handle
*);
92 int pcic_print (void *arg
, const char *pnp
);
93 int pcic_intr_socket(struct pcic_handle
*);
94 void pcic_poll_intr(void *);
96 void pcic_attach_card(struct pcic_handle
*);
97 void pcic_detach_card(struct pcic_handle
*, int);
98 void pcic_deactivate_card(struct pcic_handle
*);
100 void pcic_chip_do_mem_map(struct pcic_handle
*, int);
101 void pcic_chip_do_io_map(struct pcic_handle
*, int);
103 void pcic_event_thread(void *);
105 void pcic_queue_event(struct pcic_handle
*, int);
106 void pcic_power(int, void *);
108 static int pcic_wait_ready(struct pcic_handle
*);
109 static void pcic_delay(struct pcic_handle
*, int, const char *);
111 static uint8_t st_pcic_read(struct pcic_handle
*, int);
112 static void st_pcic_write(struct pcic_handle
*, int, uint8_t);
115 pcic_ident_ok(int ident
)
118 /* this is very empirical and heuristic */
120 if ((ident
== 0) || (ident
== 0xff) || (ident
& PCIC_IDENT_ZERO
))
123 if ((ident
& PCIC_IDENT_REV_MASK
) == 0)
126 if ((ident
& PCIC_IDENT_IFTYPE_MASK
) != PCIC_IDENT_IFTYPE_MEM_AND_IO
) {
128 printf("pcic: does not support memory and I/O cards, "
129 "ignored (ident=%0x)\n", ident
);
138 pcic_vendor(struct pcic_handle
*h
)
143 reg
= pcic_read(h
, PCIC_IDENT
);
145 if ((reg
& PCIC_IDENT_REV_MASK
) == 0)
146 return PCIC_VENDOR_NONE
;
151 return PCIC_VENDOR_NONE
;
152 case PCIC_IDENT_ID_INTEL0
:
153 vendor
= PCIC_VENDOR_I82365SLR0
;
155 case PCIC_IDENT_ID_INTEL1
:
156 vendor
= PCIC_VENDOR_I82365SLR1
;
158 case PCIC_IDENT_ID_INTEL2
:
159 vendor
= PCIC_VENDOR_I82365SL_DF
;
161 case PCIC_IDENT_ID_IBM1
:
162 case PCIC_IDENT_ID_IBM2
:
163 vendor
= PCIC_VENDOR_IBM
;
165 case PCIC_IDENT_ID_IBM3
:
166 vendor
= PCIC_VENDOR_IBM_KING
;
169 vendor
= PCIC_VENDOR_UNKNOWN
;
173 if (vendor
== PCIC_VENDOR_I82365SLR0
||
174 vendor
== PCIC_VENDOR_I82365SLR1
) {
176 * Check for Cirrus PD67xx.
177 * the chip_id of the cirrus toggles between 11 and 00 after a
180 pcic_write(h
, PCIC_CIRRUS_CHIP_INFO
, 0);
181 reg
= pcic_read(h
, -1);
182 if ((reg
& PCIC_CIRRUS_CHIP_INFO_CHIP_ID
) ==
183 PCIC_CIRRUS_CHIP_INFO_CHIP_ID
) {
184 reg
= pcic_read(h
, -1);
185 if ((reg
& PCIC_CIRRUS_CHIP_INFO_CHIP_ID
) == 0)
186 return PCIC_VENDOR_CIRRUS_PD67XX
;
190 * check for Ricoh RF5C[23]96
192 reg
= pcic_read(h
, PCIC_RICOH_REG_CHIP_ID
);
194 case PCIC_RICOH_CHIP_ID_5C296
:
195 return PCIC_VENDOR_RICOH_5C296
;
196 case PCIC_RICOH_CHIP_ID_5C396
:
197 return PCIC_VENDOR_RICOH_5C396
;
205 pcic_vendor_to_string(int vendor
)
209 case PCIC_VENDOR_I82365SLR0
:
210 return "Intel 82365SL Revision 0";
211 case PCIC_VENDOR_I82365SLR1
:
212 return "Intel 82365SL Revision 1";
213 case PCIC_VENDOR_CIRRUS_PD67XX
:
214 return "Cirrus PD6710/2X";
215 case PCIC_VENDOR_I82365SL_DF
:
216 return "Intel 82365SL-DF";
217 case PCIC_VENDOR_RICOH_5C296
:
218 return "Ricoh RF5C296";
219 case PCIC_VENDOR_RICOH_5C396
:
220 return "Ricoh RF5C396";
221 case PCIC_VENDOR_IBM
:
223 case PCIC_VENDOR_IBM_KING
:
227 return "Unknown controller";
231 pcic_attach(struct pcic_softc
*sc
)
233 int i
, reg
, chip
, socket
;
234 struct pcic_handle
*h
;
237 DPRINTF(("pcic ident regs:"));
240 mutex_init(&sc
->sc_pcic_lock
, MUTEX_DEFAULT
, IPL_NONE
);
242 /* find and configure for the available sockets */
243 for (i
= 0; i
< __arraycount(sc
->handle
); i
++) {
251 h
->sock
= chip
* PCIC_CHIP_OFFSET
+ socket
* PCIC_SOCKET_OFFSET
;
252 h
->laststate
= PCIC_LASTSTATE_EMPTY
;
253 /* initialize pcic_read and pcic_write functions */
254 h
->ph_read
= st_pcic_read
;
255 h
->ph_write
= st_pcic_write
;
256 h
->ph_bus_t
= sc
->iot
;
257 h
->ph_bus_h
= sc
->ioh
;
260 /* need to read vendor -- for cirrus to report no xtra chip */
262 h
->vendor
= pcic_vendor(h
);
263 if (i
< __arraycount(sc
->handle
) - 1)
264 (h
+ 1)->vendor
= h
->vendor
;
268 case PCIC_VENDOR_NONE
:
271 case PCIC_VENDOR_CIRRUS_PD67XX
:
272 reg
= pcic_read(h
, PCIC_CIRRUS_CHIP_INFO
);
274 (reg
& PCIC_CIRRUS_CHIP_INFO_SLOTS
))
275 h
->flags
= PCIC_FLAG_SOCKETP
;
279 * During the socket probe, read the ident register
280 * twice. I don't understand why, but sometimes the
281 * clone chips in hpcmips boxes read all-0s the first
284 reg
= pcic_read(h
, PCIC_IDENT
);
285 DPRINTF(("socket %d ident reg 0x%02x\n", i
, reg
));
286 reg
= pcic_read(h
, PCIC_IDENT
);
287 DPRINTF(("socket %d ident reg 0x%02x\n", i
, reg
));
288 if (pcic_ident_ok(reg
))
289 h
->flags
= PCIC_FLAG_SOCKETP
;
294 for (i
= 0; i
< __arraycount(sc
->handle
); i
++) {
297 if (h
->flags
& PCIC_FLAG_SOCKETP
) {
298 SIMPLEQ_INIT(&h
->events
);
300 /* disable interrupts and leave socket in reset */
301 pcic_write(h
, PCIC_INTR
, 0);
303 /* zero out the address windows */
304 pcic_write(h
, PCIC_ADDRWIN_ENABLE
, 0);
306 /* power down the socket */
307 pcic_write(h
, PCIC_PWRCTL
, 0);
309 pcic_write(h
, PCIC_CSC_INTR
, 0);
310 (void) pcic_read(h
, PCIC_CSC
);
314 /* print detected info */
315 for (i
= 0; i
< __arraycount(sc
->handle
) - 1; i
+= 2) {
319 if (h
->vendor
== PCIC_VENDOR_NONE
)
322 aprint_normal_dev(self
, "controller %d (%s) has ",
323 chip
, pcic_vendor_to_string(sc
->handle
[i
].vendor
));
325 if ((h
->flags
& PCIC_FLAG_SOCKETP
) &&
326 ((h
+ 1)->flags
& PCIC_FLAG_SOCKETP
))
327 aprint_normal("sockets A and B\n");
328 else if (h
->flags
& PCIC_FLAG_SOCKETP
)
329 aprint_normal("socket A only\n");
330 else if ((h
+ 1)->flags
& PCIC_FLAG_SOCKETP
)
331 aprint_normal("socket B only\n");
333 aprint_normal("no sockets\n");
338 * attach the sockets before we know what interrupts we have
341 pcic_attach_sockets(struct pcic_softc
*sc
)
345 for (i
= 0; i
< __arraycount(sc
->handle
); i
++)
346 if (sc
->handle
[i
].flags
& PCIC_FLAG_SOCKETP
)
347 pcic_attach_socket(&sc
->handle
[i
]);
351 pcic_power(int why
, void *arg
)
353 struct pcic_handle
*h
= arg
;
354 struct pcic_softc
*sc
= device_private(h
->ph_parent
);
357 DPRINTF(("%s: power: why %d\n", device_xname(h
->ph_parent
), why
));
359 if (h
->flags
& PCIC_FLAG_SOCKETP
) {
360 if ((why
== PWR_RESUME
) &&
361 (pcic_read(h
, PCIC_CSC_INTR
) == 0)) {
365 reg
= PCIC_CSC_INTR_CD_ENABLE
;
367 reg
|= sc
->irq
<< PCIC_CSC_INTR_IRQ_SHIFT
;
368 pcic_write(h
, PCIC_CSC_INTR
, reg
);
370 snprintb(bitbuf
, sizeof(bitbuf
), PCIC_CSC_INTR_FORMAT
,
371 pcic_read(h
, PCIC_CSC_INTR
));
373 DPRINTF(("%s: CSC_INTR was zero; reset to %s\n",
374 device_xname(&sc
->dev
), bitbuf
));
378 * check for card insertion or removal during suspend period.
379 * XXX: the code can't cope with card swap (remove then insert).
380 * how can we detect such situation?
382 if (why
== PWR_RESUME
)
383 (void)pcic_intr_socket(h
);
389 * attach a socket -- we don't know about irqs yet
392 pcic_attach_socket(struct pcic_handle
*h
)
394 struct pcmciabus_attach_args paa
;
395 struct pcic_softc
*sc
= device_private(h
->ph_parent
);
396 int locs
[PCMCIABUSCF_NLOCS
];
398 /* initialize the rest of the handle */
405 /* now, config one pcmcia device per socket */
407 paa
.paa_busname
= "pcmcia";
408 paa
.pct
= (pcmcia_chipset_tag_t
) sc
->pct
;
409 paa
.pch
= (pcmcia_chipset_handle_t
) h
;
410 paa
.iobase
= sc
->iobase
;
411 paa
.iosize
= sc
->iosize
;
413 locs
[PCMCIABUSCF_CONTROLLER
] = h
->chip
;
414 locs
[PCMCIABUSCF_SOCKET
] = h
->socket
;
416 h
->pcmcia
= config_found_sm_loc(&sc
->dev
, "pcmciabus", locs
, &paa
,
417 pcic_print
, config_stdsubmatch
);
418 if (h
->pcmcia
== NULL
) {
419 h
->flags
&= ~PCIC_FLAG_SOCKETP
;
426 * now finish attaching the sockets, we are ready to allocate
430 pcic_attach_sockets_finish(struct pcic_softc
*sc
)
434 for (i
= 0; i
< __arraycount(sc
->handle
); i
++)
435 if (sc
->handle
[i
].flags
& PCIC_FLAG_SOCKETP
)
436 pcic_attach_socket_finish(&sc
->handle
[i
]);
440 * finishing attaching the socket. Interrupts may now be on
441 * if so expects the pcic interrupt to be blocked
444 pcic_attach_socket_finish(struct pcic_handle
*h
)
446 struct pcic_softc
*sc
= device_private(h
->ph_parent
);
450 DPRINTF(("%s: attach finish socket %ld\n", device_xname(h
->ph_parent
),
451 (long) (h
- &sc
->handle
[0])));
454 * Set up a powerhook to ensure it continues to interrupt on
455 * card detect even after suspend.
456 * (this works around a bug seen in suspend-to-disk on the
457 * Sony VAIO Z505; on resume, the CSC_INTR state is not preserved).
459 powerhook_establish(device_xname(h
->ph_parent
), pcic_power
, h
);
461 /* enable interrupts on card detect, poll for them if no irq avail */
462 reg
= PCIC_CSC_INTR_CD_ENABLE
;
464 if (sc
->poll_established
== 0) {
465 callout_init(&sc
->poll_ch
, 0);
466 callout_reset(&sc
->poll_ch
, hz
/ 2, pcic_poll_intr
, sc
);
467 sc
->poll_established
= 1;
470 reg
|= sc
->irq
<< PCIC_CSC_INTR_IRQ_SHIFT
;
471 pcic_write(h
, PCIC_CSC_INTR
, reg
);
473 /* steer above mgmt interrupt to configured place */
475 pcic_write(h
, PCIC_INTR
, PCIC_INTR_ENABLE
);
477 /* clear possible card detect interrupt */
478 (void) pcic_read(h
, PCIC_CSC
);
480 DPRINTF(("%s: attach finish vendor 0x%02x\n",
481 device_xname(h
->ph_parent
), h
->vendor
));
483 /* unsleep the cirrus controller */
484 if (h
->vendor
== PCIC_VENDOR_CIRRUS_PD67XX
) {
485 reg
= pcic_read(h
, PCIC_CIRRUS_MISC_CTL_2
);
486 if (reg
& PCIC_CIRRUS_MISC_CTL_2_SUSPEND
) {
487 DPRINTF(("%s: socket %02x was suspended\n",
488 device_xname(h
->ph_parent
), h
->sock
));
489 reg
&= ~PCIC_CIRRUS_MISC_CTL_2_SUSPEND
;
490 pcic_write(h
, PCIC_CIRRUS_MISC_CTL_2
, reg
);
494 /* if there's a card there, then attach it. */
495 reg
= pcic_read(h
, PCIC_IF_STATUS
);
496 if ((reg
& PCIC_IF_STATUS_CARDDETECT_MASK
) ==
497 PCIC_IF_STATUS_CARDDETECT_PRESENT
) {
498 pcic_queue_event(h
, PCIC_EVENT_INSERTION
);
499 h
->laststate
= PCIC_LASTSTATE_PRESENT
;
501 h
->laststate
= PCIC_LASTSTATE_EMPTY
;
505 * queue creation of a kernel thread to handle insert/removal events.
508 if (h
->event_thread
!= NULL
)
509 panic("pcic_attach_socket: event thread");
511 config_pending_incr();
512 snprintf(cs
, sizeof(cs
), "%d,%d", h
->chip
, h
->socket
);
514 if (kthread_create(PRI_NONE
, 0, NULL
, pcic_event_thread
, h
,
515 &h
->event_thread
, "%s,%s", device_xname(h
->ph_parent
), cs
)) {
516 aprint_error_dev(h
->ph_parent
,
517 "unable to create event thread for sock 0x%02x\n", h
->sock
);
518 panic("pcic_attach_socket");
523 pcic_event_thread(void *arg
)
525 struct pcic_handle
*h
= arg
;
526 struct pcic_event
*pe
;
528 struct pcic_softc
*sc
= device_private(h
->ph_parent
);
530 while (h
->shutdown
== 0) {
532 * Serialize event processing on the PCIC. We may
533 * sleep while we hold this lock.
535 mutex_enter(&sc
->sc_pcic_lock
);
538 if ((pe
= SIMPLEQ_FIRST(&h
->events
)) == NULL
) {
542 config_pending_decr();
545 * No events to process; release the PCIC lock.
547 (void) mutex_exit(&sc
->sc_pcic_lock
);
548 (void) tsleep(&h
->events
, PWAIT
, "pcicev", 0);
552 /* sleep .25s to be enqueued chatterling interrupts */
553 (void) tsleep((void *)pcic_event_thread
, PWAIT
,
557 SIMPLEQ_REMOVE_HEAD(&h
->events
, pe_q
);
560 switch (pe
->pe_type
) {
561 case PCIC_EVENT_INSERTION
:
564 struct pcic_event
*pe1
, *pe2
;
566 if ((pe1
= SIMPLEQ_FIRST(&h
->events
)) == NULL
)
568 if (pe1
->pe_type
!= PCIC_EVENT_REMOVAL
)
570 if ((pe2
= SIMPLEQ_NEXT(pe1
, pe_q
)) == NULL
)
572 if (pe2
->pe_type
== PCIC_EVENT_INSERTION
) {
573 SIMPLEQ_REMOVE_HEAD(&h
->events
, pe_q
);
575 SIMPLEQ_REMOVE_HEAD(&h
->events
, pe_q
);
581 DPRINTF(("%s: insertion event\n",
582 device_xname(h
->ph_parent
)));
586 case PCIC_EVENT_REMOVAL
:
589 struct pcic_event
*pe1
, *pe2
;
591 if ((pe1
= SIMPLEQ_FIRST(&h
->events
)) == NULL
)
593 if (pe1
->pe_type
!= PCIC_EVENT_INSERTION
)
595 if ((pe2
= SIMPLEQ_NEXT(pe1
, pe_q
)) == NULL
)
597 if (pe2
->pe_type
== PCIC_EVENT_REMOVAL
) {
598 SIMPLEQ_REMOVE_HEAD(&h
->events
, pe_q
);
600 SIMPLEQ_REMOVE_HEAD(&h
->events
, pe_q
);
606 DPRINTF(("%s: removal event\n",
607 device_xname(h
->ph_parent
)));
608 pcic_detach_card(h
, DETACH_FORCE
);
612 panic("pcic_event_thread: unknown event %d",
617 mutex_exit(&sc
->sc_pcic_lock
);
620 h
->event_thread
= NULL
;
622 /* In case parent is waiting for us to exit. */
629 pcic_print(void *arg
, const char *pnp
)
631 struct pcmciabus_attach_args
*paa
= arg
;
632 struct pcic_handle
*h
= (struct pcic_handle
*) paa
->pch
;
634 /* Only "pcmcia"s can attach to "pcic"s... easy. */
636 aprint_normal("pcmcia at %s", pnp
);
638 aprint_normal(" controller %d socket %d", h
->chip
, h
->socket
);
644 pcic_poll_intr(void *arg
)
646 struct pcic_softc
*sc
;
651 for (i
= 0; i
< __arraycount(sc
->handle
); i
++)
652 if (sc
->handle
[i
].flags
& PCIC_FLAG_SOCKETP
)
653 (void)pcic_intr_socket(&sc
->handle
[i
]);
654 callout_reset(&sc
->poll_ch
, hz
/ 2, pcic_poll_intr
, sc
);
661 struct pcic_softc
*sc
= arg
;
664 DPRINTF(("%s: intr\n", device_xname(&sc
->dev
)));
666 for (i
= 0; i
< __arraycount(sc
->handle
); i
++)
667 if (sc
->handle
[i
].flags
& PCIC_FLAG_SOCKETP
)
668 ret
+= pcic_intr_socket(&sc
->handle
[i
]);
674 pcic_intr_socket(struct pcic_handle
*h
)
678 cscreg
= pcic_read(h
, PCIC_CSC
);
680 cscreg
&= (PCIC_CSC_GPI
|
686 if (cscreg
& PCIC_CSC_GPI
) {
687 DPRINTF(("%s: %02x GPI\n",
688 device_xname(h
->ph_parent
), h
->sock
));
690 if (cscreg
& PCIC_CSC_CD
) {
693 statreg
= pcic_read(h
, PCIC_IF_STATUS
);
695 DPRINTF(("%s: %02x CD %x\n", device_xname(h
->ph_parent
),
698 if ((statreg
& PCIC_IF_STATUS_CARDDETECT_MASK
) ==
699 PCIC_IF_STATUS_CARDDETECT_PRESENT
) {
700 if (h
->laststate
!= PCIC_LASTSTATE_PRESENT
) {
701 DPRINTF(("%s: enqueing INSERTION event\n",
702 device_xname(h
->ph_parent
)));
703 pcic_queue_event(h
, PCIC_EVENT_INSERTION
);
705 h
->laststate
= PCIC_LASTSTATE_PRESENT
;
707 if (h
->laststate
== PCIC_LASTSTATE_PRESENT
) {
708 /* Deactivate the card now. */
709 DPRINTF(("%s: deactivating card\n",
710 device_xname(h
->ph_parent
)));
711 pcic_deactivate_card(h
);
713 DPRINTF(("%s: enqueing REMOVAL event\n",
714 device_xname(h
->ph_parent
)));
715 pcic_queue_event(h
, PCIC_EVENT_REMOVAL
);
717 h
->laststate
= PCIC_LASTSTATE_EMPTY
;
720 if (cscreg
& PCIC_CSC_READY
) {
721 DPRINTF(("%s: %02x READY\n", device_xname(h
->ph_parent
),
723 /* shouldn't happen */
725 if (cscreg
& PCIC_CSC_BATTWARN
) {
726 DPRINTF(("%s: %02x BATTWARN\n", device_xname(h
->ph_parent
),
729 if (cscreg
& PCIC_CSC_BATTDEAD
) {
730 DPRINTF(("%s: %02x BATTDEAD\n", device_xname(h
->ph_parent
),
733 return cscreg
? 1 : 0;
737 pcic_queue_event(struct pcic_handle
*h
, int event
)
739 struct pcic_event
*pe
;
742 pe
= malloc(sizeof(*pe
), M_TEMP
, M_NOWAIT
);
744 panic("pcic_queue_event: can't allocate event");
748 SIMPLEQ_INSERT_TAIL(&h
->events
, pe
, pe_q
);
754 pcic_attach_card(struct pcic_handle
*h
)
757 if ((h
->flags
& PCIC_FLAG_CARDP
) == 0) {
758 /* call the MI attach function */
759 pcmcia_card_attach(h
->pcmcia
);
761 h
->flags
|= PCIC_FLAG_CARDP
;
763 DPRINTF(("pcic_attach_card: already attached"));
768 pcic_detach_card(struct pcic_handle
*h
, int flags
)
769 /* flags: DETACH_* */
772 if (h
->flags
& PCIC_FLAG_CARDP
) {
773 h
->flags
&= ~PCIC_FLAG_CARDP
;
775 /* call the MI detach function */
776 pcmcia_card_detach(h
->pcmcia
, flags
);
778 DPRINTF(("pcic_detach_card: already detached"));
783 pcic_deactivate_card(struct pcic_handle
*h
)
787 /* call the MI deactivate function */
788 pcmcia_card_deactivate(h
->pcmcia
);
790 /* reset the socket */
791 intr
= pcic_read(h
, PCIC_INTR
);
792 intr
&= PCIC_INTR_ENABLE
;
793 pcic_write(h
, PCIC_INTR
, intr
);
795 /* power down the socket */
796 pcic_write(h
, PCIC_PWRCTL
, 0);
800 pcic_chip_mem_alloc(pcmcia_chipset_handle_t pch
, bus_size_t size
,
801 struct pcmcia_mem_handle
*pcmhp
)
803 struct pcic_handle
*h
= (struct pcic_handle
*) pch
;
804 bus_space_handle_t memh
;
807 int i
, mask
, mhandle
;
808 struct pcic_softc
*sc
= device_private(h
->ph_parent
);
810 /* out of sc->memh, allocate as many pages as necessary */
812 /* convert size to PCIC pages */
813 sizepg
= (size
+ (PCIC_MEM_ALIGN
- 1)) / PCIC_MEM_ALIGN
;
814 if (sizepg
> PCIC_MAX_MEM_PAGES
)
817 mask
= (1 << sizepg
) - 1;
819 addr
= 0; /* XXX gcc -Wuninitialized */
820 mhandle
= 0; /* XXX gcc -Wuninitialized */
822 for (i
= 0; i
<= PCIC_MAX_MEM_PAGES
- sizepg
; i
++) {
823 if ((sc
->subregionmask
& (mask
<< i
)) == (mask
<< i
)) {
824 if (bus_space_subregion(sc
->memt
, sc
->memh
,
825 i
* PCIC_MEM_PAGESIZE
,
826 sizepg
* PCIC_MEM_PAGESIZE
, &memh
))
829 addr
= sc
->membase
+ (i
* PCIC_MEM_PAGESIZE
);
830 sc
->subregionmask
&= ~(mhandle
);
831 pcmhp
->memt
= sc
->memt
;
835 pcmhp
->mhandle
= mhandle
;
836 pcmhp
->realsize
= sizepg
* PCIC_MEM_PAGESIZE
;
845 pcic_chip_mem_free(pcmcia_chipset_handle_t pch
, struct pcmcia_mem_handle
*pcmhp
)
847 struct pcic_handle
*h
= (struct pcic_handle
*) pch
;
848 struct pcic_softc
*sc
= device_private(h
->ph_parent
);
850 sc
->subregionmask
|= pcmhp
->mhandle
;
853 static const struct mem_map_index_st
{
854 int sysmem_start_lsb
;
855 int sysmem_start_msb
;
861 } mem_map_index
[] = {
863 PCIC_SYSMEM_ADDR0_START_LSB
,
864 PCIC_SYSMEM_ADDR0_START_MSB
,
865 PCIC_SYSMEM_ADDR0_STOP_LSB
,
866 PCIC_SYSMEM_ADDR0_STOP_MSB
,
867 PCIC_CARDMEM_ADDR0_LSB
,
868 PCIC_CARDMEM_ADDR0_MSB
,
869 PCIC_ADDRWIN_ENABLE_MEM0
,
872 PCIC_SYSMEM_ADDR1_START_LSB
,
873 PCIC_SYSMEM_ADDR1_START_MSB
,
874 PCIC_SYSMEM_ADDR1_STOP_LSB
,
875 PCIC_SYSMEM_ADDR1_STOP_MSB
,
876 PCIC_CARDMEM_ADDR1_LSB
,
877 PCIC_CARDMEM_ADDR1_MSB
,
878 PCIC_ADDRWIN_ENABLE_MEM1
,
881 PCIC_SYSMEM_ADDR2_START_LSB
,
882 PCIC_SYSMEM_ADDR2_START_MSB
,
883 PCIC_SYSMEM_ADDR2_STOP_LSB
,
884 PCIC_SYSMEM_ADDR2_STOP_MSB
,
885 PCIC_CARDMEM_ADDR2_LSB
,
886 PCIC_CARDMEM_ADDR2_MSB
,
887 PCIC_ADDRWIN_ENABLE_MEM2
,
890 PCIC_SYSMEM_ADDR3_START_LSB
,
891 PCIC_SYSMEM_ADDR3_START_MSB
,
892 PCIC_SYSMEM_ADDR3_STOP_LSB
,
893 PCIC_SYSMEM_ADDR3_STOP_MSB
,
894 PCIC_CARDMEM_ADDR3_LSB
,
895 PCIC_CARDMEM_ADDR3_MSB
,
896 PCIC_ADDRWIN_ENABLE_MEM3
,
899 PCIC_SYSMEM_ADDR4_START_LSB
,
900 PCIC_SYSMEM_ADDR4_START_MSB
,
901 PCIC_SYSMEM_ADDR4_STOP_LSB
,
902 PCIC_SYSMEM_ADDR4_STOP_MSB
,
903 PCIC_CARDMEM_ADDR4_LSB
,
904 PCIC_CARDMEM_ADDR4_MSB
,
905 PCIC_ADDRWIN_ENABLE_MEM4
,
910 pcic_chip_do_mem_map(struct pcic_handle
*h
, int win
)
913 int kind
= h
->mem
[win
].kind
& ~PCMCIA_WIDTH_MEM_MASK
;
915 (h
->mem
[win
].kind
& PCMCIA_WIDTH_MEM_MASK
) == PCMCIA_WIDTH_MEM8
916 || (kind
== PCMCIA_MEM_ATTR
);
918 DPRINTF(("mem8 %d\n", mem8
));
921 pcic_write(h
, mem_map_index
[win
].sysmem_start_lsb
,
922 (h
->mem
[win
].addr
>> PCIC_SYSMEM_ADDRX_SHIFT
) & 0xff);
923 pcic_write(h
, mem_map_index
[win
].sysmem_start_msb
,
924 ((h
->mem
[win
].addr
>> (PCIC_SYSMEM_ADDRX_SHIFT
+ 8)) &
925 PCIC_SYSMEM_ADDRX_START_MSB_ADDR_MASK
) |
926 (mem8
? 0 : PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT
));
928 pcic_write(h
, mem_map_index
[win
].sysmem_stop_lsb
,
929 ((h
->mem
[win
].addr
+ h
->mem
[win
].size
) >>
930 PCIC_SYSMEM_ADDRX_SHIFT
) & 0xff);
931 pcic_write(h
, mem_map_index
[win
].sysmem_stop_msb
,
932 (((h
->mem
[win
].addr
+ h
->mem
[win
].size
) >>
933 (PCIC_SYSMEM_ADDRX_SHIFT
+ 8)) &
934 PCIC_SYSMEM_ADDRX_STOP_MSB_ADDR_MASK
) |
935 PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2
);
937 pcic_write(h
, mem_map_index
[win
].cardmem_lsb
,
938 (h
->mem
[win
].offset
>> PCIC_CARDMEM_ADDRX_SHIFT
) & 0xff);
939 pcic_write(h
, mem_map_index
[win
].cardmem_msb
,
940 ((h
->mem
[win
].offset
>> (PCIC_CARDMEM_ADDRX_SHIFT
+ 8)) &
941 PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK
) |
942 ((kind
== PCMCIA_MEM_ATTR
) ?
943 PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR
: 0));
945 reg
= pcic_read(h
, PCIC_ADDRWIN_ENABLE
);
946 reg
|= (mem_map_index
[win
].memenable
| PCIC_ADDRWIN_ENABLE_MEMCS16
);
947 pcic_write(h
, PCIC_ADDRWIN_ENABLE
, reg
);
953 int r1
, r2
, r3
, r4
, r5
, r6
;
955 r1
= pcic_read(h
, mem_map_index
[win
].sysmem_start_msb
);
956 r2
= pcic_read(h
, mem_map_index
[win
].sysmem_start_lsb
);
957 r3
= pcic_read(h
, mem_map_index
[win
].sysmem_stop_msb
);
958 r4
= pcic_read(h
, mem_map_index
[win
].sysmem_stop_lsb
);
959 r5
= pcic_read(h
, mem_map_index
[win
].cardmem_msb
);
960 r6
= pcic_read(h
, mem_map_index
[win
].cardmem_lsb
);
962 DPRINTF(("pcic_chip_do_mem_map window %d: %02x%02x %02x%02x "
963 "%02x%02x\n", win
, r1
, r2
, r3
, r4
, r5
, r6
));
969 pcic_chip_mem_map(pcmcia_chipset_handle_t pch
, int kind
, bus_addr_t card_addr
,
970 bus_size_t size
, struct pcmcia_mem_handle
*pcmhp
, bus_size_t
*offsetp
,
973 struct pcic_handle
*h
= (struct pcic_handle
*) pch
;
977 struct pcic_softc
*sc
= device_private(h
->ph_parent
);
980 for (i
= 0; i
< (sizeof(mem_map_index
) / sizeof(mem_map_index
[0]));
982 if ((h
->memalloc
& (1 << i
)) == 0) {
984 h
->memalloc
|= (1 << i
);
994 /* XXX this is pretty gross */
996 if (sc
->memt
!= pcmhp
->memt
)
997 panic("pcic_chip_mem_map memt is bogus");
999 busaddr
= pcmhp
->addr
;
1002 * compute the address offset to the pcmcia address space for the
1003 * pcic. this is intentionally signed. The masks and shifts below
1004 * will cause TRT to happen in the pcic registers. Deal with making
1005 * sure the address is aligned, and return the alignment offset.
1008 *offsetp
= card_addr
% PCIC_MEM_ALIGN
;
1009 card_addr
-= *offsetp
;
1011 DPRINTF(("pcic_chip_mem_map window %d bus %lx+%lx+%lx at card addr "
1012 "%lx\n", win
, (u_long
) busaddr
, (u_long
) * offsetp
, (u_long
) size
,
1013 (u_long
) card_addr
));
1016 * include the offset in the size, and decrement size by one, since
1017 * the hw wants start/stop
1019 size
+= *offsetp
- 1;
1021 card_offset
= (((long) card_addr
) - ((long) busaddr
));
1023 h
->mem
[win
].addr
= busaddr
;
1024 h
->mem
[win
].size
= size
;
1025 h
->mem
[win
].offset
= card_offset
;
1026 h
->mem
[win
].kind
= kind
;
1028 pcic_chip_do_mem_map(h
, win
);
1034 pcic_chip_mem_unmap(pcmcia_chipset_handle_t pch
, int window
)
1036 struct pcic_handle
*h
= (struct pcic_handle
*) pch
;
1039 if (window
>= (sizeof(mem_map_index
) / sizeof(mem_map_index
[0])))
1040 panic("pcic_chip_mem_unmap: window out of range");
1042 reg
= pcic_read(h
, PCIC_ADDRWIN_ENABLE
);
1043 reg
&= ~mem_map_index
[window
].memenable
;
1044 pcic_write(h
, PCIC_ADDRWIN_ENABLE
, reg
);
1046 h
->memalloc
&= ~(1 << window
);
1050 pcic_chip_io_alloc(pcmcia_chipset_handle_t pch
, bus_addr_t start
,
1051 bus_size_t size
, bus_size_t align
, struct pcmcia_io_handle
*pcihp
)
1053 struct pcic_handle
*h
= (struct pcic_handle
*) pch
;
1054 bus_space_tag_t iot
;
1055 bus_space_handle_t ioh
;
1058 struct pcic_softc
*sc
= device_private(h
->ph_parent
);
1061 * Allocate some arbitrary I/O space.
1068 if (bus_space_map(iot
, start
, size
, 0, &ioh
))
1070 DPRINTF(("pcic_chip_io_alloc map port %lx+%lx\n",
1071 (u_long
) ioaddr
, (u_long
) size
));
1073 flags
|= PCMCIA_IO_ALLOCATED
;
1074 if (bus_space_alloc(iot
, sc
->iobase
,
1075 sc
->iobase
+ sc
->iosize
, size
, align
, 0, 0,
1078 DPRINTF(("pcic_chip_io_alloc alloc port %lx+%lx\n",
1079 (u_long
) ioaddr
, (u_long
) size
));
1084 pcihp
->addr
= ioaddr
;
1086 pcihp
->flags
= flags
;
1092 pcic_chip_io_free(pcmcia_chipset_handle_t pch
, struct pcmcia_io_handle
*pcihp
)
1094 bus_space_tag_t iot
= pcihp
->iot
;
1095 bus_space_handle_t ioh
= pcihp
->ioh
;
1096 bus_size_t size
= pcihp
->size
;
1098 if (pcihp
->flags
& PCMCIA_IO_ALLOCATED
)
1099 bus_space_free(iot
, ioh
, size
);
1101 bus_space_unmap(iot
, ioh
, size
);
1105 static const struct io_map_index_st
{
1112 int ioctlbits
[3]; /* indexed by PCMCIA_WIDTH_* */
1113 } io_map_index
[] = {
1115 PCIC_IOADDR0_START_LSB
,
1116 PCIC_IOADDR0_START_MSB
,
1117 PCIC_IOADDR0_STOP_LSB
,
1118 PCIC_IOADDR0_STOP_MSB
,
1119 PCIC_ADDRWIN_ENABLE_IO0
,
1120 PCIC_IOCTL_IO0_WAITSTATE
| PCIC_IOCTL_IO0_ZEROWAIT
|
1121 PCIC_IOCTL_IO0_IOCS16SRC_MASK
| PCIC_IOCTL_IO0_DATASIZE_MASK
,
1123 PCIC_IOCTL_IO0_IOCS16SRC_CARD
,
1124 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE
|
1125 PCIC_IOCTL_IO0_DATASIZE_8BIT
,
1126 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE
|
1127 PCIC_IOCTL_IO0_DATASIZE_16BIT
,
1131 PCIC_IOADDR1_START_LSB
,
1132 PCIC_IOADDR1_START_MSB
,
1133 PCIC_IOADDR1_STOP_LSB
,
1134 PCIC_IOADDR1_STOP_MSB
,
1135 PCIC_ADDRWIN_ENABLE_IO1
,
1136 PCIC_IOCTL_IO1_WAITSTATE
| PCIC_IOCTL_IO1_ZEROWAIT
|
1137 PCIC_IOCTL_IO1_IOCS16SRC_MASK
| PCIC_IOCTL_IO1_DATASIZE_MASK
,
1139 PCIC_IOCTL_IO1_IOCS16SRC_CARD
,
1140 PCIC_IOCTL_IO1_IOCS16SRC_DATASIZE
|
1141 PCIC_IOCTL_IO1_DATASIZE_8BIT
,
1142 PCIC_IOCTL_IO1_IOCS16SRC_DATASIZE
|
1143 PCIC_IOCTL_IO1_DATASIZE_16BIT
,
1149 pcic_chip_do_io_map(struct pcic_handle
*h
, int win
)
1153 DPRINTF(("pcic_chip_do_io_map win %d addr %lx size %lx width %d\n",
1154 win
, (long) h
->io
[win
].addr
, (long) h
->io
[win
].size
,
1155 h
->io
[win
].width
* 8));
1157 pcic_write(h
, io_map_index
[win
].start_lsb
, h
->io
[win
].addr
& 0xff);
1158 pcic_write(h
, io_map_index
[win
].start_msb
,
1159 (h
->io
[win
].addr
>> 8) & 0xff);
1161 pcic_write(h
, io_map_index
[win
].stop_lsb
,
1162 (h
->io
[win
].addr
+ h
->io
[win
].size
- 1) & 0xff);
1163 pcic_write(h
, io_map_index
[win
].stop_msb
,
1164 ((h
->io
[win
].addr
+ h
->io
[win
].size
- 1) >> 8) & 0xff);
1166 reg
= pcic_read(h
, PCIC_IOCTL
);
1167 reg
&= ~io_map_index
[win
].ioctlmask
;
1168 reg
|= io_map_index
[win
].ioctlbits
[h
->io
[win
].width
];
1169 pcic_write(h
, PCIC_IOCTL
, reg
);
1171 reg
= pcic_read(h
, PCIC_ADDRWIN_ENABLE
);
1172 reg
|= io_map_index
[win
].ioenable
;
1173 pcic_write(h
, PCIC_ADDRWIN_ENABLE
, reg
);
1177 pcic_chip_io_map(pcmcia_chipset_handle_t pch
, int width
, bus_addr_t offset
,
1178 bus_size_t size
, struct pcmcia_io_handle
*pcihp
, int *windowp
)
1180 struct pcic_handle
*h
= (struct pcic_handle
*) pch
;
1181 bus_addr_t ioaddr
= pcihp
->addr
+ offset
;
1184 static const char *width_names
[] = { "auto", "io8", "io16" };
1186 struct pcic_softc
*sc
= device_private(h
->ph_parent
);
1188 /* XXX Sanity check offset/size. */
1191 for (i
= 0; i
< (sizeof(io_map_index
) / sizeof(io_map_index
[0])); i
++) {
1192 if ((h
->ioalloc
& (1 << i
)) == 0) {
1194 h
->ioalloc
|= (1 << i
);
1204 /* XXX this is pretty gross */
1206 if (sc
->iot
!= pcihp
->iot
)
1207 panic("pcic_chip_io_map iot is bogus");
1209 DPRINTF(("pcic_chip_io_map window %d %s port %lx+%lx\n",
1210 win
, width_names
[width
], (u_long
) ioaddr
, (u_long
) size
));
1212 /* XXX wtf is this doing here? */
1214 printf("%s: port 0x%lx", device_xname(&sc
->dev
), (u_long
) ioaddr
);
1216 printf("-0x%lx", (u_long
) ioaddr
+ (u_long
) size
- 1);
1219 h
->io
[win
].addr
= ioaddr
;
1220 h
->io
[win
].size
= size
;
1221 h
->io
[win
].width
= width
;
1223 pcic_chip_do_io_map(h
, win
);
1229 pcic_chip_io_unmap(pcmcia_chipset_handle_t pch
, int window
)
1231 struct pcic_handle
*h
= (struct pcic_handle
*) pch
;
1234 if (window
>= (sizeof(io_map_index
) / sizeof(io_map_index
[0])))
1235 panic("pcic_chip_io_unmap: window out of range");
1237 reg
= pcic_read(h
, PCIC_ADDRWIN_ENABLE
);
1238 reg
&= ~io_map_index
[window
].ioenable
;
1239 pcic_write(h
, PCIC_ADDRWIN_ENABLE
, reg
);
1241 h
->ioalloc
&= ~(1 << window
);
1245 pcic_wait_ready(struct pcic_handle
*h
)
1250 /* wait an initial 10ms for quick cards */
1251 stat
= pcic_read(h
, PCIC_IF_STATUS
);
1252 if (stat
& PCIC_IF_STATUS_READY
)
1254 pcic_delay(h
, 10, "pccwr0");
1255 for (i
= 0; i
< 50; i
++) {
1256 stat
= pcic_read(h
, PCIC_IF_STATUS
);
1257 if (stat
& PCIC_IF_STATUS_READY
)
1259 if ((stat
& PCIC_IF_STATUS_CARDDETECT_MASK
) !=
1260 PCIC_IF_STATUS_CARDDETECT_PRESENT
)
1262 /* wait .1s (100ms) each iteration now */
1263 pcic_delay(h
, 100, "pccwr1");
1266 printf("pcic_wait_ready: ready never happened, status=%02x\n", stat
);
1271 * Perform long (msec order) delay.
1274 pcic_delay(struct pcic_handle
*h
, int timo
, const char *wmesg
)
1275 /* timo: in ms. must not be zero */
1280 panic("pcic_delay: called with timeout %d", timo
);
1282 panic("pcic_delay: called in interrupt context");
1283 if (!h
->event_thread
)
1284 panic("pcic_delay: no event thread");
1286 DPRINTF(("pcic_delay: \"%s\" %p, sleep %d ms\n",
1287 wmesg
, h
->event_thread
, timo
));
1291 tsleep(pcic_delay
, PWAIT
, wmesg
,
1292 roundup(timo
* hz
, 1000) / 1000);
1296 pcic_chip_socket_enable(pcmcia_chipset_handle_t pch
)
1298 struct pcic_handle
*h
= (struct pcic_handle
*) pch
;
1300 uint8_t power
, intr
;
1306 if (h
->flags
& PCIC_FLAG_ENABLED
)
1307 printf("pcic_chip_socket_enable: enabling twice\n");
1310 /* disable interrupts; assert RESET */
1311 intr
= pcic_read(h
, PCIC_INTR
);
1312 intr
&= PCIC_INTR_ENABLE
;
1313 pcic_write(h
, PCIC_INTR
, intr
);
1315 /* zero out the address windows */
1316 pcic_write(h
, PCIC_ADDRWIN_ENABLE
, 0);
1318 /* power off; assert output enable bit */
1319 power
= PCIC_PWRCTL_OE
;
1320 pcic_write(h
, PCIC_PWRCTL
, power
);
1323 * power hack for RICOH RF5C[23]96
1325 switch (h
->vendor
) {
1326 case PCIC_VENDOR_RICOH_5C296
:
1327 case PCIC_VENDOR_RICOH_5C396
:
1330 regtmp
= pcic_read(h
, PCIC_RICOH_REG_MCR2
);
1331 #ifdef RICOH_POWER_HACK
1332 regtmp
|= PCIC_RICOH_MCR2_VCC_DIRECT
;
1335 ~(PCIC_RICOH_MCR2_VCC_DIRECT
|PCIC_RICOH_MCR2_VCC_SEL_3V
);
1337 pcic_write(h
, PCIC_RICOH_REG_MCR2
, regtmp
);
1344 #ifdef VADEM_POWER_HACK
1345 bus_space_write_1(sc
->iot
, sc
->ioh
, PCIC_REG_INDEX
, 0x0e);
1346 bus_space_write_1(sc
->iot
, sc
->ioh
, PCIC_REG_INDEX
, 0x37);
1347 printf("prcr = %02x\n", pcic_read(h
, 0x02));
1348 printf("cvsr = %02x\n", pcic_read(h
, 0x2f));
1349 printf("DANGER WILL ROBINSON! Changing voltage select!\n");
1350 pcic_write(h
, 0x2f, pcic_read(h
, 0x2f) & ~0x03);
1351 printf("cvsr = %02x\n", pcic_read(h
, 0x2f));
1354 /* power up the socket */
1355 power
|= PCIC_PWRCTL_PWR_ENABLE
| PCIC_PWRCTL_VPP1_VCC
;
1356 pcic_write(h
, PCIC_PWRCTL
, power
);
1359 * Table 4-18 and figure 4-6 of the PC Card specifiction say:
1360 * Vcc Rising Time (Tpr) = 100ms
1361 * RESET Width (Th (Hi-z RESET)) = 1ms
1362 * RESET Width (Tw (RESET)) = 10us
1364 * some machines require some more time to be settled
1365 * (100ms is added here).
1367 pcic_delay(h
, 200 + 1, "pccen1");
1370 intr
|= PCIC_INTR_RESET
;
1371 pcic_write(h
, PCIC_INTR
, intr
);
1374 * RESET Setup Time (Tsu (RESET)) = 20ms
1376 pcic_delay(h
, 20, "pccen2");
1379 reg
= pcic_read(h
, PCIC_IF_STATUS
);
1380 if ((reg
& PCIC_IF_STATUS_POWERACTIVE
) == 0)
1381 printf("pcic_chip_socket_enable: no power, status=%x\n", reg
);
1384 /* wait for the chip to finish initializing */
1385 if (pcic_wait_ready(h
)) {
1386 /* XXX return a failure status?? */
1387 pcic_write(h
, PCIC_PWRCTL
, 0);
1391 /* reinstall all the memory and io mappings */
1392 for (win
= 0; win
< PCIC_MEM_WINS
; win
++)
1393 if (h
->memalloc
& (1 << win
))
1394 pcic_chip_do_mem_map(h
, win
);
1395 for (win
= 0; win
< PCIC_IO_WINS
; win
++)
1396 if (h
->ioalloc
& (1 << win
))
1397 pcic_chip_do_io_map(h
, win
);
1399 h
->flags
|= PCIC_FLAG_ENABLED
;
1403 pcic_chip_socket_disable(pcmcia_chipset_handle_t pch
)
1405 struct pcic_handle
*h
= (struct pcic_handle
*) pch
;
1408 DPRINTF(("pcic_chip_socket_disable\n"));
1410 /* disable interrupts; assert RESET */
1411 intr
= pcic_read(h
, PCIC_INTR
);
1412 intr
&= PCIC_INTR_ENABLE
;
1413 pcic_write(h
, PCIC_INTR
, intr
);
1415 /* zero out the address windows */
1416 pcic_write(h
, PCIC_ADDRWIN_ENABLE
, 0);
1418 /* disable socket: negate output enable bit and power off */
1419 pcic_write(h
, PCIC_PWRCTL
, 0);
1422 * Vcc Falling Time (Tpf) = 300ms
1424 pcic_delay(h
, 300, "pccwr1");
1426 h
->flags
&= ~PCIC_FLAG_ENABLED
;
1430 pcic_chip_socket_settype(pcmcia_chipset_handle_t pch
, int type
)
1432 struct pcic_handle
*h
= (struct pcic_handle
*) pch
;
1435 intr
= pcic_read(h
, PCIC_INTR
);
1436 intr
&= ~(PCIC_INTR_IRQ_MASK
| PCIC_INTR_CARDTYPE_MASK
);
1437 if (type
== PCMCIA_IFTYPE_IO
) {
1438 intr
|= PCIC_INTR_CARDTYPE_IO
;
1439 intr
|= h
->ih_irq
<< PCIC_INTR_IRQ_SHIFT
;
1441 intr
|= PCIC_INTR_CARDTYPE_MEM
;
1442 pcic_write(h
, PCIC_INTR
, intr
);
1444 DPRINTF(("%s: pcic_chip_socket_settype %02x type %s %02x\n",
1445 device_xname(h
->ph_parent
), h
->sock
,
1446 ((type
== PCMCIA_IFTYPE_IO
) ? "io" : "mem"), intr
));
1450 st_pcic_read(struct pcic_handle
*h
, int idx
)
1454 bus_space_write_1(h
->ph_bus_t
, h
->ph_bus_h
, PCIC_REG_INDEX
,
1456 return bus_space_read_1(h
->ph_bus_t
, h
->ph_bus_h
, PCIC_REG_DATA
);
1460 st_pcic_write(struct pcic_handle
*h
, int idx
, uint8_t data
)
1464 bus_space_write_1(h
->ph_bus_t
, h
->ph_bus_h
, PCIC_REG_INDEX
,
1466 bus_space_write_1(h
->ph_bus_t
, h
->ph_bus_h
, PCIC_REG_DATA
, data
);