sys/dev/ic/i82595reg.h

   1 /*      $NetBSD: i82595reg.h,v 1.9 2007/03/04 02:59:07 tsutsui Exp $    */
   2
   3 /*-
   4  * Copyright (c) 1996 The NetBSD Foundation, Inc.
   5  * All rights reserved.
   6  *
   7  * This code is derived from software contributed to The NetBSD Foundation
   8  * by Ignatios Souvatzis.
   9  *
  10  * Redistribution and use in source and binary forms, with or without
  11  * modification, are permitted provided that the following conditions
  12  * are met:
  13  * 1. Redistributions of source code must retain the above copyright
  14  *    notice, this list of conditions and the following disclaimer.
  15  * 2. Redistributions in binary form must reproduce the above copyright
  16  *    notice, this list of conditions and the following disclaimer in the
  17  *    documentation and/or other materials provided with the distribution.
  18  *
  19  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
  20  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  21  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  22  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
  23  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  29  * POSSIBILITY OF SUCH DAMAGE.
  30  */
  31
  32 /*
  33  * Intel 82595 Ethernet chip register, bit, and structure definitions.
  34  *
  35  * Written by is with reference to Intel's i82595FX data sheet, with some
  36  * clarification coming from looking at the Clarkson Packet Driver code for this
  37  * chip written by Russ Nelson and others;
  38  *
  39  * and
  40  *
  41  * configuration EEPROM layout. Written with reference to Intels
  42  * public "LAN595 Hardware and Software Specifications" document.
  43  */
  44
  45 /* registers */
  46
  47 /* bank0 */
  48
  49 #define COMMAND_REG 0   /* available in any bank */
  50
  51 #define         MC_SETUP_CMD    0x03
  52 #define         XMT_CMD         0x04
  53 #define         TDR_CMD         0x05
  54 #define         DUMP_CMD        0x06
  55 #define         DIAG_CMD        0x07
  56 #define         RCV_ENABLE_CMD  0x08
  57 #define         RCV_DISABLE_CMD 0x0a
  58 #define         RCV_STOP_CMD    0x0b
  59 #define         RESET_CMD       0x0e
  60 #define         TRISTATE_CMD    0x16
  61 #define         NO_TRISTATE_CMD 0x17
  62 #define         POWER_DOWN_CMD  0x18
  63 #define         SLEEP_MODE_CMD  0x19
  64 #define         NEGOTIATE_CMD   0x1a
  65 #define         RESUME_XMT_CMD  0x1c
  66 #define         SEL_RESET_CMD   0x1e
  67 #define         BANK_SEL(n)     (n<<6)  /* 0, 1, 2 */
  68
  69 #define STATUS_REG 1
  70
  71 #define         RX_STP_INT      0x01
  72 #define         RX_INT          0x02
  73 #define         TX_INT          0x04
  74 #define         EXEC_INT        0x08
  75 #define         EXEC_STATUS     0x30
  76
  77 #define ID_REG 2
  78
  79 #define         ID_REG_MASK     0x2c
  80 #define         ID_REG_SIG      0x24
  81 #define         R_ROBIN_BITS    0xc0
  82 #define         R_ROBIN_SHIFT   6
  83 #define         AUTO_ENABLE     0x10
  84
  85 #define INT_MASK_REG 3
  86
  87 #define         RX_STOP_BIT     0x01
  88 #define         RX_BIT          0x02
  89 #define         TX_BIT          0x04
  90 #define         EXEC_BIT        0x08
  91 #define         ALL_INTS        0x0f
  92
  93 #define RCV_START_LOW 4
  94 #define RCV_START_HIGH 5
  95
  96 #define RCV_STOP_LOW 6
  97 #define RCV_STOP_HIGH 7
  98
  99 #define RCV_COPY_THRESHOLD 8    /* byte */
 100
 101 #define XMT_ADDR_REG 0x0a
 102 #define HOST_ADDR_REG 0x0c
 103 #define MEM_PORT_REG 0x0e
 104
 105 /* -------------------- bank1 -------------------- */
 106
 107 #define REG1 1
 108
 109 #define         WORD_WIDTH      0x02
 110 #define         INT_ENABLE      0x80
 111
 112 #define INT_NO_REG 2
 113
 114 #define RCV_LOWER_LIMIT_REG 8
 115 #define RCV_UPPER_LIMIT_REG 9
 116
 117 #define XMT_LOWER_LIMIT_REG 10
 118 #define XMT_UPPER_LIMIT_REG 11
 119
 120 /* bank2 */
 121
 122 /* reg1, apparently */
 123
 124 #define         XMT_CHAIN_INT   0x20    /* interrupt at end of xmt chain */
 125 #define         XMT_CHAIN_ERRSTOP 0x40  /* int at end of chain even if err */
 126 #define         RCV_DISCARD_BAD 0x80    /* Throw bad frames away and continue */
 127
 128 #define RECV_MODES_REG 2
 129
 130 #define         PROMISC_MODE    0x01
 131 #define         NO_BRDCST       0x02
 132 #define         NO_RX_CRC       0x04
 133 #define         NO_ADD_INS      0x10
 134 #define         MULTI_IA        0x20
 135
 136 #define         MATCH_ID        (NO_ADD_INS | NO_RX_CRC | NO_BRDCST)
 137 #define         MATCH_BRDCST    (NO_ADD_INS | NO_RX_CRC)
 138 #define         MATCH_MULTI     (NO_ADD_INS | NO_RX_CRC | MULTI_IA)
 139 #define         MATCH_ALL       (NO_ADD_INS | NO_RX_CRC | PROMISC_MODE)
 140
 141 #define MEDIA_SELECT 3
 142
 143 #define         TPE_BIT         0x04
 144 #define         BNC_BIT         0x20
 145 #define         TEST_MODE_MASK  0x3f
 146
 147 #define I_ADD(n) (n+4)  /* 0..5 -> 4..9 */
 148
 149 #define EEPROM_REG 10
 150
 151 #define         EEDO 8
 152 #define         EEDI 4
 153 #define         EECS 2
 154 #define         EESK 1
 155
 156 /*
 157  * EEPROM layout. Written with reference to Intels public "LAN595 Hardware and
 158  * Software Specifications" document.
 159  */
 160
 161 #define EEPPW0          0
 162 #define         EEPP_BusWidth   0x0004
 163 #define         EEPP_FlashAdrs  0x0038
 164 #define         EEPP_FLASHTRANSFORM {-1, -1, 0xC8000, 0xCC000, 0xD0000, \
 165                                         0xD4000, 0xD8000, 0xDC000}
 166 #define         EEPP_AutoIO     0x0040
 167 #define         EEPP_IOMapping  0xfc00
 168
 169 #define EEPPW1          1
 170 #define         EEPP_Int        0x0007
 171 #define         EEPP_INTMAP     {9, 3, 5, 10, 11, -1, -1, -1}
 172 #define         EEPP_RINTMAP    {0xff, 0xff, 0x02, 0x00, 0xff, 0x01, 0xff, \
 173                                  0xff, 0xff, 0x02, 0x03, 0x04 }
 174
 175 #define         EEPP_LinkInteg  0x0008
 176 #define         EEPP_PolarCorr  0x0010
 177 #define         EEPP_AuiTpe     0x0020
 178 #define         EEPP_Jabber     0x0040
 179 #define         EEPP_AutoPort   0x0080
 180 #define         EEPP_SmOut      0x0100
 181 #define         EEPP_BootFls    0x0200
 182 #define         EEPP_DramSize   0x1000
 183 #define         EEPP_AltReady   0x2000
 184
 185 #define EEPPEther2      2
 186 #define EEPPEther1      3
 187 #define EEPPEther0      4
 188
 189 #define EEPPEther2a     0x3c
 190 #define EEPPEther1a     0x3d
 191 #define EEPPEther0a     0x3e
 192
 193 #define EEPPW5          5
 194 #define         EEPP_BncTpe     0x0001
 195 #define         EEPP_RomSlct    0x0006  /* none, NetWare, NDIS, rsrvd. */
 196 #define         EEPP_NumConn    0x0008  /* 0=2, 1=3 */
 197
 198 #define EEPW6           6
 199 #define EEPP_BoardRev   0x00FF
 200
 201 #define EEPP_LENGTH 0x40
 202 #define EEPP_CHKSUM 0xBABA /* Intel claim 0x0, but this seems to be wrong */
 203
 204 #define RCV_NO_RSC_REG  11
 205         /* How many packets were dropped due to insufficient space */
 206
 207 /* ---- xmt /rcv /exec buffer format ---- */
 208
 209 #define I595_XMT_HDRLEN 8
 210
 211 #define CMD_MASK        0x001f
 212 #define TX_DONE         0x0080
 213 #define CHAIN           0x8000
 214
 215 #define XMT_STATUS      0x02
 216 #define XMT_CHAIN       0x04
 217 #define XMT_COUNT       0x06
 218
 219 #define I595_RCV_HDRLEN 8
 220
 221 #define RCV_DONE        0x0008
 222 #define RX_OK           0x2000
 223 #define RX_ERR          0x0d81
 224
 225