sys/dev/ic/ims332reg.h

   1 /* $NetBSD: ims332reg.h,v 1.1.46.1 2005/03/04 16:41:29 skrll Exp $ */
   2
   3 /*
   4  * Mach Operating System
   5  * Copyright (c) 1991,1990,1989 Carnegie Mellon University
   6  * All Rights Reserved.
   7  *
   8  * Permission to use, copy, modify and distribute this software and its
   9  * documentation is hereby granted, provided that both the copyright
  10  * notice and this permission notice appear in all copies of the
  11  * software, derivative works or modified versions, and any portions
  12  * thereof, and that both notices appear in supporting documentation.
  13  *
  14  * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
  15  * CONDITION.  CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR
  16  * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
  17  *
  18  * Carnegie Mellon requests users of this software to return to
  19  *
  20  *  Software Distribution Coordinator  or  Software.Distribution@CS.CMU.EDU
  21  *  School of Computer Science
  22  *  Carnegie Mellon University
  23  *  Pittsburgh PA 15213-3890
  24  *
  25  * any improvements or extensions that they make and grant Carnegie Mellon
  26  * the rights to redistribute these changes.
  27  */
  28
  29 /*
  30  *      Defines for the Inmos IMS-G332 Colour video controller
  31  *      Author: Alessandro Forin, Carnegie Mellon University
  32  *      See: IMS G332 Colour Video Controller, 1990 Databook, pg 139-163,
  33  *              Inmos, Ltd.
  34  */
  35
  36 /*
  37  * Although the chip is built to be memory-mapped
  38  * it can be programmed for 32 or 64 bit addressing.
  39  * Moreover, the hardware bits have been twisted
  40  * even more on the machine I am writing this for.
  41  * So I'll just define the chip's offsets and leave
  42  * it to the implementation to define the rest.
  43  */
  44
  45 #define IMS332_REG_BOOT                 0x000   /* boot time config */
  46
  47 #define IMS332_REG_HALF_SYNCH           0x021   /* datapath registers */
  48 #define IMS332_REG_BACK_PORCH           0x022
  49 #define IMS332_REG_DISPLAY              0x023
  50 #define IMS332_REG_SHORT_DIS            0x024
  51 #define IMS332_REG_BROAD_PULSE          0x025
  52 #define IMS332_REG_V_SYNC               0x026
  53 #define IMS332_REG_V_PRE_EQUALIZE       0x027
  54 #define IMS332_REG_V_POST_EQUALIZE      0x028
  55 #define IMS332_REG_V_BLANK              0x029
  56 #define IMS332_REG_V_DISPLAY            0x02a
  57 #define IMS332_REG_LINE_TIME            0x02b
  58 #define IMS332_REG_LINE_START           0x02c
  59 #define IMS332_REG_MEM_INIT             0x02d
  60 #define IMS332_REG_XFER_DELAY           0x02e
  61
  62 #define IMS332_REG_COLOR_MASK           0x040   /* color mask register */
  63
  64 #define IMS332_REG_CSR_A                0x060
  65
  66 #define IMS332_REG_CSR_B                0x070
  67
  68 #define IMS332_REG_TOP_SCREEN           0x080   /* top-of-screen offset */
  69
  70 #define IMS332_REG_CURSOR_LUT_0         0x0a1   /* cursor palette */
  71 #define IMS332_REG_CURSOR_LUT_1         0x0a2
  72 #define IMS332_REG_CURSOR_LUT_2         0x0a3
  73
  74 #define IMS332_REG_RGB_CKSUM_0          0x0c0   /* test registers */
  75 #define IMS332_REG_RGB_CKSUM_1          0x0c1
  76 #define IMS332_REG_RGB_CKSUM_2          0x0c2
  77
  78 #define IMS332_REG_CURSOR_LOC           0x0c7   /* cursor location */
  79
  80 #define IMS332_REG_LUT_BASE             0x100   /* color palette */
  81 #define IMS332_REG_LUT_END              0x1ff
  82
  83 #define IMS332_REG_CURSOR_RAM           0x200   /* cursor bitmap */
  84 #define IMS332_REG_CURSOR_RAM_END       0x3ff
  85
  86 /*
  87  * Control register A
  88  */
  89
  90 #define IMS332_CSR_A_VTG_ENABLE         0x000001        /* vertical timing generator */
  91 #define IMS332_CSR_A_INTERLACED         0x000002        /* screen format */
  92 #define IMS332_CSR_A_CCIR               0x000004        /* default is EIA */
  93 #define IMS332_CSR_A_SLAVE_SYNC         0x000008        /* else from our pll */
  94 #define IMS332_CSR_A_PLAIN_SYNC         0x000010        /* else tesselated */
  95 #define IMS332_CSR_A_SEPARATE_SYNC      0x000020        /* else composite */
  96 #define IMS332_CSR_A_VIDEO_ONLY         0x000040        /* else video+sync */
  97 #define IMS332_CSR_A_BLANK_PEDESTAL     0x000080        /* blank level */
  98 #define IMS332_CSR_A_CBLANK_IS_OUT      0x000100
  99 #define IMS332_CSR_A_CBLANK_NO_DELAY    0x000200
 100 #define IMS332_CSR_A_FORCE_BLANK        0x000400
 101 #define IMS332_CSR_A_BLANK_DISABLE      0x000800
 102 #define IMS332_CSR_A_VRAM_INCREMENT     0x003000
 103 #       define IMS332_VRAM_INC_1        0x000000
 104 #       define IMS332_VRAM_INC_256      0x001000        /* except interlaced->2 */
 105 #       define IMS332_VRAM_INC_512      0x002000
 106 #       define IMS332_VRAM_INC_1024     0x003000
 107 #define IMS332_CSR_A_DMA_DISABLE        0x004000
 108 #define IMS332_CSR_A_SYNC_DELAY_MASK    0x038000        /* 0-7 VTG clk delays */
 109 #define IMS332_CSR_A_PIXEL_INTERLEAVE   0x040000
 110 #define IMS332_CSR_A_DELAYED_SAMPLING   0x080000
 111 #define IMS332_CSR_A_BITS_PER_PIXEL     0x700000
 112 #       define IMS332_BPP_1             0x000000
 113 #       define IMS332_BPP_2             0x100000
 114 #       define IMS332_BPP_4             0x200000
 115 #       define IMS332_BPP_8             0x300000
 116 #       define IMS332_BPP_15            0x400000
 117 #       define IMS332_BPP_16            0x500000
 118 #define IMS332_CSR_A_DISABLE_CURSOR     0x800000
 119
 120
 121 /*
 122  * Control register B is mbz
 123  */
 124
 125 /*
 126  * Boot register
 127  */
 128
 129 #define IMS332_BOOT_PLL                 0x00001f        /* xPLL, binary */
 130 #define IMS332_BOOT_CLOCK_PLL           0x000020        /* else xternal */
 131 #define IMS332_BOOT_64_BIT_MODE         0x000040        /* else 32 */
 132 #define IMS332_BOOT_xxx                 0xffff80        /* reserved, mbz */