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[netbsd-mini2440.git] / sys / dev / ic / midway.c
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1 /* $NetBSD: midway.c,v 1.87 2009/03/15 15:52:12 cegger Exp $ */
2 /* (sync'd to midway.c 1.68) */
3
4 /*
5 *
6 * Copyright (c) 1996 Charles D. Cranor and Washington University.
7 * All rights reserved.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. All advertising materials mentioning features or use of this software
18 * must display the following acknowledgement:
19 * This product includes software developed by Charles D. Cranor and
20 * Washington University.
21 * 4. The name of the author may not be used to endorse or promote products
22 * derived from this software without specific prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
25 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
26 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
27 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
28 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
29 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
30 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
31 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
32 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
33 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 */
35
36 /*
37 *
38 * m i d w a y . c e n i 1 5 5 d r i v e r
39 *
40 * author: Chuck Cranor <chuck@ccrc.wustl.edu>
41 * started: spring, 1996 (written from scratch).
42 *
43 * notes from the author:
44 * Extra special thanks go to Werner Almesberger, EPFL LRC. Werner's
45 * ENI driver was especially useful in figuring out how this card works.
46 * I would also like to thank Werner for promptly answering email and being
47 * generally helpful.
48 */
49 /*
50 * 1997/12/02, major update on 1999/04/06 kjc
51 * new features added:
52 * - BPF support (link type is DLT_ATM_RFC1483)
53 * BPF understands only LLC/SNAP!! (because bpf can't
54 * handle variable link header length.)
55 * (bpfwrite should work if atm_pseudohdr and LLC/SNAP are prepended.)
56 * - support vc shaping
57 * - integrate IPv6 support.
58 * - support pvc sub interface
59 *
60 * initial work on per-pvc-interface for ipv6 was done
61 * by Katsushi Kobayashi <ikob@cc.uec.ac.jp> of the WIDE Project.
62 * some of the extensions for pvc subinterfaces are merged from
63 * the CAIRN project written by Suresh Bhogavilli (suresh@isi.edu).
64 *
65 * code cleanup:
66 * - remove WMAYBE related code. ENI WMAYBE DMA doesn't work.
67 * - remove updating if_lastchange for every packet.
68 */
69
70 #include <sys/cdefs.h>
71 __KERNEL_RCSID(0, "$NetBSD: midway.c,v 1.87 2009/03/15 15:52:12 cegger Exp $");
72
73 #include "opt_natm.h"
74
75 #undef EN_DEBUG
76 #undef EN_DEBUG_RANGE /* check ranges on en_read/en_write's? */
77 #define EN_MBUF_OPT /* try and put more stuff in mbuf? */
78 #define EN_DIAG
79 #define EN_STAT
80 #ifndef EN_DMA
81 #define EN_DMA 1 /* use DMA? */
82 #endif
83 #define EN_NOTXDMA 0 /* hook to disable tx DMA only */
84 #define EN_NORXDMA 0 /* hook to disable rx DMA only */
85 #define EN_NOWMAYBE 1 /* hook to disable word maybe DMA */
86 /* XXX: WMAYBE doesn't work, needs debugging */
87 #define EN_DDBHOOK 1 /* compile in ddb functions */
88 #if defined(MIDWAY_ADPONLY)
89 #define EN_ENIDMAFIX 0 /* no ENI cards to worry about */
90 #else
91 #define EN_ENIDMAFIX 1 /* avoid byte DMA on the ENI card (see below) */
92 #endif
93
94 /*
95 * note on EN_ENIDMAFIX: the byte aligner on the ENI version of the card
96 * appears to be broken. it works just fine if there is no load... however
97 * when the card is loaded the data get corrupted. to see this, one only
98 * has to use "telnet" over ATM. do the following command in "telnet":
99 * cat /usr/share/misc/termcap
100 * "telnet" seems to generate lots of 1023 byte mbufs (which make great
101 * use of the byte aligner). watch "netstat -s" for checksum errors.
102 *
103 * I further tested this by adding a function that compared the transmit
104 * data on the card's SRAM with the data in the mbuf chain _after_ the
105 * "transmit DMA complete" interrupt. using the "telnet" test I got data
106 * mismatches where the byte-aligned data should have been. using ddb
107 * and en_dumpmem() I verified that the DTQs fed into the card were
108 * absolutely correct. thus, we are forced to concluded that the ENI
109 * hardware is buggy. note that the Adaptec version of the card works
110 * just fine with byte DMA.
111 *
112 * bottom line: we set EN_ENIDMAFIX to 1 to avoid byte DMAs on the ENI
113 * card.
114 */
115
116 #if defined(DIAGNOSTIC) && !defined(EN_DIAG)
117 #define EN_DIAG /* link in with master DIAG option */
118 #endif
119 #ifdef EN_STAT
120 #define EN_COUNT(X) (X)++
121 #else
122 #define EN_COUNT(X) /* nothing */
123 #endif
124
125 #ifdef EN_DEBUG
126 #undef EN_DDBHOOK
127 #define EN_DDBHOOK 1
128 #define STATIC /* nothing */
129 #define INLINE /* nothing */
130 #else /* EN_DEBUG */
131 #define STATIC static
132 #define INLINE inline
133 #endif /* EN_DEBUG */
134
135 #ifdef __FreeBSD__
136 #include "en.h"
137 #endif
138
139 #ifdef __NetBSD__
140 #include "opt_ddb.h"
141 #include "opt_inet.h"
142 #else
143 #define snprintb((q), (f), "%b", q,f,b,l) snprintf((b), (l))
144 #endif
145
146 #if NEN > 0 || !defined(__FreeBSD__)
147
148 #include <sys/param.h>
149 #include <sys/systm.h>
150 #if defined(__NetBSD__) || defined(__OpenBSD__) || defined(__bsdi__)
151 #include <sys/device.h>
152 #endif
153 #if defined(__FreeBSD__)
154 #include <sys/sockio.h>
155 #else
156 #include <sys/ioctl.h>
157 #endif
158 #include <sys/mbuf.h>
159 #include <sys/socket.h>
160 #include <sys/socketvar.h>
161 #include <sys/queue.h>
162 #include <sys/proc.h>
163 #include <sys/kauth.h>
164
165 #include <net/if.h>
166 #include <net/if_ether.h>
167 #include <net/if_atm.h>
168
169 #ifdef __NetBSD__
170 #include <uvm/uvm_extern.h>
171 #else
172 #include <vm/vm.h>
173 #endif
174
175 #if defined(INET) || defined(INET6)
176 #include <netinet/in.h>
177 #include <netinet/if_atm.h>
178 #ifdef INET6
179 #include <netinet6/in6_var.h>
180 #endif
181 #endif
182
183 #ifdef NATM
184 #if !(defined(INET) || defined(INET6))
185 #include <netinet/in.h>
186 #endif
187 #include <netnatm/natm.h>
188 #endif
189
190
191 #if !defined(__FreeBSD__)
192 #include <sys/bus.h>
193
194 #endif
195
196 #if defined(__NetBSD__) || defined(__OpenBSD__)
197 #include <dev/ic/midwayreg.h>
198 #include <dev/ic/midwayvar.h>
199 #if defined(__alpha__)
200 /* XXX XXX NEED REAL DMA MAPPING SUPPORT XXX XXX */
201 #undef vtophys
202 #define vtophys(va) alpha_XXX_dmamap((vaddr_t)(va))
203 #endif
204 #elif defined(__FreeBSD__)
205 #include <machine/cpufunc.h> /* for rdtsc proto for clock.h below */
206 #include <machine/clock.h> /* for DELAY */
207 #include <dev/en/midwayreg.h>
208 #include <dev/en/midwayvar.h>
209 #include <vm/pmap.h> /* for vtophys proto */
210
211 /*
212 * 2.1.x does not have if_softc. detect this by seeing if IFF_NOTRAILERS
213 * is defined, as per kjc.
214 */
215 #ifdef IFF_NOTRAILERS
216 #define MISSING_IF_SOFTC
217 #else
218 #define IFF_NOTRAILERS 0
219 #endif
220
221 #endif /* __FreeBSD__ */
222
223 #ifdef ATM_PVCEXT
224 # ifndef NATM
225 /* this is for for __KAME__ */
226 # include <netinet/in.h>
227 # endif
228 # if defined (__KAME__) && defined(INET6)
229 # include <netinet6/in6_ifattach.h>
230 # endif
231 #endif /*ATM_PVCEXT*/
232
233 #include "bpfilter.h"
234 #if NBPFILTER > 0
235 #include <net/bpf.h>
236 #ifdef __FreeBSD__
237 #define BPFATTACH(ifp, dlt, hlen) bpfattach((ifp), (dlt), (hlen))
238 #define BPF_MTAP(ifp, m) bpf_mtap((ifp), (m))
239 #else
240 #define BPFATTACH(ifp, dlt, hlen) bpfattach(&(ifp)->if_bpf, (ifp), (dlt), (hlen))
241 #define BPF_MTAP(ifp, m) bpf_mtap((ifp)->if_bpf, (m))
242 #endif
243 #endif /* NBPFILTER > 0 */
244
245 /*
246 * params
247 */
248
249 #ifndef EN_TXHIWAT
250 #define EN_TXHIWAT (64*1024) /* max 64 KB waiting to be DMAd out */
251 #endif
252
253 #ifndef EN_MINDMA
254 #define EN_MINDMA 32 /* don't DMA anything less than this (bytes) */
255 #endif
256
257 #define RX_NONE 0xffff /* recv VC not in use */
258
259 #define EN_OBHDR ATM_PH_DRIVER7 /* TBD in first mbuf ! */
260 #define EN_OBTRL ATM_PH_DRIVER8 /* PDU trailer in last mbuf ! */
261
262 #define ENOTHER_FREE 0x01 /* free rxslot */
263 #define ENOTHER_DRAIN 0x02 /* almost free (drain DRQ DMA) */
264 #define ENOTHER_RAW 0x04 /* 'raw' access (aka boodi mode) */
265 #define ENOTHER_SWSL 0x08 /* in software service list */
266
267 int en_dma = EN_DMA; /* use DMA (switch off for dbg) */
268
269 /*
270 * autoconfig attachments
271 */
272
273 extern struct cfdriver en_cd;
274
275 /*
276 * local structures
277 */
278
279 /*
280 * params to en_txlaunch() function
281 */
282
283 struct en_launch {
284 u_int32_t tbd1; /* TBD 1 */
285 u_int32_t tbd2; /* TBD 2 */
286 u_int32_t pdu1; /* PDU 1 (aal5) */
287 int nodma; /* don't use DMA */
288 int need; /* total space we need (pad out if less data) */
289 int mlen; /* length of mbuf (for dtq) */
290 struct mbuf *t; /* data */
291 u_int32_t aal; /* aal code */
292 u_int32_t atm_vci; /* vci */
293 u_int8_t atm_flags; /* flags */
294 };
295
296
297 /*
298 * DMA table (index by # of words)
299 *
300 * plan A: use WMAYBE
301 * plan B: avoid WMAYBE
302 */
303
304 struct en_dmatab {
305 u_int8_t bcode; /* code */
306 u_int8_t divshift; /* byte divisor */
307 };
308
309 static struct en_dmatab en_dma_planA[] = {
310 { 0, 0 }, /* 0 */ { MIDDMA_WORD, 2 }, /* 1 */
311 { MIDDMA_2WORD, 3}, /* 2 */ { MIDDMA_4WMAYBE, 2}, /* 3 */
312 { MIDDMA_4WORD, 4}, /* 4 */ { MIDDMA_8WMAYBE, 2}, /* 5 */
313 { MIDDMA_8WMAYBE, 2}, /* 6 */ { MIDDMA_8WMAYBE, 2}, /* 7 */
314 { MIDDMA_8WORD, 5}, /* 8 */ { MIDDMA_16WMAYBE, 2}, /* 9 */
315 { MIDDMA_16WMAYBE,2}, /* 10 */ { MIDDMA_16WMAYBE, 2}, /* 11 */
316 { MIDDMA_16WMAYBE,2}, /* 12 */ { MIDDMA_16WMAYBE, 2}, /* 13 */
317 { MIDDMA_16WMAYBE,2}, /* 14 */ { MIDDMA_16WMAYBE, 2}, /* 15 */
318 { MIDDMA_16WORD, 6}, /* 16 */
319 };
320
321 static struct en_dmatab en_dma_planB[] = {
322 { 0, 0 }, /* 0 */ { MIDDMA_WORD, 2}, /* 1 */
323 { MIDDMA_2WORD, 3}, /* 2 */ { MIDDMA_WORD, 2}, /* 3 */
324 { MIDDMA_4WORD, 4}, /* 4 */ { MIDDMA_WORD, 2}, /* 5 */
325 { MIDDMA_2WORD, 3}, /* 6 */ { MIDDMA_WORD, 2}, /* 7 */
326 { MIDDMA_8WORD, 5}, /* 8 */ { MIDDMA_WORD, 2}, /* 9 */
327 { MIDDMA_2WORD, 3}, /* 10 */ { MIDDMA_WORD, 2}, /* 11 */
328 { MIDDMA_4WORD, 4}, /* 12 */ { MIDDMA_WORD, 2}, /* 13 */
329 { MIDDMA_2WORD, 3}, /* 14 */ { MIDDMA_WORD, 2}, /* 15 */
330 { MIDDMA_16WORD, 6}, /* 16 */
331 };
332
333 static struct en_dmatab *en_dmaplan = en_dma_planA;
334
335 /*
336 * prototypes
337 */
338
339 STATIC INLINE int en_b2sz(int) __unused;
340 #ifdef EN_DDBHOOK
341 int en_dump(int,int);
342 int en_dumpmem(int,int,int);
343 #endif
344 STATIC void en_dmaprobe(struct en_softc *);
345 STATIC int en_dmaprobe_doit(struct en_softc *, u_int8_t *,
346 u_int8_t *, int);
347 STATIC INLINE int en_dqneed(struct en_softc *, void *, u_int,
348 u_int) __unused;
349 STATIC void en_init(struct en_softc *);
350 STATIC int en_ioctl(struct ifnet *, EN_IOCTL_CMDT, void *);
351 STATIC INLINE int en_k2sz(int) __unused;
352 STATIC void en_loadvc(struct en_softc *, int);
353 STATIC int en_mfix(struct en_softc *, struct mbuf **,
354 struct mbuf *);
355 STATIC INLINE struct mbuf *en_mget(struct en_softc *, u_int,
356 u_int *) __unused;
357 STATIC INLINE u_int32_t en_read(struct en_softc *,
358 u_int32_t) __unused;
359 STATIC int en_rxctl(struct en_softc *, struct atm_pseudoioctl *, int);
360 STATIC void en_txdma(struct en_softc *, int);
361 STATIC void en_txlaunch(struct en_softc *, int, struct en_launch *);
362 STATIC void en_service(struct en_softc *);
363 STATIC void en_start(struct ifnet *);
364 STATIC INLINE int en_sz2b(int) __unused;
365 STATIC INLINE void en_write(struct en_softc *, u_int32_t,
366 u_int32_t) __unused;
367
368 #ifdef ATM_PVCEXT
369 static void rrp_add(struct en_softc *, struct ifnet *);
370 static struct ifnet *en_pvcattach(struct ifnet *);
371 static int en_txctl(struct en_softc *, int, int, int);
372 static int en_pvctx(struct en_softc *, struct pvctxreq *);
373 static int en_pvctxget(struct en_softc *, struct pvctxreq *);
374 static int en_pcr2txspeed(int);
375 static int en_txspeed2pcr(int);
376 static struct ifnet *en_vci2ifp(struct en_softc *, int);
377 #endif
378
379 /*
380 * macros/inline
381 */
382
383 /*
384 * raw read/write macros
385 */
386
387 #define EN_READDAT(SC,R) en_read(SC,R)
388 #define EN_WRITEDAT(SC,R,V) en_write(SC,R,V)
389
390 /*
391 * cooked read/write macros
392 */
393
394 #define EN_READ(SC,R) ntohl(en_read(SC,R))
395 #define EN_WRITE(SC,R,V) en_write(SC,R, htonl(V))
396
397 #define EN_WRAPADD(START,STOP,CUR,VAL) { \
398 (CUR) = (CUR) + (VAL); \
399 if ((CUR) >= (STOP)) \
400 (CUR) = (START) + ((CUR) - (STOP)); \
401 }
402
403 #define WORD_IDX(START, X) (((X) - (START)) / sizeof(u_int32_t))
404
405 /* we store sc->dtq and sc->drq data in the following format... */
406 #define EN_DQ_MK(SLOT,LEN) (((SLOT) << 20)|(LEN)|(0x80000))
407 /* the 0x80000 ensures we != 0 */
408 #define EN_DQ_SLOT(X) ((X) >> 20)
409 #define EN_DQ_LEN(X) ((X) & 0x3ffff)
410
411 /* format of DTQ/DRQ word 1 differs between ENI and ADP */
412 #if defined(MIDWAY_ENIONLY)
413
414 #define MID_MK_TXQ(SC,CNT,CHAN,END,BCODE) \
415 EN_WRITE((SC), (SC)->dtq_us, \
416 MID_MK_TXQ_ENI((CNT), (CHAN), (END), (BCODE)));
417
418 #define MID_MK_RXQ(SC,CNT,VCI,END,BCODE) \
419 EN_WRITE((SC), (SC)->drq_us, \
420 MID_MK_RXQ_ENI((CNT), (VCI), (END), (BCODE)));
421
422 #elif defined(MIDWAY_ADPONLY)
423
424 #define MID_MK_TXQ(SC,CNT,CHAN,END,JK) \
425 EN_WRITE((SC), (SC)->dtq_us, \
426 MID_MK_TXQ_ADP((CNT), (CHAN), (END), (JK)));
427
428 #define MID_MK_RXQ(SC,CNT,VCI,END,JK) \
429 EN_WRITE((SC), (SC)->drq_us, \
430 MID_MK_RXQ_ADP((CNT), (VCI), (END), (JK)));
431
432 #else
433
434 #define MID_MK_TXQ(SC,CNT,CHAN,END,JK_OR_BCODE) { \
435 if ((SC)->is_adaptec) \
436 EN_WRITE((SC), (SC)->dtq_us, \
437 MID_MK_TXQ_ADP((CNT), (CHAN), (END), (JK_OR_BCODE))); \
438 else \
439 EN_WRITE((SC), (SC)->dtq_us, \
440 MID_MK_TXQ_ENI((CNT), (CHAN), (END), (JK_OR_BCODE))); \
441 }
442
443 #define MID_MK_RXQ(SC,CNT,VCI,END,JK_OR_BCODE) { \
444 if ((SC)->is_adaptec) \
445 EN_WRITE((SC), (SC)->drq_us, \
446 MID_MK_RXQ_ADP((CNT), (VCI), (END), (JK_OR_BCODE))); \
447 else \
448 EN_WRITE((SC), (SC)->drq_us, \
449 MID_MK_RXQ_ENI((CNT), (VCI), (END), (JK_OR_BCODE))); \
450 }
451
452 #endif
453
454 /* add an item to the DTQ */
455 #define EN_DTQADD(SC,CNT,CHAN,JK_OR_BCODE,ADDR,LEN,END) { \
456 if (END) \
457 (SC)->dtq[MID_DTQ_A2REG((SC)->dtq_us)] = EN_DQ_MK(CHAN,LEN); \
458 MID_MK_TXQ(SC,CNT,CHAN,END,JK_OR_BCODE); \
459 (SC)->dtq_us += 4; \
460 EN_WRITE((SC), (SC)->dtq_us, (ADDR)); \
461 EN_WRAPADD(MID_DTQOFF, MID_DTQEND, (SC)->dtq_us, 4); \
462 (SC)->dtq_free--; \
463 if (END) \
464 EN_WRITE((SC), MID_DMA_WRTX, MID_DTQ_A2REG((SC)->dtq_us)); \
465 }
466
467 /* DRQ add macro */
468 #define EN_DRQADD(SC,CNT,VCI,JK_OR_BCODE,ADDR,LEN,SLOT,END) { \
469 if (END) \
470 (SC)->drq[MID_DRQ_A2REG((SC)->drq_us)] = EN_DQ_MK(SLOT,LEN); \
471 MID_MK_RXQ(SC,CNT,VCI,END,JK_OR_BCODE); \
472 (SC)->drq_us += 4; \
473 EN_WRITE((SC), (SC)->drq_us, (ADDR)); \
474 EN_WRAPADD(MID_DRQOFF, MID_DRQEND, (SC)->drq_us, 4); \
475 (SC)->drq_free--; \
476 if (END) \
477 EN_WRITE((SC), MID_DMA_WRRX, MID_DRQ_A2REG((SC)->drq_us)); \
478 }
479
480 /*
481 * the driver code
482 *
483 * the code is arranged in a specific way:
484 * [1] short/inline functions
485 * [2] autoconfig stuff
486 * [3] ioctl stuff
487 * [4] reset -> init -> transmit -> intr -> receive functions
488 *
489 */
490
491 /***********************************************************************/
492
493 /*
494 * en_read: read a word from the card. this is the only function
495 * that reads from the card.
496 */
497
498 STATIC INLINE u_int32_t en_read(struct en_softc *sc, uint32_t r)
499 {
500
501 #ifdef EN_DEBUG_RANGE
502 if (r > MID_MAXOFF || (r % 4))
503 panic("en_read out of range, r=0x%x", r);
504 #endif
505
506 return(bus_space_read_4(sc->en_memt, sc->en_base, r));
507 }
508
509 /*
510 * en_write: write a word to the card. this is the only function that
511 * writes to the card.
512 */
513
514 STATIC INLINE void en_write(struct en_softc *sc, uint32_t r, uint32_t v)
515 {
516 #ifdef EN_DEBUG_RANGE
517 if (r > MID_MAXOFF || (r % 4))
518 panic("en_write out of range, r=0x%x", r);
519 #endif
520
521 bus_space_write_4(sc->en_memt, sc->en_base, r, v);
522 }
523
524 /*
525 * en_k2sz: convert KBytes to a size parameter (a log2)
526 */
527
528 STATIC INLINE int en_k2sz(int k)
529 {
530 switch(k) {
531 case 1: return(0);
532 case 2: return(1);
533 case 4: return(2);
534 case 8: return(3);
535 case 16: return(4);
536 case 32: return(5);
537 case 64: return(6);
538 case 128: return(7);
539 default: panic("en_k2sz");
540 }
541 return(0);
542 }
543 #define en_log2(X) en_k2sz(X)
544
545
546 /*
547 * en_b2sz: convert a DMA burst code to its byte size
548 */
549
550 STATIC INLINE int en_b2sz(int b)
551 {
552 switch (b) {
553 case MIDDMA_WORD: return(1*4);
554 case MIDDMA_2WMAYBE:
555 case MIDDMA_2WORD: return(2*4);
556 case MIDDMA_4WMAYBE:
557 case MIDDMA_4WORD: return(4*4);
558 case MIDDMA_8WMAYBE:
559 case MIDDMA_8WORD: return(8*4);
560 case MIDDMA_16WMAYBE:
561 case MIDDMA_16WORD: return(16*4);
562 default: panic("en_b2sz");
563 }
564 return(0);
565 }
566
567
568 /*
569 * en_sz2b: convert a burst size (bytes) to DMA burst code
570 */
571
572 STATIC INLINE int en_sz2b(int sz)
573 {
574 switch (sz) {
575 case 1*4: return(MIDDMA_WORD);
576 case 2*4: return(MIDDMA_2WORD);
577 case 4*4: return(MIDDMA_4WORD);
578 case 8*4: return(MIDDMA_8WORD);
579 case 16*4: return(MIDDMA_16WORD);
580 default: panic("en_sz2b");
581 }
582 return(0);
583 }
584
585
586 /*
587 * en_dqneed: calculate number of DTQ/DRQ's needed for a buffer
588 */
589
590 STATIC INLINE int en_dqneed(struct en_softc *sc, void *data, u_int len, u_int tx)
591 {
592 int result, needalign, sz;
593
594 #if !defined(MIDWAY_ENIONLY)
595 #if !defined(MIDWAY_ADPONLY)
596 if (sc->is_adaptec)
597 #endif /* !MIDWAY_ADPONLY */
598 return(1); /* adaptec can DMA anything in one go */
599 #endif
600
601 #if !defined(MIDWAY_ADPONLY)
602 result = 0;
603 if (len < EN_MINDMA) {
604 if (!tx) /* XXX: conservative */
605 return(1); /* will copy/DMA_JK */
606 }
607
608 if (tx) { /* byte burst? */
609 needalign = (((unsigned long) data) % sizeof(u_int32_t));
610 if (needalign) {
611 result++;
612 sz = min(len, sizeof(u_int32_t) - needalign);
613 len -= sz;
614 data = (char *)data + sz;
615 }
616 }
617
618 if (sc->alburst && len) {
619 needalign = (((unsigned long) data) & sc->bestburstmask);
620 if (needalign) {
621 result++; /* alburst */
622 sz = min(len, sc->bestburstlen - needalign);
623 len -= sz;
624 }
625 }
626
627 if (len >= sc->bestburstlen) {
628 sz = len / sc->bestburstlen;
629 sz = sz * sc->bestburstlen;
630 len -= sz;
631 result++; /* best shot */
632 }
633
634 if (len) {
635 result++; /* clean up */
636 if (tx && (len % sizeof(u_int32_t)) != 0)
637 result++; /* byte cleanup */
638 }
639
640 return(result);
641 #endif /* !MIDWAY_ADPONLY */
642 }
643
644
645 /*
646 * en_mget: get an mbuf chain that can hold totlen bytes and return it
647 * (for recv) [based on am7990_get from if_le and ieget from if_ie]
648 * after this call the sum of all the m_len's in the chain will be totlen.
649 */
650
651 STATIC INLINE struct mbuf *en_mget(struct en_softc *sc, u_int totlen, u_int *drqneed)
652 {
653 struct mbuf *m;
654 struct mbuf *top, **mp;
655 *drqneed = 0;
656
657 MGETHDR(m, M_DONTWAIT, MT_DATA);
658 if (m == NULL)
659 return(NULL);
660 m->m_pkthdr.rcvif = &sc->enif;
661 m->m_pkthdr.len = totlen;
662 m->m_len = MHLEN;
663 top = NULL;
664 mp = &top;
665
666 /* if (top != NULL) then we've already got 1 mbuf on the chain */
667 while (totlen > 0) {
668 if (top) {
669 MGET(m, M_DONTWAIT, MT_DATA);
670 if (!m) {
671 m_freem(top);
672 return(NULL); /* out of mbufs */
673 }
674 m->m_len = MLEN;
675 }
676 if (totlen >= MINCLSIZE) {
677 MCLGET(m, M_DONTWAIT);
678 if ((m->m_flags & M_EXT) == 0) {
679 m_free(m);
680 m_freem(top);
681 return(NULL); /* out of mbuf clusters */
682 }
683 m->m_len = MCLBYTES;
684 }
685 m->m_len = min(totlen, m->m_len);
686 totlen -= m->m_len;
687 *mp = m;
688 mp = &m->m_next;
689
690 *drqneed += en_dqneed(sc, m->m_data, m->m_len, 0);
691
692 }
693 return(top);
694 }
695
696 /***********************************************************************/
697
698 /*
699 * autoconfig stuff
700 */
701
702 void en_attach(struct en_softc *sc)
703 {
704 struct ifnet *ifp = &sc->enif;
705 int sz;
706 u_int32_t reg, lcv, check, ptr, sav, midvloc;
707
708 /*
709 * probe card to determine memory size. the stupid ENI card always
710 * reports to PCI that it needs 4MB of space (2MB regs and 2MB RAM).
711 * if it has less than 2MB RAM the addresses wrap in the RAM address space.
712 * (i.e. on a 512KB card addresses 0x3ffffc, 0x37fffc, and 0x2ffffc
713 * are aliases for 0x27fffc [note that RAM starts at offset 0x200000]).
714 */
715
716 if (sc->en_busreset)
717 sc->en_busreset(sc);
718 EN_WRITE(sc, MID_RESID, 0x0); /* reset card before touching RAM */
719 for (lcv = MID_PROBEOFF; lcv <= MID_MAXOFF ; lcv += MID_PROBSIZE) {
720 EN_WRITE(sc, lcv, lcv); /* data[address] = address */
721 for (check = MID_PROBEOFF ; check < lcv ; check += MID_PROBSIZE) {
722 reg = EN_READ(sc, check);
723 if (reg != check) { /* found an alias! */
724 goto done_probe; /* and quit */
725 }
726 }
727 }
728 done_probe:
729 lcv -= MID_PROBSIZE; /* take one step back */
730 sc->en_obmemsz = (lcv + 4) - MID_RAMOFF;
731
732 /*
733 * determine the largest DMA burst supported
734 */
735
736 en_dmaprobe(sc);
737
738 /*
739 * "hello world"
740 */
741
742 if (sc->en_busreset)
743 sc->en_busreset(sc);
744 EN_WRITE(sc, MID_RESID, 0x0); /* reset */
745 for (lcv = MID_RAMOFF ; lcv < MID_RAMOFF + sc->en_obmemsz ; lcv += 4)
746 EN_WRITE(sc, lcv, 0); /* zero memory */
747
748 reg = EN_READ(sc, MID_RESID);
749
750 aprint_normal_dev(&sc->sc_dev,
751 "ATM midway v%d, board IDs %d.%d, %s%s%s, %ldKB on-board RAM\n",
752 MID_VER(reg), MID_MID(reg), MID_DID(reg),
753 (MID_IS_SABRE(reg)) ? "sabre controller, " : "",
754 (MID_IS_SUNI(reg)) ? "SUNI" : "Utopia",
755 (!MID_IS_SUNI(reg) && MID_IS_UPIPE(reg)) ? " (pipelined)" : "",
756 (u_long)sc->en_obmemsz / 1024);
757
758 if (sc->is_adaptec) {
759 if (sc->bestburstlen == 64 && sc->alburst == 0)
760 aprint_normal_dev(&sc->sc_dev, "passed 64 byte DMA test\n");
761 else
762 aprint_error_dev(&sc->sc_dev, "FAILED DMA TEST: burst=%d, alburst=%d\n",
763 sc->bestburstlen, sc->alburst);
764 } else {
765 aprint_normal_dev(&sc->sc_dev, "maximum DMA burst length = %d bytes%s\n",
766 sc->bestburstlen, (sc->alburst) ? " (must align)" : "");
767 }
768
769 #if 0 /* WMAYBE doesn't work, don't complain about it */
770 /* check if en_dmaprobe disabled wmaybe */
771 if (en_dmaplan == en_dma_planB)
772 aprint_normal_dev(&sc->sc_dev, "note: WMAYBE DMA has been disabled\n");
773 #endif
774
775 /*
776 * link into network subsystem and prepare card
777 */
778
779 #if defined(__NetBSD__) || defined(__OpenBSD__)
780 strlcpy(sc->enif.if_xname, device_xname(&sc->sc_dev), IFNAMSIZ);
781 #endif
782 #if !defined(MISSING_IF_SOFTC)
783 sc->enif.if_softc = sc;
784 #endif
785 ifp->if_flags = IFF_SIMPLEX|IFF_NOTRAILERS;
786 ifp->if_ioctl = en_ioctl;
787 ifp->if_output = atm_output;
788 ifp->if_start = en_start;
789 IFQ_SET_READY(&ifp->if_snd);
790
791 /*
792 * init softc
793 */
794
795 for (lcv = 0 ; lcv < MID_N_VC ; lcv++) {
796 sc->rxvc2slot[lcv] = RX_NONE;
797 sc->txspeed[lcv] = 0; /* full */
798 sc->txvc2slot[lcv] = 0; /* full speed == slot 0 */
799 }
800
801 sz = sc->en_obmemsz - (MID_BUFOFF - MID_RAMOFF);
802 ptr = sav = MID_BUFOFF;
803 ptr = roundup(ptr, EN_TXSZ * 1024); /* align */
804 sz = sz - (ptr - sav);
805 if (EN_TXSZ*1024 * EN_NTX > sz) {
806 aprint_error_dev(&sc->sc_dev, "EN_NTX/EN_TXSZ too big\n");
807 return;
808 }
809 for (lcv = 0 ; lcv < EN_NTX ; lcv++) {
810 sc->txslot[lcv].mbsize = 0;
811 sc->txslot[lcv].start = ptr;
812 ptr += (EN_TXSZ * 1024);
813 sz -= (EN_TXSZ * 1024);
814 sc->txslot[lcv].stop = ptr;
815 sc->txslot[lcv].nref = 0;
816 #ifdef ATM_PVCEXT
817 sc->txrrp = NULL;
818 #endif
819 memset(&sc->txslot[lcv].indma, 0, sizeof(sc->txslot[lcv].indma));
820 memset(&sc->txslot[lcv].q, 0, sizeof(sc->txslot[lcv].q));
821 #ifdef EN_DEBUG
822 aprint_debug_dev(&sc->sc_dev, "tx%d: start 0x%x, stop 0x%x\n", lcv,
823 sc->txslot[lcv].start, sc->txslot[lcv].stop);
824 #endif
825 }
826
827 sav = ptr;
828 ptr = roundup(ptr, EN_RXSZ * 1024); /* align */
829 sz = sz - (ptr - sav);
830 sc->en_nrx = sz / (EN_RXSZ * 1024);
831 if (sc->en_nrx <= 0) {
832 aprint_error_dev(&sc->sc_dev, "EN_NTX/EN_TXSZ/EN_RXSZ too big\n");
833 return;
834 }
835
836 /*
837 * ensure that there is always one VC slot on the service list free
838 * so that we can tell the difference between a full and empty list.
839 */
840 if (sc->en_nrx >= MID_N_VC)
841 sc->en_nrx = MID_N_VC - 1;
842
843 for (lcv = 0 ; lcv < sc->en_nrx ; lcv++) {
844 sc->rxslot[lcv].rxhand = NULL;
845 sc->rxslot[lcv].oth_flags = ENOTHER_FREE;
846 memset(&sc->rxslot[lcv].indma, 0, sizeof(sc->rxslot[lcv].indma));
847 memset(&sc->rxslot[lcv].q, 0, sizeof(sc->rxslot[lcv].q));
848 midvloc = sc->rxslot[lcv].start = ptr;
849 ptr += (EN_RXSZ * 1024);
850 sz -= (EN_RXSZ * 1024);
851 sc->rxslot[lcv].stop = ptr;
852 midvloc = midvloc - MID_RAMOFF;
853 midvloc = (midvloc & ~((EN_RXSZ*1024) - 1)) >> 2; /* mask, cvt to words */
854 midvloc = midvloc >> MIDV_LOCTOPSHFT; /* we only want the top 11 bits */
855 midvloc = (midvloc & MIDV_LOCMASK) << MIDV_LOCSHIFT;
856 sc->rxslot[lcv].mode = midvloc |
857 (en_k2sz(EN_RXSZ) << MIDV_SZSHIFT) | MIDV_TRASH;
858
859 #ifdef EN_DEBUG
860 aprint_debug_dev(&sc->sc_dev, "rx%d: start 0x%x, stop 0x%x, mode 0x%x\n",
861 lcv, sc->rxslot[lcv].start, sc->rxslot[lcv].stop, sc->rxslot[lcv].mode);
862 #endif
863 }
864
865 #ifdef EN_STAT
866 sc->vtrash = sc->otrash = sc->mfix = sc->txmbovr = sc->dmaovr = 0;
867 sc->txoutspace = sc->txdtqout = sc->launch = sc->lheader = sc->ltail = 0;
868 sc->hwpull = sc->swadd = sc->rxqnotus = sc->rxqus = sc->rxoutboth = 0;
869 sc->rxdrqout = sc->ttrash = sc->rxmbufout = sc->mfixfail = 0;
870 sc->headbyte = sc->tailbyte = sc->tailflush = 0;
871 #endif
872 sc->need_drqs = sc->need_dtqs = 0;
873
874 aprint_normal_dev(&sc->sc_dev,
875 "%d %dKB receive buffers, %d %dKB transmit buffers allocated\n",
876 sc->en_nrx, EN_RXSZ, EN_NTX, EN_TXSZ);
877
878 aprint_normal_dev(&sc->sc_dev, "End Station Identifier (mac address) %s\n",
879 ether_sprintf(sc->macaddr));
880
881 /*
882 * final commit
883 */
884
885 if_attach(ifp);
886 atm_ifattach(ifp);
887
888 #ifdef ATM_PVCEXT
889 rrp_add(sc, ifp);
890 #endif
891 }
892
893
894 /*
895 * en_dmaprobe: helper function for en_attach.
896 *
897 * see how the card handles DMA by running a few DMA tests. we need
898 * to figure out the largest number of bytes we can DMA in one burst
899 * ("bestburstlen"), and if the starting address for a burst needs to
900 * be aligned on any sort of boundary or not ("alburst").
901 *
902 * typical findings:
903 * sparc1: bestburstlen=4, alburst=0 (ick, broken DMA!)
904 * sparc2: bestburstlen=64, alburst=1
905 * p166: bestburstlen=64, alburst=0
906 */
907
908 STATIC void en_dmaprobe(struct en_softc *sc)
909 {
910 u_int32_t srcbuf[64], dstbuf[64];
911 u_int8_t *sp, *dp;
912 int bestalgn, bestnotalgn, lcv, try, fail;
913
914 sc->alburst = 0;
915
916 sp = (u_int8_t *) srcbuf;
917 while ((((unsigned long) sp) % MIDDMA_MAXBURST) != 0)
918 sp += 4;
919 dp = (u_int8_t *) dstbuf;
920 while ((((unsigned long) dp) % MIDDMA_MAXBURST) != 0)
921 dp += 4;
922
923 bestalgn = bestnotalgn = en_dmaprobe_doit(sc, sp, dp, 0);
924
925 for (lcv = 4 ; lcv < MIDDMA_MAXBURST ; lcv += 4) {
926 try = en_dmaprobe_doit(sc, sp+lcv, dp+lcv, 0);
927 if (try < bestnotalgn)
928 bestnotalgn = try;
929 }
930
931 if (bestalgn != bestnotalgn) /* need bursts aligned */
932 sc->alburst = 1;
933
934 sc->bestburstlen = bestalgn;
935 sc->bestburstshift = en_log2(bestalgn);
936 sc->bestburstmask = sc->bestburstlen - 1; /* must be power of 2 */
937 sc->bestburstcode = en_sz2b(bestalgn);
938
939 if (sc->bestburstlen <= 2*sizeof(u_int32_t))
940 return; /* won't be using WMAYBE */
941
942 /*
943 * adaptec does not have (or need) wmaybe. do not bother testing
944 * for it.
945 */
946 if (sc->is_adaptec) {
947 /* XXX, actually don't need a DMA plan: adaptec is smarter than that */
948 en_dmaplan = en_dma_planB;
949 return;
950 }
951
952 /*
953 * test that WMAYBE DMA works like we think it should
954 * (i.e. no alignment restrictions on host address other than alburst)
955 */
956
957 try = sc->bestburstlen - 4;
958 fail = 0;
959 fail += en_dmaprobe_doit(sc, sp, dp, try);
960 for (lcv = 4 ; lcv < sc->bestburstlen ; lcv += 4) {
961 fail += en_dmaprobe_doit(sc, sp+lcv, dp+lcv, try);
962 if (sc->alburst)
963 try -= 4;
964 }
965 if (EN_NOWMAYBE || fail) {
966 if (fail)
967 aprint_error_dev(&sc->sc_dev, "WARNING: WMAYBE DMA test failed %d time(s)\n",
968 fail);
969 en_dmaplan = en_dma_planB; /* fall back to plan B */
970 }
971
972 }
973
974
975 /*
976 * en_dmaprobe_doit: do actual testing
977 */
978
979 int
980 en_dmaprobe_doit(struct en_softc *sc, uint8_t *sp, uint8_t *dp, int wmtry)
981 {
982 int lcv, retval = 4, cnt, count;
983 u_int32_t reg, bcode, midvloc;
984
985 /*
986 * set up a 1k buffer at MID_BUFOFF
987 */
988
989 if (sc->en_busreset)
990 sc->en_busreset(sc);
991 EN_WRITE(sc, MID_RESID, 0x0); /* reset card before touching RAM */
992
993 midvloc = ((MID_BUFOFF - MID_RAMOFF) / sizeof(u_int32_t)) >> MIDV_LOCTOPSHFT;
994 EN_WRITE(sc, MIDX_PLACE(0), MIDX_MKPLACE(en_k2sz(1), midvloc));
995 EN_WRITE(sc, MID_VC(0), (midvloc << MIDV_LOCSHIFT)
996 | (en_k2sz(1) << MIDV_SZSHIFT) | MIDV_TRASH);
997 EN_WRITE(sc, MID_DST_RP(0), 0);
998 EN_WRITE(sc, MID_WP_ST_CNT(0), 0);
999
1000 for (lcv = 0 ; lcv < 68 ; lcv++) /* set up sample data */
1001 sp[lcv] = lcv+1;
1002 EN_WRITE(sc, MID_MAST_CSR, MID_MCSR_ENDMA); /* enable DMA (only) */
1003
1004 sc->drq_chip = MID_DRQ_REG2A(EN_READ(sc, MID_DMA_RDRX));
1005 sc->dtq_chip = MID_DTQ_REG2A(EN_READ(sc, MID_DMA_RDTX));
1006
1007 /*
1008 * try it now . . . DMA it out, then DMA it back in and compare
1009 *
1010 * note: in order to get the DMA stuff to reverse directions it wants
1011 * the "end" flag set! since we are not DMA'ing valid data we may
1012 * get an ident mismatch interrupt (which we will ignore).
1013 *
1014 * note: we've got two different tests rolled up in the same loop
1015 * if (wmtry)
1016 * then we are doing a wmaybe test and wmtry is a byte count
1017 * else we are doing a burst test
1018 */
1019
1020 for (lcv = 8 ; lcv <= MIDDMA_MAXBURST ; lcv = lcv * 2) {
1021
1022 /* zero SRAM and dest buffer */
1023 for (cnt = 0 ; cnt < 1024; cnt += 4)
1024 EN_WRITE(sc, MID_BUFOFF+cnt, 0); /* zero memory */
1025 for (cnt = 0 ; cnt < 68 ; cnt++)
1026 dp[cnt] = 0;
1027
1028 if (wmtry) {
1029 count = (sc->bestburstlen - sizeof(u_int32_t)) / sizeof(u_int32_t);
1030 bcode = en_dmaplan[count].bcode;
1031 count = wmtry >> en_dmaplan[count].divshift;
1032 } else {
1033 bcode = en_sz2b(lcv);
1034 count = 1;
1035 }
1036 if (sc->is_adaptec)
1037 EN_WRITE(sc, sc->dtq_chip, MID_MK_TXQ_ADP(lcv, 0, MID_DMA_END, 0));
1038 else
1039 EN_WRITE(sc, sc->dtq_chip, MID_MK_TXQ_ENI(count, 0, MID_DMA_END, bcode));
1040 EN_WRITE(sc, sc->dtq_chip+4, vtophys((vaddr_t)sp));
1041 EN_WRITE(sc, MID_DMA_WRTX, MID_DTQ_A2REG(sc->dtq_chip+8));
1042 cnt = 1000;
1043 while (EN_READ(sc, MID_DMA_RDTX) == MID_DTQ_A2REG(sc->dtq_chip)) {
1044 DELAY(1);
1045 cnt--;
1046 if (cnt == 0) {
1047 aprint_error_dev(&sc->sc_dev, "unexpected timeout in tx DMA test\n");
1048 return(retval); /* timeout, give up */
1049 }
1050 }
1051 EN_WRAPADD(MID_DTQOFF, MID_DTQEND, sc->dtq_chip, 8);
1052 reg = EN_READ(sc, MID_INTACK);
1053 if ((reg & MID_INT_DMA_TX) != MID_INT_DMA_TX) {
1054 aprint_error_dev(&sc->sc_dev, "unexpected status in tx DMA test: 0x%x\n",
1055 reg);
1056 return(retval);
1057 }
1058 EN_WRITE(sc, MID_MAST_CSR, MID_MCSR_ENDMA); /* re-enable DMA (only) */
1059
1060 /* "return to sender..." address is known ... */
1061
1062 if (sc->is_adaptec)
1063 EN_WRITE(sc, sc->drq_chip, MID_MK_RXQ_ADP(lcv, 0, MID_DMA_END, 0));
1064 else
1065 EN_WRITE(sc, sc->drq_chip, MID_MK_RXQ_ENI(count, 0, MID_DMA_END, bcode));
1066 EN_WRITE(sc, sc->drq_chip+4, vtophys((vaddr_t)dp));
1067 EN_WRITE(sc, MID_DMA_WRRX, MID_DRQ_A2REG(sc->drq_chip+8));
1068 cnt = 1000;
1069 while (EN_READ(sc, MID_DMA_RDRX) == MID_DRQ_A2REG(sc->drq_chip)) {
1070 DELAY(1);
1071 cnt--;
1072 if (cnt == 0) {
1073 aprint_error_dev(&sc->sc_dev, "unexpected timeout in rx DMA test\n");
1074 return(retval); /* timeout, give up */
1075 }
1076 }
1077 EN_WRAPADD(MID_DRQOFF, MID_DRQEND, sc->drq_chip, 8);
1078 reg = EN_READ(sc, MID_INTACK);
1079 if ((reg & MID_INT_DMA_RX) != MID_INT_DMA_RX) {
1080 aprint_error_dev(&sc->sc_dev, "unexpected status in rx DMA test: 0x%x\n",
1081 reg);
1082 return(retval);
1083 }
1084 EN_WRITE(sc, MID_MAST_CSR, MID_MCSR_ENDMA); /* re-enable DMA (only) */
1085
1086 if (wmtry) {
1087 return(memcmp(sp, dp, wmtry)); /* wmtry always exits here, no looping */
1088 }
1089
1090 if (memcmp(sp, dp, lcv))
1091 return(retval); /* failed, use last value */
1092
1093 retval = lcv;
1094
1095 }
1096 return(retval); /* studly 64 byte DMA present! oh baby!! */
1097 }
1098
1099 /***********************************************************************/
1100
1101 /*
1102 * en_ioctl: handle ioctl requests
1103 *
1104 * NOTE: if you add an ioctl to set txspeed, you should choose a new
1105 * TX channel/slot. Choose the one with the lowest sc->txslot[slot].nref
1106 * value, subtract one from sc->txslot[0].nref, add one to the
1107 * sc->txslot[slot].nref, set sc->txvc2slot[vci] = slot, and then set
1108 * txspeed[vci].
1109 */
1110
1111 STATIC int en_ioctl(struct ifnet *ifp, EN_IOCTL_CMDT cmd, void *data)
1112 {
1113 #ifdef MISSING_IF_SOFTC
1114 struct en_softc *sc = (struct en_softc *)device_lookup_private(&en_cd, ifp->if_unit);
1115 #else
1116 struct en_softc *sc = (struct en_softc *) ifp->if_softc;
1117 #endif
1118 struct ifaddr *ifa = (struct ifaddr *) data;
1119 struct ifreq *ifr = (struct ifreq *) data;
1120 struct atm_pseudoioctl *api = (struct atm_pseudoioctl *)data;
1121 #ifdef NATM
1122 struct atm_rawioctl *ario = (struct atm_rawioctl *)data;
1123 int slot;
1124 #endif
1125 int s, error = 0;
1126
1127 s = splnet();
1128
1129 switch (cmd) {
1130 case SIOCATMENA: /* enable circuit for recv */
1131 error = en_rxctl(sc, api, 1);
1132 break;
1133
1134 case SIOCATMDIS: /* disable circuit for recv */
1135 error = en_rxctl(sc, api, 0);
1136 break;
1137
1138 #ifdef NATM
1139 case SIOCXRAWATM:
1140 if ((slot = sc->rxvc2slot[ario->npcb->npcb_vci]) == RX_NONE) {
1141 error = EINVAL;
1142 break;
1143 }
1144 if (ario->rawvalue > EN_RXSZ*1024)
1145 ario->rawvalue = EN_RXSZ*1024;
1146 if (ario->rawvalue) {
1147 sc->rxslot[slot].oth_flags |= ENOTHER_RAW;
1148 sc->rxslot[slot].raw_threshold = ario->rawvalue;
1149 } else {
1150 sc->rxslot[slot].oth_flags &= (~ENOTHER_RAW);
1151 sc->rxslot[slot].raw_threshold = 0;
1152 }
1153 #ifdef EN_DEBUG
1154 printf("%s: rxvci%d: turn %s raw (boodi) mode\n",
1155 device_xname(&sc->sc_dev), ario->npcb->npcb_vci,
1156 (ario->rawvalue) ? "on" : "off");
1157 #endif
1158 break;
1159 #endif
1160 case SIOCINITIFADDR:
1161 ifp->if_flags |= IFF_UP;
1162 en_reset(sc);
1163 en_init(sc);
1164 switch (ifa->ifa_addr->sa_family) {
1165 #ifdef INET
1166 case AF_INET:
1167 ifa->ifa_rtrequest = atm_rtrequest; /* ??? */
1168 break;
1169 #endif
1170 #ifdef INET6
1171 case AF_INET6:
1172 ifa->ifa_rtrequest = atm_rtrequest; /* ??? */
1173 break;
1174 #endif
1175 default:
1176 /* what to do if not INET? */
1177 break;
1178 }
1179 break;
1180
1181 case SIOCSIFFLAGS:
1182 if ((error = ifioctl_common(ifp, cmd, data)) != 0)
1183 break;
1184 #ifdef ATM_PVCEXT
1185 /* point-2-point pvc is allowed to change if_flags */
1186 if (((ifp->if_flags & IFF_UP) && !(ifp->if_flags & IFF_RUNNING))
1187 || (!(ifp->if_flags & IFF_UP) && (ifp->if_flags & IFF_RUNNING))) {
1188 en_reset(sc);
1189 en_init(sc);
1190 }
1191 #else
1192 error = EINVAL;
1193 #endif
1194 break;
1195
1196 #if defined(SIOCSIFMTU) /* ??? copied from if_de */
1197 #if !defined(ifr_mtu)
1198 #define ifr_mtu ifr_metric
1199 #endif
1200 case SIOCSIFMTU:
1201 /*
1202 * Set the interface MTU.
1203 */
1204 #ifdef notsure
1205 if (ifr->ifr_mtu > ATMMTU) {
1206 error = EINVAL;
1207 break;
1208 }
1209 #endif
1210 if ((error = ifioctl_common(ifp, cmd, data)) == ENETRESET) {
1211 error = 0;
1212 /* XXXCDC: do we really need to reset on MTU size change? */
1213 en_reset(sc);
1214 en_init(sc);
1215 }
1216 break;
1217 #endif /* SIOCSIFMTU */
1218
1219 #ifdef ATM_PVCEXT
1220 case SIOCADDMULTI:
1221 case SIOCDELMULTI:
1222 if (ifp == &sc->enif || ifr == 0) {
1223 error = EAFNOSUPPORT; /* XXX */
1224 break;
1225 }
1226 switch (ifreq_getaddr(cmd, ifr)->sa_family) {
1227 #ifdef INET
1228 case AF_INET:
1229 break;
1230 #endif
1231 #ifdef INET6
1232 case AF_INET6:
1233 break;
1234 #endif
1235 default:
1236 error = EAFNOSUPPORT;
1237 break;
1238 }
1239 break;
1240
1241 case SIOCGPVCSIF:
1242 if (ifp != &sc->enif) {
1243 #ifdef __NetBSD__
1244 strlcpy(ifr->ifr_name, sc->enif.if_xname,
1245 sizeof(ifr->ifr_name));
1246 #else
1247 snprintf(ifr->ifr_name, sizeof(ifr->ifr_name), "%s%d",
1248 sc->enif.if_name, sc->enif.if_unit);
1249 #endif
1250 }
1251 else
1252 error = EINVAL;
1253 break;
1254
1255 case SIOCSPVCSIF:
1256 if (ifp == &sc->enif) {
1257 struct ifnet *sifp;
1258
1259 if ((error = kauth_authorize_generic(curlwp->l_cred,
1260 KAUTH_GENERIC_ISSUSER, NULL)) != 0)
1261 break;
1262
1263 if ((sifp = en_pvcattach(ifp)) != NULL) {
1264 #ifdef __NetBSD__
1265 strlcpy(ifr->ifr_name, sifp->if_xname,
1266 sizeof(ifr->ifr_name));
1267 #else
1268 snprintf(ifr->ifr_name, sizeof(ifr->ifr_name), "%s%d",
1269 sifp->if_name, sifp->if_unit);
1270 #endif
1271 #if defined(__KAME__) && defined(INET6)
1272 /* get EUI64 for PVC, from ATM hardware interface */
1273 in6_ifattach(sifp, ifp);
1274 #endif
1275 }
1276 else
1277 error = ENOMEM;
1278 }
1279 else
1280 error = EINVAL;
1281 break;
1282
1283 case SIOCGPVCTX:
1284 error = en_pvctxget(sc, (struct pvctxreq *)data);
1285 break;
1286
1287 case SIOCSPVCTX:
1288 if ((error = kauth_authorize_network(curlwp->l_cred,
1289 KAUTH_NETWORK_INTERFACE,
1290 KAUTH_REQ_NETWORK_INTERFACE_SETPRIV, ifp, KAUTH_ARG(cmd),
1291 NULL)) == 0)
1292 error = en_pvctx(sc, (struct pvctxreq *)data);
1293 break;
1294
1295 #endif /* ATM_PVCEXT */
1296
1297 default:
1298 error = ifioctl_common(ifp, cmd, data);
1299 break;
1300 }
1301 splx(s);
1302 return error;
1303 }
1304
1305
1306 /*
1307 * en_rxctl: turn on and off VCs for recv.
1308 */
1309
1310 STATIC int en_rxctl(struct en_softc *sc, struct atm_pseudoioctl *pi, int on)
1311 {
1312 u_int s, vci, flags, slot;
1313 u_int32_t oldmode, newmode;
1314
1315 vci = ATM_PH_VCI(&pi->aph);
1316 flags = ATM_PH_FLAGS(&pi->aph);
1317
1318 #ifdef EN_DEBUG
1319 printf("%s: %s vpi=%d, vci=%d, flags=%d\n", device_xname(&sc->sc_dev),
1320 (on) ? "enable" : "disable", ATM_PH_VPI(&pi->aph), vci, flags);
1321 #endif
1322
1323 if (ATM_PH_VPI(&pi->aph) || vci >= MID_N_VC)
1324 return(EINVAL);
1325
1326 /*
1327 * turn on VCI!
1328 */
1329
1330 if (on) {
1331 if (sc->rxvc2slot[vci] != RX_NONE)
1332 return(EINVAL);
1333 for (slot = 0 ; slot < sc->en_nrx ; slot++)
1334 if (sc->rxslot[slot].oth_flags & ENOTHER_FREE)
1335 break;
1336 if (slot == sc->en_nrx)
1337 return(ENOSPC);
1338 sc->rxvc2slot[vci] = slot;
1339 sc->rxslot[slot].rxhand = NULL;
1340 oldmode = sc->rxslot[slot].mode;
1341 newmode = (flags & ATM_PH_AAL5) ? MIDV_AAL5 : MIDV_NOAAL;
1342 sc->rxslot[slot].mode = MIDV_SETMODE(oldmode, newmode);
1343 sc->rxslot[slot].atm_vci = vci;
1344 sc->rxslot[slot].atm_flags = flags;
1345 sc->rxslot[slot].oth_flags = 0;
1346 sc->rxslot[slot].rxhand = pi->rxhand;
1347 if (sc->rxslot[slot].indma.ifq_head || sc->rxslot[slot].q.ifq_head)
1348 panic("en_rxctl: left over mbufs on enable");
1349 sc->txspeed[vci] = 0; /* full speed to start */
1350 sc->txvc2slot[vci] = 0; /* init value */
1351 sc->txslot[0].nref++; /* bump reference count */
1352 en_loadvc(sc, vci); /* does debug printf for us */
1353 return(0);
1354 }
1355
1356 /*
1357 * turn off VCI
1358 */
1359
1360 if (sc->rxvc2slot[vci] == RX_NONE)
1361 return(EINVAL);
1362 slot = sc->rxvc2slot[vci];
1363 if ((sc->rxslot[slot].oth_flags & (ENOTHER_FREE|ENOTHER_DRAIN)) != 0)
1364 return(EINVAL);
1365 s = splnet(); /* block out enintr() */
1366 oldmode = EN_READ(sc, MID_VC(vci));
1367 newmode = MIDV_SETMODE(oldmode, MIDV_TRASH) & ~MIDV_INSERVICE;
1368 EN_WRITE(sc, MID_VC(vci), (newmode | (oldmode & MIDV_INSERVICE)));
1369 /* halt in tracks, be careful to preserve inserivce bit */
1370 DELAY(27);
1371 sc->rxslot[slot].rxhand = NULL;
1372 sc->rxslot[slot].mode = newmode;
1373
1374 sc->txslot[sc->txvc2slot[vci]].nref--;
1375 sc->txspeed[vci] = 0;
1376 sc->txvc2slot[vci] = 0;
1377
1378 /* if stuff is still going on we are going to have to drain it out */
1379 if (sc->rxslot[slot].indma.ifq_head ||
1380 sc->rxslot[slot].q.ifq_head ||
1381 (sc->rxslot[slot].oth_flags & ENOTHER_SWSL) != 0) {
1382 sc->rxslot[slot].oth_flags |= ENOTHER_DRAIN;
1383 } else {
1384 sc->rxslot[slot].oth_flags = ENOTHER_FREE;
1385 sc->rxslot[slot].atm_vci = RX_NONE;
1386 sc->rxvc2slot[vci] = RX_NONE;
1387 }
1388 splx(s); /* enable enintr() */
1389 #ifdef EN_DEBUG
1390 printf("%s: rx%d: VCI %d is now %s\n", device_xname(&sc->sc_dev), slot, vci,
1391 (sc->rxslot[slot].oth_flags & ENOTHER_DRAIN) ? "draining" : "free");
1392 #endif
1393 return(0);
1394 }
1395
1396 /***********************************************************************/
1397
1398 /*
1399 * en_reset: reset the board, throw away work in progress.
1400 * must en_init to recover.
1401 */
1402
1403 void en_reset(struct en_softc *sc)
1404 {
1405 struct mbuf *m;
1406 int lcv, slot;
1407
1408 #ifdef EN_DEBUG
1409 printf("%s: reset\n", device_xname(&sc->sc_dev));
1410 #endif
1411
1412 if (sc->en_busreset)
1413 sc->en_busreset(sc);
1414 EN_WRITE(sc, MID_RESID, 0x0); /* reset hardware */
1415
1416 /*
1417 * recv: dump any mbufs we are DMA'ing into, if DRAINing, then a reset
1418 * will free us!
1419 */
1420
1421 for (lcv = 0 ; lcv < MID_N_VC ; lcv++) {
1422 if (sc->rxvc2slot[lcv] == RX_NONE)
1423 continue;
1424 slot = sc->rxvc2slot[lcv];
1425 while (1) {
1426 IF_DEQUEUE(&sc->rxslot[slot].indma, m);
1427 if (m == NULL)
1428 break; /* >>> exit 'while(1)' here <<< */
1429 m_freem(m);
1430 }
1431 while (1) {
1432 IF_DEQUEUE(&sc->rxslot[slot].q, m);
1433 if (m == NULL)
1434 break; /* >>> exit 'while(1)' here <<< */
1435 m_freem(m);
1436 }
1437 sc->rxslot[slot].oth_flags &= ~ENOTHER_SWSL;
1438 if (sc->rxslot[slot].oth_flags & ENOTHER_DRAIN) {
1439 sc->rxslot[slot].oth_flags = ENOTHER_FREE;
1440 sc->rxvc2slot[lcv] = RX_NONE;
1441 #ifdef EN_DEBUG
1442 printf("%s: rx%d: VCI %d is now free\n", device_xname(&sc->sc_dev), slot, lcv);
1443 #endif
1444 }
1445 }
1446
1447 /*
1448 * xmit: dump everything
1449 */
1450
1451 for (lcv = 0 ; lcv < EN_NTX ; lcv++) {
1452 while (1) {
1453 IF_DEQUEUE(&sc->txslot[lcv].indma, m);
1454 if (m == NULL)
1455 break; /* >>> exit 'while(1)' here <<< */
1456 m_freem(m);
1457 }
1458 while (1) {
1459 IF_DEQUEUE(&sc->txslot[lcv].q, m);
1460 if (m == NULL)
1461 break; /* >>> exit 'while(1)' here <<< */
1462 m_freem(m);
1463 }
1464 sc->txslot[lcv].mbsize = 0;
1465 }
1466
1467 return;
1468 }
1469
1470
1471 /*
1472 * en_init: init board and sync the card with the data in the softc.
1473 */
1474
1475 STATIC void en_init(struct en_softc *sc)
1476 {
1477 int vc, slot;
1478 u_int32_t loc;
1479 #ifdef ATM_PVCEXT
1480 struct pvcsif *pvcsif;
1481 #endif
1482
1483 if ((sc->enif.if_flags & IFF_UP) == 0) {
1484 #ifdef ATM_PVCEXT
1485 LIST_FOREACH(pvcsif, &sc->sif_list, sif_links) {
1486 if (pvcsif->sif_if.if_flags & IFF_UP) {
1487 /*
1488 * down the device only when there is no active pvc subinterface.
1489 * if there is, we have to go through the init sequence to reflect
1490 * the software states to the device.
1491 */
1492 goto up;
1493 }
1494 }
1495 #endif
1496 #ifdef EN_DEBUG
1497 printf("%s: going down\n", device_xname(&sc->sc_dev));
1498 #endif
1499 en_reset(sc); /* to be safe */
1500 sc->enif.if_flags &= ~IFF_RUNNING; /* disable */
1501 return;
1502 }
1503
1504 #ifdef ATM_PVCEXT
1505 up:
1506 #endif
1507 #ifdef EN_DEBUG
1508 printf("%s: going up\n", device_xname(&sc->sc_dev));
1509 #endif
1510 sc->enif.if_flags |= IFF_RUNNING; /* enable */
1511 #ifdef ATM_PVCEXT
1512 LIST_FOREACH(pvcsif, &sc->sif_list, sif_links) {
1513 pvcsif->sif_if.if_flags |= IFF_RUNNING;
1514 }
1515 #endif
1516
1517 if (sc->en_busreset)
1518 sc->en_busreset(sc);
1519 EN_WRITE(sc, MID_RESID, 0x0); /* reset */
1520
1521 /*
1522 * init obmem data structures: vc tab, DMA q's, slist.
1523 *
1524 * note that we set drq_free/dtq_free to one less than the total number
1525 * of DTQ/DRQs present. we do this because the card uses the condition
1526 * (drq_chip == drq_us) to mean "list is empty"... but if you allow the
1527 * circular list to be completely full then (drq_chip == drq_us) [i.e.
1528 * the drq_us pointer will wrap all the way around]. by restricting
1529 * the number of active requests to (N - 1) we prevent the list from
1530 * becoming completely full. note that the card will sometimes give
1531 * us an interrupt for a DTQ/DRQ we have already processes... this helps
1532 * keep that interrupt from messing us up.
1533 */
1534
1535 for (vc = 0 ; vc < MID_N_VC ; vc++)
1536 en_loadvc(sc, vc);
1537
1538 memset(&sc->drq, 0, sizeof(sc->drq));
1539 sc->drq_free = MID_DRQ_N - 1; /* N - 1 */
1540 sc->drq_chip = MID_DRQ_REG2A(EN_READ(sc, MID_DMA_RDRX));
1541 EN_WRITE(sc, MID_DMA_WRRX, MID_DRQ_A2REG(sc->drq_chip));
1542 /* ensure zero queue */
1543 sc->drq_us = sc->drq_chip;
1544
1545 memset(&sc->dtq, 0, sizeof(sc->dtq));
1546 sc->dtq_free = MID_DTQ_N - 1; /* N - 1 */
1547 sc->dtq_chip = MID_DTQ_REG2A(EN_READ(sc, MID_DMA_RDTX));
1548 EN_WRITE(sc, MID_DMA_WRTX, MID_DRQ_A2REG(sc->dtq_chip));
1549 /* ensure zero queue */
1550 sc->dtq_us = sc->dtq_chip;
1551
1552 sc->hwslistp = MID_SL_REG2A(EN_READ(sc, MID_SERV_WRITE));
1553 sc->swsl_size = sc->swsl_head = sc->swsl_tail = 0;
1554
1555 #ifdef EN_DEBUG
1556 printf("%s: drq free/chip: %d/0x%x, dtq free/chip: %d/0x%x, hwslist: 0x%x\n",
1557 device_xname(&sc->sc_dev), sc->drq_free, sc->drq_chip,
1558 sc->dtq_free, sc->dtq_chip, sc->hwslistp);
1559 #endif
1560
1561 for (slot = 0 ; slot < EN_NTX ; slot++) {
1562 sc->txslot[slot].bfree = EN_TXSZ * 1024;
1563 EN_WRITE(sc, MIDX_READPTR(slot), 0);
1564 EN_WRITE(sc, MIDX_DESCSTART(slot), 0);
1565 loc = sc->txslot[slot].cur = sc->txslot[slot].start;
1566 loc = loc - MID_RAMOFF;
1567 loc = (loc & ~((EN_TXSZ*1024) - 1)) >> 2; /* mask, cvt to words */
1568 loc = loc >> MIDV_LOCTOPSHFT; /* top 11 bits */
1569 EN_WRITE(sc, MIDX_PLACE(slot), MIDX_MKPLACE(en_k2sz(EN_TXSZ), loc));
1570 #ifdef EN_DEBUG
1571 printf("%s: tx%d: place 0x%x\n", device_xname(&sc->sc_dev), slot,
1572 EN_READ(sc, MIDX_PLACE(slot)));
1573 #endif
1574 }
1575
1576 /*
1577 * enable!
1578 */
1579
1580 EN_WRITE(sc, MID_INTENA, MID_INT_TX|MID_INT_DMA_OVR|MID_INT_IDENT|
1581 MID_INT_LERR|MID_INT_DMA_ERR|MID_INT_DMA_RX|MID_INT_DMA_TX|
1582 MID_INT_SERVICE| /* >>> MID_INT_SUNI| XXXCDC<<< */ MID_INT_STATS);
1583 EN_WRITE(sc, MID_MAST_CSR, MID_SETIPL(sc->ipl)|MID_MCSR_ENDMA|
1584 MID_MCSR_ENTX|MID_MCSR_ENRX);
1585
1586 }
1587
1588
1589 /*
1590 * en_loadvc: load a vc tab entry from a slot
1591 */
1592
1593 STATIC void en_loadvc(struct en_softc *sc, int vc)
1594 {
1595 int slot;
1596 u_int32_t reg = EN_READ(sc, MID_VC(vc));
1597
1598 reg = MIDV_SETMODE(reg, MIDV_TRASH);
1599 EN_WRITE(sc, MID_VC(vc), reg);
1600 DELAY(27);
1601
1602 if ((slot = sc->rxvc2slot[vc]) == RX_NONE)
1603 return;
1604
1605 /* no need to set CRC */
1606 EN_WRITE(sc, MID_DST_RP(vc), 0); /* read pointer = 0, desc. start = 0 */
1607 EN_WRITE(sc, MID_WP_ST_CNT(vc), 0); /* write pointer = 0 */
1608 EN_WRITE(sc, MID_VC(vc), sc->rxslot[slot].mode); /* set mode, size, loc */
1609 sc->rxslot[slot].cur = sc->rxslot[slot].start;
1610
1611 #ifdef EN_DEBUG
1612 printf("%s: rx%d: assigned to VCI %d\n", device_xname(&sc->sc_dev), slot, vc);
1613 #endif
1614 }
1615
1616
1617 /*
1618 * en_start: start transmitting the next packet that needs to go out
1619 * if there is one. note that atm_output() has already splnet()'d us.
1620 */
1621
1622 STATIC void en_start(struct ifnet *ifp)
1623 {
1624 #ifdef MISSING_IF_SOFTC
1625 struct en_softc *sc = (struct en_softc *)device_lookup_private(&en_cd, ifp->if_unit);
1626 #else
1627 struct en_softc *sc = (struct en_softc *) ifp->if_softc;
1628 #endif
1629 struct mbuf *m, *lastm, *prev;
1630 struct atm_pseudohdr *ap, *new_ap;
1631 int txchan, mlen, got, need, toadd, cellcnt, first;
1632 u_int32_t atm_vpi, atm_vci, atm_flags, *dat, aal;
1633 u_int8_t *cp;
1634
1635 if ((ifp->if_flags & IFF_RUNNING) == 0)
1636 return;
1637
1638 /*
1639 * remove everything from interface queue since we handle all queueing
1640 * locally ...
1641 */
1642
1643 while (1) {
1644
1645 IFQ_DEQUEUE(&ifp->if_snd, m);
1646 if (m == NULL)
1647 return; /* EMPTY: >>> exit here <<< */
1648
1649 /*
1650 * calculate size of packet (in bytes)
1651 * also, if we are not doing transmit DMA we eliminate all stupid
1652 * (non-word) alignments here using en_mfix(). calls to en_mfix()
1653 * seem to be due to tcp retransmits for the most part.
1654 *
1655 * after this loop mlen total length of mbuf chain (including atm_ph),
1656 * and lastm is a pointer to the last mbuf on the chain.
1657 */
1658
1659 lastm = m;
1660 mlen = 0;
1661 prev = NULL;
1662 while (1) {
1663 /* no DMA? */
1664 if ((!sc->is_adaptec && EN_ENIDMAFIX) || EN_NOTXDMA || !en_dma) {
1665 if ( (mtod(lastm, unsigned long) % sizeof(u_int32_t)) != 0 ||
1666 ((lastm->m_len % sizeof(u_int32_t)) != 0 && lastm->m_next)) {
1667 first = (lastm == m);
1668 if (en_mfix(sc, &lastm, prev) == 0) { /* failed? */
1669 m_freem(m);
1670 m = NULL;
1671 break;
1672 }
1673 if (first)
1674 m = lastm; /* update */
1675 }
1676 prev = lastm;
1677 }
1678 mlen += lastm->m_len;
1679 if (lastm->m_next == NULL)
1680 break;
1681 lastm = lastm->m_next;
1682 }
1683
1684 if (m == NULL) /* happens only if mfix fails */
1685 continue;
1686
1687 ap = mtod(m, struct atm_pseudohdr *);
1688
1689 atm_vpi = ATM_PH_VPI(ap);
1690 atm_vci = ATM_PH_VCI(ap);
1691 atm_flags = ATM_PH_FLAGS(ap) & ~(EN_OBHDR|EN_OBTRL);
1692 aal = ((atm_flags & ATM_PH_AAL5) != 0)
1693 ? MID_TBD_AAL5 : MID_TBD_NOAAL5;
1694
1695 /*
1696 * check that vpi/vci is one we can use
1697 */
1698
1699 if (atm_vpi || atm_vci >= MID_N_VC) {
1700 printf("%s: output vpi=%d, vci=%d out of card range, dropping...\n",
1701 device_xname(&sc->sc_dev), atm_vpi, atm_vci);
1702 m_freem(m);
1703 continue;
1704 }
1705
1706 /*
1707 * computing how much padding we need on the end of the mbuf, then
1708 * see if we can put the TBD at the front of the mbuf where the
1709 * link header goes (well behaved protocols will reserve room for us).
1710 * last, check if room for PDU tail.
1711 *
1712 * got = number of bytes of data we have
1713 * cellcnt = number of cells in this mbuf
1714 * need = number of bytes of data + padding we need (excludes TBD)
1715 * toadd = number of bytes of data we need to add to end of mbuf,
1716 * [including AAL5 PDU, if AAL5]
1717 */
1718
1719 got = mlen - sizeof(struct atm_pseudohdr);
1720 toadd = (aal == MID_TBD_AAL5) ? MID_PDU_SIZE : 0; /* PDU */
1721 cellcnt = (got + toadd + (MID_ATMDATASZ - 1)) / MID_ATMDATASZ;
1722 need = cellcnt * MID_ATMDATASZ;
1723 toadd = need - got; /* recompute, including zero padding */
1724
1725 #ifdef EN_DEBUG
1726 printf("%s: txvci%d: mlen=%d, got=%d, need=%d, toadd=%d, cell#=%d\n",
1727 device_xname(&sc->sc_dev), atm_vci, mlen, got, need, toadd, cellcnt);
1728 printf(" leading_space=%d, trailing_space=%d\n",
1729 M_LEADINGSPACE(m), M_TRAILINGSPACE(lastm));
1730 #endif
1731
1732 #ifdef EN_MBUF_OPT
1733
1734 /*
1735 * note: external storage (M_EXT) can be shared between mbufs
1736 * to avoid copying (see m_copym()). this means that the same
1737 * data buffer could be shared by several mbufs, and thus it isn't
1738 * a good idea to try and write TBDs or PDUs to M_EXT data areas.
1739 */
1740
1741 if (M_LEADINGSPACE(m) >= MID_TBD_SIZE && (m->m_flags & M_EXT) == 0) {
1742 m->m_data -= MID_TBD_SIZE;
1743 m->m_len += MID_TBD_SIZE;
1744 mlen += MID_TBD_SIZE;
1745 new_ap = mtod(m, struct atm_pseudohdr *);
1746 *new_ap = *ap; /* move it back */
1747 ap = new_ap;
1748 dat = ((u_int32_t *) ap) + 1;
1749 /* make sure the TBD is in proper byte order */
1750 *dat++ = htonl(MID_TBD_MK1(aal, sc->txspeed[atm_vci], cellcnt));
1751 *dat = htonl(MID_TBD_MK2(atm_vci, 0, 0));
1752 atm_flags |= EN_OBHDR;
1753 }
1754
1755 if (toadd && (lastm->m_flags & M_EXT) == 0 &&
1756 M_TRAILINGSPACE(lastm) >= toadd) {
1757 cp = mtod(lastm, u_int8_t *) + lastm->m_len;
1758 lastm->m_len += toadd;
1759 mlen += toadd;
1760 if (aal == MID_TBD_AAL5) {
1761 memset(cp, 0, toadd - MID_PDU_SIZE);
1762 dat = (u_int32_t *)(cp + toadd - MID_PDU_SIZE);
1763 /* make sure the PDU is in proper byte order */
1764 *dat = htonl(MID_PDU_MK1(0, 0, got));
1765 } else {
1766 memset(cp, 0, toadd);
1767 }
1768 atm_flags |= EN_OBTRL;
1769 }
1770 ATM_PH_FLAGS(ap) = atm_flags; /* update EN_OBHDR/EN_OBTRL bits */
1771 #endif /* EN_MBUF_OPT */
1772
1773 /*
1774 * get assigned channel (will be zero unless txspeed[atm_vci] is set)
1775 */
1776
1777 txchan = sc->txvc2slot[atm_vci];
1778
1779 if (sc->txslot[txchan].mbsize > EN_TXHIWAT) {
1780 EN_COUNT(sc->txmbovr);
1781 m_freem(m);
1782 #ifdef EN_DEBUG
1783 printf("%s: tx%d: buffer space shortage\n", device_xname(&sc->sc_dev),
1784 txchan);
1785 #endif
1786 continue;
1787 }
1788
1789 sc->txslot[txchan].mbsize += mlen;
1790
1791 #ifdef EN_DEBUG
1792 printf("%s: tx%d: VPI=%d, VCI=%d, FLAGS=0x%x, speed=0x%x\n",
1793 device_xname(&sc->sc_dev), txchan, atm_vpi, atm_vci, atm_flags,
1794 sc->txspeed[atm_vci]);
1795 printf(" adjusted mlen=%d, mbsize=%d\n", mlen,
1796 sc->txslot[txchan].mbsize);
1797 #endif
1798
1799 IF_ENQUEUE(&sc->txslot[txchan].q, m);
1800 en_txdma(sc, txchan);
1801
1802 }
1803 /*NOTREACHED*/
1804 }
1805
1806
1807 /*
1808 * en_mfix: fix a stupid mbuf
1809 */
1810
1811 #ifndef __FreeBSD__
1812
1813 STATIC int en_mfix(struct en_softc *sc, struct mbuf **mm, struct mbuf *prev)
1814 {
1815 struct mbuf *m, *new;
1816 u_char *d, *cp;
1817 int off;
1818 struct mbuf *nxt;
1819
1820 m = *mm;
1821
1822 EN_COUNT(sc->mfix); /* count # of calls */
1823 #ifdef EN_DEBUG
1824 printf("%s: mfix mbuf m_data=%p, m_len=%d\n", device_xname(&sc->sc_dev),
1825 m->m_data, m->m_len);
1826 #endif
1827
1828 d = mtod(m, u_char *);
1829 off = ((unsigned long) d) % sizeof(u_int32_t);
1830
1831 if (off) {
1832 if ((m->m_flags & M_EXT) == 0) {
1833 memmove(d - off, d, m->m_len); /* ALIGN! (with costly data copy...) */
1834 d -= off;
1835 m->m_data = (void *)d;
1836 } else {
1837 /* can't write to an M_EXT mbuf since it may be shared */
1838 MGET(new, M_DONTWAIT, MT_DATA);
1839 if (!new) {
1840 EN_COUNT(sc->mfixfail);
1841 return(0);
1842 }
1843 MCLGET(new, M_DONTWAIT);
1844 if ((new->m_flags & M_EXT) == 0) {
1845 m_free(new);
1846 EN_COUNT(sc->mfixfail);
1847 return(0);
1848 }
1849 memcpy(new->m_data, d, m->m_len); /* ALIGN! (with costly data copy...) */
1850 new->m_len = m->m_len;
1851 new->m_next = m->m_next;
1852 if (prev)
1853 prev->m_next = new;
1854 m_free(m);
1855 *mm = m = new; /* note: 'd' now invalid */
1856 }
1857 }
1858
1859 off = m->m_len % sizeof(u_int32_t);
1860 if (off == 0)
1861 return(1);
1862
1863 d = mtod(m, u_char *) + m->m_len;
1864 off = sizeof(u_int32_t) - off;
1865
1866 nxt = m->m_next;
1867 while (off--) {
1868 for ( ; nxt != NULL && nxt->m_len == 0 ; nxt = nxt->m_next)
1869 /*null*/;
1870 if (nxt == NULL) { /* out of data, zero fill */
1871 *d++ = 0;
1872 continue; /* next "off" */
1873 }
1874 cp = mtod(nxt, u_char *);
1875 *d++ = *cp++;
1876 m->m_len++;
1877 nxt->m_len--;
1878 nxt->m_data = (void *)cp;
1879 }
1880 return(1);
1881 }
1882
1883 #else /* __FreeBSD__ */
1884
1885 STATIC int en_makeexclusive(struct en_softc *, struct mbuf **, struct mbuf *);
1886
1887 STATIC int en_makeexclusive(sc, mm, prev)
1888 struct en_softc *sc;
1889 struct mbuf **mm, *prev;
1890 {
1891 struct mbuf *m, *new;
1892
1893 m = *mm;
1894
1895 if (m->m_flags & M_EXT) {
1896 if (m->m_ext.ext_free) {
1897 /* external buffer isn't an ordinary mbuf cluster! */
1898 aprint_error_dev(&sc->sc_dev, "mfix: special buffer! can't make a copy!\n");
1899 return (0);
1900 }
1901
1902 if (mclrefcnt[mtocl(m->m_ext.ext_buf)] > 1) {
1903 /* make a real copy of the M_EXT mbuf since it is shared */
1904 MGET(new, M_DONTWAIT, MT_DATA);
1905 if (!new) {
1906 EN_COUNT(sc->mfixfail);
1907 return(0);
1908 }
1909 if (m->m_flags & M_PKTHDR)
1910 M_COPY_PKTHDR(new, m);
1911 MCLGET(new, M_DONTWAIT);
1912 if ((new->m_flags & M_EXT) == 0) {
1913 m_free(new);
1914 EN_COUNT(sc->mfixfail);
1915 return(0);
1916 }
1917 memcpy(new->m_data, m->m_data, m->m_len);
1918 new->m_len = m->m_len;
1919 new->m_next = m->m_next;
1920 if (prev)
1921 prev->m_next = new;
1922 m_free(m);
1923 *mm = new;
1924 }
1925 else {
1926 /* the buffer is not shared, align the data offset using
1927 this buffer. */
1928 u_char *d = mtod(m, u_char *);
1929 int off = ((u_long)d) % sizeof(u_int32_t);
1930
1931 if (off > 0) {
1932 memmove(d - off, d, m->m_len);
1933 m->m_data = (void *)d - off;
1934 }
1935 }
1936 }
1937 return (1);
1938 }
1939
1940 STATIC int en_mfix(sc, mm, prev)
1941
1942 struct en_softc *sc;
1943 struct mbuf **mm, *prev;
1944
1945 {
1946 struct mbuf *m;
1947 u_char *d, *cp;
1948 int off;
1949 struct mbuf *nxt;
1950
1951 m = *mm;
1952
1953 EN_COUNT(sc->mfix); /* count # of calls */
1954 #ifdef EN_DEBUG
1955 printf("%s: mfix mbuf m_data=0x%x, m_len=%d\n", device_xname(&sc->sc_dev),
1956 m->m_data, m->m_len);
1957 #endif
1958
1959 d = mtod(m, u_char *);
1960 off = ((unsigned long) d) % sizeof(u_int32_t);
1961
1962 if (off) {
1963 if ((m->m_flags & M_EXT) == 0) {
1964 memmove(d - off, d, m->m_len); /* ALIGN! (with costly data copy...) */
1965 d -= off;
1966 m->m_data = (void *)d;
1967 } else {
1968 /* can't write to an M_EXT mbuf since it may be shared */
1969 if (en_makeexclusive(sc, &m, prev) == 0)
1970 return (0);
1971 *mm = m; /* note: 'd' now invalid */
1972 }
1973 }
1974
1975 off = m->m_len % sizeof(u_int32_t);
1976 if (off == 0)
1977 return(1);
1978
1979 if (m->m_flags & M_EXT) {
1980 /* can't write to an M_EXT mbuf since it may be shared */
1981 if (en_makeexclusive(sc, &m, prev) == 0)
1982 return (0);
1983 *mm = m; /* note: 'd' now invalid */
1984 }
1985
1986 d = mtod(m, u_char *) + m->m_len;
1987 off = sizeof(u_int32_t) - off;
1988
1989 nxt = m->m_next;
1990 while (off--) {
1991 if (nxt != NULL && nxt->m_len == 0) {
1992 /* remove an empty mbuf. this avoids odd byte padding to an empty
1993 last mbuf. */
1994 m->m_next = nxt = m_free(nxt);
1995 }
1996 if (nxt == NULL) { /* out of data, zero fill */
1997 *d++ = 0;
1998 continue; /* next "off" */
1999 }
2000 cp = mtod(nxt, u_char *);
2001 *d++ = *cp++;
2002 m->m_len++;
2003 nxt->m_len--;
2004 nxt->m_data = (void *)cp;
2005 }
2006 if (nxt != NULL && nxt->m_len == 0)
2007 m->m_next = m_free(nxt);
2008 return(1);
2009 }
2010
2011 #endif /* __FreeBSD__ */
2012
2013 /*
2014 * en_txdma: start transmit DMA, if possible
2015 */
2016
2017 STATIC void en_txdma(struct en_softc *sc, int chan)
2018 {
2019 struct mbuf *tmp;
2020 struct atm_pseudohdr *ap;
2021 struct en_launch launch;
2022 int datalen = 0, dtqneed, len, ncells;
2023 u_int8_t *cp;
2024 struct ifnet *ifp;
2025
2026 memset(&launch, 0, sizeof launch); /* XXX gcc */
2027
2028 #ifdef EN_DEBUG
2029 printf("%s: tx%d: starting...\n", device_xname(&sc->sc_dev), chan);
2030 #endif
2031
2032 /*
2033 * note: now that txlaunch handles non-word aligned/sized requests
2034 * the only time you can safely set launch.nodma is if you've en_mfix()'d
2035 * the mbuf chain. this happens only if EN_NOTXDMA || !en_dma.
2036 */
2037
2038 launch.nodma = (EN_NOTXDMA || !en_dma);
2039
2040 again:
2041
2042 /*
2043 * get an mbuf waiting for DMA
2044 */
2045
2046 launch.t = sc->txslot[chan].q.ifq_head; /* peek at head of queue */
2047
2048 if (launch.t == NULL) {
2049 #ifdef EN_DEBUG
2050 printf("%s: tx%d: ...done!\n", device_xname(&sc->sc_dev), chan);
2051 #endif
2052 return; /* >>> exit here if no data waiting for DMA <<< */
2053 }
2054
2055 /*
2056 * get flags, vci
2057 *
2058 * note: launch.need = # bytes we need to get on the card
2059 * dtqneed = # of DTQs we need for this packet
2060 * launch.mlen = # of bytes in in mbuf chain (<= launch.need)
2061 */
2062
2063 ap = mtod(launch.t, struct atm_pseudohdr *);
2064 launch.atm_vci = ATM_PH_VCI(ap);
2065 launch.atm_flags = ATM_PH_FLAGS(ap);
2066 launch.aal = ((launch.atm_flags & ATM_PH_AAL5) != 0) ?
2067 MID_TBD_AAL5 : MID_TBD_NOAAL5;
2068
2069 /*
2070 * XXX: have to recompute the length again, even though we already did
2071 * it in en_start(). might as well compute dtqneed here as well, so
2072 * this isn't that bad.
2073 */
2074
2075 if ((launch.atm_flags & EN_OBHDR) == 0) {
2076 dtqneed = 1; /* header still needs to be added */
2077 launch.need = MID_TBD_SIZE; /* not included with mbuf */
2078 } else {
2079 dtqneed = 0; /* header on-board, DMA with mbuf */
2080 launch.need = 0;
2081 }
2082
2083 launch.mlen = 0;
2084 for (tmp = launch.t ; tmp != NULL ; tmp = tmp->m_next) {
2085 len = tmp->m_len;
2086 launch.mlen += len;
2087 cp = mtod(tmp, u_int8_t *);
2088 if (tmp == launch.t) {
2089 len -= sizeof(struct atm_pseudohdr); /* don't count this! */
2090 cp += sizeof(struct atm_pseudohdr);
2091 }
2092 launch.need += len;
2093 if (len == 0)
2094 continue; /* atm_pseudohdr alone in first mbuf */
2095
2096 dtqneed += en_dqneed(sc, (void *) cp, len, 1);
2097 }
2098
2099 if ((launch.need % sizeof(u_int32_t)) != 0)
2100 dtqneed++; /* need DTQ to FLUSH internal buffer */
2101
2102 if ((launch.atm_flags & EN_OBTRL) == 0) {
2103 if (launch.aal == MID_TBD_AAL5) {
2104 datalen = launch.need - MID_TBD_SIZE;
2105 launch.need += MID_PDU_SIZE; /* AAL5: need PDU tail */
2106 }
2107 dtqneed++; /* need to work on the end a bit */
2108 }
2109
2110 /*
2111 * finish calculation of launch.need (need to figure out how much padding
2112 * we will need). launch.need includes MID_TBD_SIZE, but we need to
2113 * remove that to so we can round off properly. we have to add
2114 * MID_TBD_SIZE back in after calculating ncells.
2115 */
2116
2117 launch.need = roundup(launch.need - MID_TBD_SIZE, MID_ATMDATASZ);
2118 ncells = launch.need / MID_ATMDATASZ;
2119 launch.need += MID_TBD_SIZE;
2120
2121 if (launch.need > EN_TXSZ * 1024) {
2122 printf("%s: tx%d: packet larger than xmit buffer (%d > %d)\n",
2123 device_xname(&sc->sc_dev), chan, launch.need, EN_TXSZ * 1024);
2124 goto dequeue_drop;
2125 }
2126
2127 /*
2128 * note: note that we cannot totally fill the circular buffer (i.e.
2129 * we can't use up all of the remaining sc->txslot[chan].bfree free
2130 * bytes) because that would cause the circular buffer read pointer
2131 * to become equal to the write pointer, thus signaling 'empty buffer'
2132 * to the hardware and stopping the transmitter.
2133 */
2134 if (launch.need >= sc->txslot[chan].bfree) {
2135 EN_COUNT(sc->txoutspace);
2136 #ifdef EN_DEBUG
2137 printf("%s: tx%d: out of transmit space\n", device_xname(&sc->sc_dev), chan);
2138 #endif
2139 return; /* >>> exit here if out of obmem buffer space <<< */
2140 }
2141
2142 /*
2143 * ensure we have enough dtqs to go, if not, wait for more.
2144 */
2145
2146 if (launch.nodma) {
2147 dtqneed = 1;
2148 }
2149 if (dtqneed > sc->dtq_free) {
2150 sc->need_dtqs = 1;
2151 EN_COUNT(sc->txdtqout);
2152 #ifdef EN_DEBUG
2153 printf("%s: tx%d: out of transmit DTQs\n", device_xname(&sc->sc_dev), chan);
2154 #endif
2155 return; /* >>> exit here if out of dtqs <<< */
2156 }
2157
2158 /*
2159 * it is a go, commit! dequeue mbuf start working on the xfer.
2160 */
2161
2162 IF_DEQUEUE(&sc->txslot[chan].q, tmp);
2163 #ifdef EN_DIAG
2164 if (launch.t != tmp)
2165 panic("en dequeue");
2166 #endif /* EN_DIAG */
2167
2168 /*
2169 * launch!
2170 */
2171
2172 EN_COUNT(sc->launch);
2173 #ifdef ATM_PVCEXT
2174 /* if there's a subinterface for this vci, override ifp. */
2175 ifp = en_vci2ifp(sc, launch.atm_vci);
2176 #else
2177 ifp = &sc->enif;
2178 #endif
2179 ifp->if_opackets++;
2180
2181 if ((launch.atm_flags & EN_OBHDR) == 0) {
2182 EN_COUNT(sc->lheader);
2183 /* store tbd1/tbd2 in host byte order */
2184 launch.tbd1 = MID_TBD_MK1(launch.aal, sc->txspeed[launch.atm_vci], ncells);
2185 launch.tbd2 = MID_TBD_MK2(launch.atm_vci, 0, 0);
2186 }
2187 if ((launch.atm_flags & EN_OBTRL) == 0 && launch.aal == MID_TBD_AAL5) {
2188 EN_COUNT(sc->ltail);
2189 launch.pdu1 = MID_PDU_MK1(0, 0, datalen); /* host byte order */
2190 }
2191
2192 en_txlaunch(sc, chan, &launch);
2193
2194 #if NBPFILTER > 0
2195 if (ifp->if_bpf) {
2196 /*
2197 * adjust the top of the mbuf to skip the pseudo atm header
2198 * (and TBD, if present) before passing the packet to bpf,
2199 * restore it afterwards.
2200 */
2201 int size = sizeof(struct atm_pseudohdr);
2202 if (launch.atm_flags & EN_OBHDR)
2203 size += MID_TBD_SIZE;
2204
2205 launch.t->m_data += size;
2206 launch.t->m_len -= size;
2207
2208 BPF_MTAP(ifp, launch.t);
2209
2210 launch.t->m_data -= size;
2211 launch.t->m_len += size;
2212 }
2213 #endif /* NBPFILTER > 0 */
2214 /*
2215 * do some housekeeping and get the next packet
2216 */
2217
2218 sc->txslot[chan].bfree -= launch.need;
2219 IF_ENQUEUE(&sc->txslot[chan].indma, launch.t);
2220 goto again;
2221
2222 /*
2223 * END of txdma loop!
2224 */
2225
2226 /*
2227 * error handles
2228 */
2229
2230 dequeue_drop:
2231 IF_DEQUEUE(&sc->txslot[chan].q, tmp);
2232 if (launch.t != tmp)
2233 panic("en dequeue drop");
2234 m_freem(launch.t);
2235 sc->txslot[chan].mbsize -= launch.mlen;
2236 goto again;
2237 }
2238
2239
2240 /*
2241 * en_txlaunch: launch an mbuf into the DMA pool!
2242 */
2243
2244 STATIC void en_txlaunch(struct en_softc *sc, int chan, struct en_launch *l)
2245 {
2246 struct mbuf *tmp;
2247 u_int32_t cur = sc->txslot[chan].cur,
2248 start = sc->txslot[chan].start,
2249 stop = sc->txslot[chan].stop,
2250 dma, *data, *datastop, count, bcode;
2251 int pad, addtail, need, len, needalign, cnt, end, mx;
2252
2253
2254 /*
2255 * vars:
2256 * need = # bytes card still needs (decr. to zero)
2257 * len = # of bytes left in current mbuf
2258 * cur = our current pointer
2259 * dma = last place we programmed into the DMA
2260 * data = pointer into data area of mbuf that needs to go next
2261 * cnt = # of bytes to transfer in this DTQ
2262 * bcode/count = DMA burst code, and chip's version of cnt
2263 *
2264 * a single buffer can require up to 5 DTQs depending on its size
2265 * and alignment requirements. the 5 possible requests are:
2266 * [1] 1, 2, or 3 byte DMA to align src data pointer to word boundary
2267 * [2] alburst DMA to align src data pointer to bestburstlen
2268 * [3] 1 or more bestburstlen DMAs
2269 * [4] clean up burst (to last word boundary)
2270 * [5] 1, 2, or 3 byte final clean up DMA
2271 */
2272
2273 need = l->need;
2274 dma = cur;
2275 addtail = (l->atm_flags & EN_OBTRL) == 0; /* add a tail? */
2276
2277 #ifdef EN_DIAG
2278 if ((need - MID_TBD_SIZE) % MID_ATMDATASZ)
2279 printf("%s: tx%d: bogus transmit needs (%d)\n", device_xname(&sc->sc_dev), chan,
2280 need);
2281 #endif
2282 #ifdef EN_DEBUG
2283 printf("%s: tx%d: launch mbuf %p! cur=0x%x[%d], need=%d, addtail=%d\n",
2284 device_xname(&sc->sc_dev), chan, l->t, cur, (cur-start)/4, need, addtail);
2285 count = EN_READ(sc, MIDX_PLACE(chan));
2286 printf(" HW: base_address=0x%x, size=%d, read=%d, descstart=%d\n",
2287 MIDX_BASE(count), MIDX_SZ(count), EN_READ(sc, MIDX_READPTR(chan)),
2288 EN_READ(sc, MIDX_DESCSTART(chan)));
2289 #endif
2290
2291 /*
2292 * do we need to insert the TBD by hand?
2293 * note that tbd1/tbd2/pdu1 are in host byte order.
2294 */
2295
2296 if ((l->atm_flags & EN_OBHDR) == 0) {
2297 #ifdef EN_DEBUG
2298 printf("%s: tx%d: insert header 0x%x 0x%x\n", device_xname(&sc->sc_dev),
2299 chan, l->tbd1, l->tbd2);
2300 #endif
2301 EN_WRITE(sc, cur, l->tbd1);
2302 EN_WRAPADD(start, stop, cur, 4);
2303 EN_WRITE(sc, cur, l->tbd2);
2304 EN_WRAPADD(start, stop, cur, 4);
2305 need -= 8;
2306 }
2307
2308 /*
2309 * now do the mbufs...
2310 */
2311
2312 for (tmp = l->t ; tmp != NULL ; tmp = tmp->m_next) {
2313
2314 /* get pointer to data and length */
2315 data = mtod(tmp, u_int32_t *);
2316 len = tmp->m_len;
2317 if (tmp == l->t) {
2318 data += sizeof(struct atm_pseudohdr)/sizeof(u_int32_t);
2319 len -= sizeof(struct atm_pseudohdr);
2320 }
2321
2322 /* now, determine if we should copy it */
2323 if (l->nodma || (len < EN_MINDMA &&
2324 (len % 4) == 0 && ((unsigned long) data % 4) == 0 && (cur % 4) == 0)) {
2325
2326 /*
2327 * roundup len: the only time this will change the value of len
2328 * is when l->nodma is true, tmp is the last mbuf, and there is
2329 * a non-word number of bytes to transmit. in this case it is
2330 * safe to round up because we've en_mfix'd the mbuf (so the first
2331 * byte is word aligned there must be enough free bytes at the end
2332 * to round off to the next word boundary)...
2333 */
2334 len = roundup(len, sizeof(u_int32_t));
2335 datastop = data + (len / sizeof(u_int32_t));
2336 /* copy loop: preserve byte order!!! use WRITEDAT */
2337 while (data != datastop) {
2338 EN_WRITEDAT(sc, cur, *data);
2339 data++;
2340 EN_WRAPADD(start, stop, cur, 4);
2341 }
2342 need -= len;
2343 #ifdef EN_DEBUG
2344 printf("%s: tx%d: copied %d bytes (%d left, cur now 0x%x)\n",
2345 device_xname(&sc->sc_dev), chan, len, need, cur);
2346 #endif
2347 continue; /* continue on to next mbuf */
2348 }
2349
2350 /* going to do DMA, first make sure the dtq is in sync. */
2351 if (dma != cur) {
2352 EN_DTQADD(sc, WORD_IDX(start,cur), chan, MIDDMA_JK, 0, 0, 0);
2353 #ifdef EN_DEBUG
2354 printf("%s: tx%d: dtq_sync: advance pointer to %d\n",
2355 device_xname(&sc->sc_dev), chan, cur);
2356 #endif
2357 }
2358
2359 /*
2360 * if this is the last buffer, and it looks like we are going to need to
2361 * flush the internal buffer, can we extend the length of this mbuf to
2362 * avoid the FLUSH?
2363 */
2364
2365 if (tmp->m_next == NULL) {
2366 cnt = (need - len) % sizeof(u_int32_t);
2367 if (cnt && M_TRAILINGSPACE(tmp) >= cnt)
2368 len += cnt; /* pad for FLUSH */
2369 }
2370
2371 #if !defined(MIDWAY_ENIONLY)
2372
2373 /*
2374 * the adaptec DMA engine is smart and handles everything for us.
2375 */
2376
2377 if (sc->is_adaptec) {
2378 /* need to DMA "len" bytes out to card */
2379 need -= len;
2380 EN_WRAPADD(start, stop, cur, len);
2381 #ifdef EN_DEBUG
2382 printf("%s: tx%d: adp_dma %d bytes (%d left, cur now 0x%x)\n",
2383 device_xname(&sc->sc_dev), chan, len, need, cur);
2384 #endif
2385 end = (need == 0) ? MID_DMA_END : 0;
2386 EN_DTQADD(sc, len, chan, 0, vtophys((vaddr_t)data), l->mlen, end);
2387 if (end)
2388 goto done;
2389 dma = cur; /* update DMA pointer */
2390 continue;
2391 }
2392 #endif /* !MIDWAY_ENIONLY */
2393
2394 #if !defined(MIDWAY_ADPONLY)
2395
2396 /*
2397 * the ENI DMA engine is not so smart and need more help from us
2398 */
2399
2400 /* do we need to do a DMA op to align to word boundary? */
2401 needalign = (unsigned long) data % sizeof(u_int32_t);
2402 if (needalign) {
2403 EN_COUNT(sc->headbyte);
2404 cnt = sizeof(u_int32_t) - needalign;
2405 if (cnt == 2 && len >= cnt) {
2406 count = 1;
2407 bcode = MIDDMA_2BYTE;
2408 } else {
2409 cnt = min(cnt, len); /* prevent overflow */
2410 count = cnt;
2411 bcode = MIDDMA_BYTE;
2412 }
2413 need -= cnt;
2414 EN_WRAPADD(start, stop, cur, cnt);
2415 #ifdef EN_DEBUG
2416 printf("%s: tx%d: small al_dma %d bytes (%d left, cur now 0x%x)\n",
2417 device_xname(&sc->sc_dev), chan, cnt, need, cur);
2418 #endif
2419 len -= cnt;
2420 end = (need == 0) ? MID_DMA_END : 0;
2421 EN_DTQADD(sc, count, chan, bcode, vtophys((vaddr_t)data), l->mlen, end);
2422 if (end)
2423 goto done;
2424 data = (u_int32_t *) ((u_char *)data + cnt);
2425 }
2426
2427 /* do we need to do a DMA op to align? */
2428 if (sc->alburst &&
2429 (needalign = (((unsigned long) data) & sc->bestburstmask)) != 0
2430 && len >= sizeof(u_int32_t)) {
2431 cnt = sc->bestburstlen - needalign;
2432 mx = len & ~(sizeof(u_int32_t)-1); /* don't go past end */
2433 if (cnt > mx) {
2434 cnt = mx;
2435 count = cnt / sizeof(u_int32_t);
2436 bcode = MIDDMA_WORD;
2437 } else {
2438 count = cnt / sizeof(u_int32_t);
2439 bcode = en_dmaplan[count].bcode;
2440 count = cnt >> en_dmaplan[count].divshift;
2441 }
2442 need -= cnt;
2443 EN_WRAPADD(start, stop, cur, cnt);
2444 #ifdef EN_DEBUG
2445 printf("%s: tx%d: al_dma %d bytes (%d left, cur now 0x%x)\n",
2446 device_xname(&sc->sc_dev), chan, cnt, need, cur);
2447 #endif
2448 len -= cnt;
2449 end = (need == 0) ? MID_DMA_END : 0;
2450 EN_DTQADD(sc, count, chan, bcode, vtophys((vaddr_t)data), l->mlen, end);
2451 if (end)
2452 goto done;
2453 data = (u_int32_t *) ((u_char *)data + cnt);
2454 }
2455
2456 /* do we need to do a max-sized burst? */
2457 if (len >= sc->bestburstlen) {
2458 count = len >> sc->bestburstshift;
2459 cnt = count << sc->bestburstshift;
2460 bcode = sc->bestburstcode;
2461 need -= cnt;
2462 EN_WRAPADD(start, stop, cur, cnt);
2463 #ifdef EN_DEBUG
2464 printf("%s: tx%d: best_dma %d bytes (%d left, cur now 0x%x)\n",
2465 device_xname(&sc->sc_dev), chan, cnt, need, cur);
2466 #endif
2467 len -= cnt;
2468 end = (need == 0) ? MID_DMA_END : 0;
2469 EN_DTQADD(sc, count, chan, bcode, vtophys((vaddr_t)data), l->mlen, end);
2470 if (end)
2471 goto done;
2472 data = (u_int32_t *) ((u_char *)data + cnt);
2473 }
2474
2475 /* do we need to do a cleanup burst? */
2476 cnt = len & ~(sizeof(u_int32_t)-1);
2477 if (cnt) {
2478 count = cnt / sizeof(u_int32_t);
2479 bcode = en_dmaplan[count].bcode;
2480 count = cnt >> en_dmaplan[count].divshift;
2481 need -= cnt;
2482 EN_WRAPADD(start, stop, cur, cnt);
2483 #ifdef EN_DEBUG
2484 printf("%s: tx%d: cleanup_dma %d bytes (%d left, cur now 0x%x)\n",
2485 device_xname(&sc->sc_dev), chan, cnt, need, cur);
2486 #endif
2487 len -= cnt;
2488 end = (need == 0) ? MID_DMA_END : 0;
2489 EN_DTQADD(sc, count, chan, bcode, vtophys((vaddr_t)data), l->mlen, end);
2490 if (end)
2491 goto done;
2492 data = (u_int32_t *) ((u_char *)data + cnt);
2493 }
2494
2495 /* any word fragments left? */
2496 if (len) {
2497 EN_COUNT(sc->tailbyte);
2498 if (len == 2) {
2499 count = 1;
2500 bcode = MIDDMA_2BYTE; /* use 2byte mode */
2501 } else {
2502 count = len;
2503 bcode = MIDDMA_BYTE; /* use 1 byte mode */
2504 }
2505 need -= len;
2506 EN_WRAPADD(start, stop, cur, len);
2507 #ifdef EN_DEBUG
2508 printf("%s: tx%d: byte cleanup_dma %d bytes (%d left, cur now 0x%x)\n",
2509 device_xname(&sc->sc_dev), chan, len, need, cur);
2510 #endif
2511 end = (need == 0) ? MID_DMA_END : 0;
2512 EN_DTQADD(sc, count, chan, bcode, vtophys((vaddr_t)data), l->mlen, end);
2513 if (end)
2514 goto done;
2515 }
2516
2517 dma = cur; /* update DMA pointer */
2518 #endif /* !MIDWAY_ADPONLY */
2519
2520 } /* next mbuf, please */
2521
2522 /*
2523 * all mbuf data has been copied out to the obmem (or set up to be DMAd).
2524 * if the trailer or padding needs to be put in, do it now.
2525 *
2526 * NOTE: experimental results reveal the following fact:
2527 * if you DMA "X" bytes to the card, where X is not a multiple of 4,
2528 * then the card will internally buffer the last (X % 4) bytes (in
2529 * hopes of getting (4 - (X % 4)) more bytes to make a complete word).
2530 * it is imporant to make sure we don't leave any important data in
2531 * this internal buffer because it is discarded on the last (end) DTQ.
2532 * one way to do this is to DMA in (4 - (X % 4)) more bytes to flush
2533 * the darn thing out.
2534 */
2535
2536 if (addtail) {
2537
2538 pad = need % sizeof(u_int32_t);
2539 if (pad) {
2540 /*
2541 * FLUSH internal data buffer. pad out with random data from the front
2542 * of the mbuf chain...
2543 */
2544 bcode = (sc->is_adaptec) ? 0 : MIDDMA_BYTE;
2545 EN_COUNT(sc->tailflush);
2546 EN_WRAPADD(start, stop, cur, pad);
2547 EN_DTQADD(sc, pad, chan, bcode, vtophys((vaddr_t)l->t->m_data), 0, 0);
2548 need -= pad;
2549 #ifdef EN_DEBUG
2550 printf("%s: tx%d: pad/FLUSH DMA %d bytes (%d left, cur now 0x%x)\n",
2551 device_xname(&sc->sc_dev), chan, pad, need, cur);
2552 #endif
2553 }
2554
2555 /* copy data */
2556 pad = need / sizeof(u_int32_t); /* round *down* */
2557 if (l->aal == MID_TBD_AAL5)
2558 pad -= 2;
2559 #ifdef EN_DEBUG
2560 printf("%s: tx%d: padding %d bytes (cur now 0x%x)\n",
2561 device_xname(&sc->sc_dev), chan, pad * sizeof(u_int32_t), cur);
2562 #endif
2563 while (pad--) {
2564 EN_WRITEDAT(sc, cur, 0); /* no byte order issues with zero */
2565 EN_WRAPADD(start, stop, cur, 4);
2566 }
2567 if (l->aal == MID_TBD_AAL5) {
2568 EN_WRITE(sc, cur, l->pdu1); /* in host byte order */
2569 EN_WRAPADD(start, stop, cur, 8);
2570 }
2571 }
2572
2573 if (addtail || dma != cur) {
2574 /* write final descriptor */
2575 EN_DTQADD(sc, WORD_IDX(start,cur), chan, MIDDMA_JK, 0,
2576 l->mlen, MID_DMA_END);
2577 /* dma = cur; */ /* not necessary since we are done */
2578 }
2579
2580 done:
2581 /* update current pointer */
2582 sc->txslot[chan].cur = cur;
2583 #ifdef EN_DEBUG
2584 printf("%s: tx%d: DONE! cur now = 0x%x\n",
2585 device_xname(&sc->sc_dev), chan, cur);
2586 #endif
2587
2588 return;
2589 }
2590
2591
2592 /*
2593 * interrupt handler
2594 */
2595
2596 EN_INTR_TYPE en_intr(void *arg)
2597 {
2598 struct en_softc *sc = (struct en_softc *) arg;
2599 struct mbuf *m;
2600 struct atm_pseudohdr ah;
2601 struct ifnet *ifp;
2602 u_int32_t reg, kick, val, mask, chip, vci, slot, dtq, drq;
2603 int lcv, idx, need_softserv = 0;
2604
2605 reg = EN_READ(sc, MID_INTACK);
2606
2607 if ((reg & MID_INT_ANY) == 0)
2608 EN_INTR_RET(0); /* not us */
2609
2610 #ifdef EN_DEBUG
2611 {
2612 char sbuf[256];
2613
2614 snprintb(sbuf, sizeof(sbuf), MID_INTBITS, reg);
2615 printf("%s: interrupt=0x%s\n", device_xname(&sc->sc_dev), sbuf);
2616 }
2617 #endif
2618
2619 /*
2620 * unexpected errors that need a reset
2621 */
2622
2623 if ((reg & (MID_INT_IDENT|MID_INT_LERR|MID_INT_DMA_ERR|MID_INT_SUNI)) != 0) {
2624 char sbuf[256];
2625
2626 snprintb(sbuf, sizeof(sbuf), MID_INTBITS, reg);
2627 printf("%s: unexpected interrupt=0x%s, resetting card\n",
2628 device_xname(&sc->sc_dev), sbuf);
2629 #ifdef EN_DEBUG
2630 #ifdef DDB
2631 #ifdef __FreeBSD__
2632 Debugger("en: unexpected error");
2633 #else
2634 Debugger();
2635 #endif
2636 #endif /* DDB */
2637 sc->enif.if_flags &= ~IFF_RUNNING; /* FREEZE! */
2638 #else
2639 en_reset(sc);
2640 en_init(sc);
2641 #endif
2642 EN_INTR_RET(1); /* for us */
2643 }
2644
2645 /*******************
2646 * xmit interrupts *
2647 ******************/
2648
2649 kick = 0; /* bitmask of channels to kick */
2650 if (reg & MID_INT_TX) { /* TX done! */
2651
2652 /*
2653 * check for tx complete, if detected then this means that some space
2654 * has come free on the card. we must account for it and arrange to
2655 * kick the channel to life (in case it is stalled waiting on the card).
2656 */
2657 for (mask = 1, lcv = 0 ; lcv < EN_NTX ; lcv++, mask = mask * 2) {
2658 if (reg & MID_TXCHAN(lcv)) {
2659 kick = kick | mask; /* want to kick later */
2660 val = EN_READ(sc, MIDX_READPTR(lcv)); /* current read pointer */
2661 val = (val * sizeof(u_int32_t)) + sc->txslot[lcv].start;
2662 /* convert to offset */
2663 if (val > sc->txslot[lcv].cur)
2664 sc->txslot[lcv].bfree = val - sc->txslot[lcv].cur;
2665 else
2666 sc->txslot[lcv].bfree = (val + (EN_TXSZ*1024)) - sc->txslot[lcv].cur;
2667 #ifdef EN_DEBUG
2668 printf("%s: tx%d: transmit done. %d bytes now free in buffer\n",
2669 device_xname(&sc->sc_dev), lcv, sc->txslot[lcv].bfree);
2670 #endif
2671 }
2672 }
2673 }
2674
2675 if (reg & MID_INT_DMA_TX) { /* TX DMA done! */
2676
2677 /*
2678 * check for TX DMA complete, if detected then this means that some DTQs
2679 * are now free. it also means some indma mbufs can be freed.
2680 * if we needed DTQs, kick all channels.
2681 */
2682 val = EN_READ(sc, MID_DMA_RDTX); /* chip's current location */
2683 idx = MID_DTQ_A2REG(sc->dtq_chip);/* where we last saw chip */
2684 if (sc->need_dtqs) {
2685 kick = MID_NTX_CH - 1; /* assume power of 2, kick all! */
2686 sc->need_dtqs = 0; /* recalculated in "kick" loop below */
2687 #ifdef EN_DEBUG
2688 printf("%s: cleared need DTQ condition\n", device_xname(&sc->sc_dev));
2689 #endif
2690 }
2691 while (idx != val) {
2692 sc->dtq_free++;
2693 if ((dtq = sc->dtq[idx]) != 0) {
2694 sc->dtq[idx] = 0; /* don't forget to zero it out when done */
2695 slot = EN_DQ_SLOT(dtq);
2696 IF_DEQUEUE(&sc->txslot[slot].indma, m);
2697 if (!m) panic("enintr: dtqsync");
2698 sc->txslot[slot].mbsize -= EN_DQ_LEN(dtq);
2699 #ifdef EN_DEBUG
2700 printf("%s: tx%d: free %d DMA bytes, mbsize now %d\n",
2701 device_xname(&sc->sc_dev), slot, EN_DQ_LEN(dtq),
2702 sc->txslot[slot].mbsize);
2703 #endif
2704 m_freem(m);
2705 }
2706 EN_WRAPADD(0, MID_DTQ_N, idx, 1);
2707 };
2708 sc->dtq_chip = MID_DTQ_REG2A(val); /* sync softc */
2709 }
2710
2711
2712 /*
2713 * kick xmit channels as needed
2714 */
2715
2716 if (kick) {
2717 #ifdef EN_DEBUG
2718 printf("%s: tx kick mask = 0x%x\n", device_xname(&sc->sc_dev), kick);
2719 #endif
2720 for (mask = 1, lcv = 0 ; lcv < EN_NTX ; lcv++, mask = mask * 2) {
2721 if ((kick & mask) && sc->txslot[lcv].q.ifq_head) {
2722 en_txdma(sc, lcv); /* kick it! */
2723 }
2724 } /* for each slot */
2725 } /* if kick */
2726
2727
2728 /*******************
2729 * recv interrupts *
2730 ******************/
2731
2732 /*
2733 * check for RX DMA complete, and pass the data "upstairs"
2734 */
2735
2736 if (reg & MID_INT_DMA_RX) {
2737 val = EN_READ(sc, MID_DMA_RDRX); /* chip's current location */
2738 idx = MID_DRQ_A2REG(sc->drq_chip);/* where we last saw chip */
2739 while (idx != val) {
2740 sc->drq_free++;
2741 if ((drq = sc->drq[idx]) != 0) {
2742 sc->drq[idx] = 0; /* don't forget to zero it out when done */
2743 slot = EN_DQ_SLOT(drq);
2744 if (EN_DQ_LEN(drq) == 0) { /* "JK" trash DMA? */
2745 m = NULL;
2746 } else {
2747 IF_DEQUEUE(&sc->rxslot[slot].indma, m);
2748 if (!m)
2749 panic("enintr: drqsync: %s: lost mbuf in slot %d!",
2750 device_xname(&sc->sc_dev), slot);
2751 }
2752 /* do something with this mbuf */
2753 if (sc->rxslot[slot].oth_flags & ENOTHER_DRAIN) { /* drain? */
2754 if (m)
2755 m_freem(m);
2756 vci = sc->rxslot[slot].atm_vci;
2757 if (sc->rxslot[slot].indma.ifq_head == NULL &&
2758 sc->rxslot[slot].q.ifq_head == NULL &&
2759 (EN_READ(sc, MID_VC(vci)) & MIDV_INSERVICE) == 0 &&
2760 (sc->rxslot[slot].oth_flags & ENOTHER_SWSL) == 0) {
2761 sc->rxslot[slot].oth_flags = ENOTHER_FREE; /* done drain */
2762 sc->rxslot[slot].atm_vci = RX_NONE;
2763 sc->rxvc2slot[vci] = RX_NONE;
2764 #ifdef EN_DEBUG
2765 printf("%s: rx%d: VCI %d now free\n", device_xname(&sc->sc_dev),
2766 slot, vci);
2767 #endif
2768 }
2769 } else if (m != NULL) {
2770 ATM_PH_FLAGS(&ah) = sc->rxslot[slot].atm_flags;
2771 ATM_PH_VPI(&ah) = 0;
2772 ATM_PH_SETVCI(&ah, sc->rxslot[slot].atm_vci);
2773 #ifdef EN_DEBUG
2774 printf("%s: rx%d: rxvci%d: atm_input, mbuf %p, len %d, hand %p\n",
2775 device_xname(&sc->sc_dev), slot, sc->rxslot[slot].atm_vci, m,
2776 EN_DQ_LEN(drq), sc->rxslot[slot].rxhand);
2777 #endif
2778
2779 #ifdef ATM_PVCEXT
2780 /* if there's a subinterface for this vci, override ifp. */
2781 ifp = en_vci2ifp(sc, sc->rxslot[slot].atm_vci);
2782 ifp->if_ipackets++;
2783 m->m_pkthdr.rcvif = ifp; /* XXX */
2784 #else
2785 ifp = &sc->enif;
2786 ifp->if_ipackets++;
2787 #endif
2788
2789 #if NBPFILTER > 0
2790 if (ifp->if_bpf)
2791 BPF_MTAP(ifp, m);
2792 #endif
2793
2794 atm_input(ifp, &ah, m, sc->rxslot[slot].rxhand);
2795 }
2796
2797 }
2798 EN_WRAPADD(0, MID_DRQ_N, idx, 1);
2799 };
2800 sc->drq_chip = MID_DRQ_REG2A(val); /* sync softc */
2801
2802 if (sc->need_drqs) { /* true if we had a DRQ shortage */
2803 need_softserv = 1;
2804 sc->need_drqs = 0;
2805 #ifdef EN_DEBUG
2806 printf("%s: cleared need DRQ condition\n", device_xname(&sc->sc_dev));
2807 #endif
2808 }
2809 }
2810
2811 /*
2812 * handle service interrupts
2813 */
2814
2815 if (reg & MID_INT_SERVICE) {
2816 chip = MID_SL_REG2A(EN_READ(sc, MID_SERV_WRITE));
2817
2818 while (sc->hwslistp != chip) {
2819
2820 /* fetch and remove it from hardware service list */
2821 vci = EN_READ(sc, sc->hwslistp);
2822 EN_WRAPADD(MID_SLOFF, MID_SLEND, sc->hwslistp, 4);/* advance hw ptr */
2823 slot = sc->rxvc2slot[vci];
2824 if (slot == RX_NONE) {
2825 #ifdef EN_DEBUG
2826 printf("%s: unexpected rx interrupt on VCI %d\n",
2827 device_xname(&sc->sc_dev), vci);
2828 #endif
2829 EN_WRITE(sc, MID_VC(vci), MIDV_TRASH); /* rx off, damn it! */
2830 continue; /* next */
2831 }
2832 EN_WRITE(sc, MID_VC(vci), sc->rxslot[slot].mode); /* remove from hwsl */
2833 EN_COUNT(sc->hwpull);
2834
2835 #ifdef EN_DEBUG
2836 printf("%s: pulled VCI %d off hwslist\n", device_xname(&sc->sc_dev), vci);
2837 #endif
2838
2839 /* add it to the software service list (if needed) */
2840 if ((sc->rxslot[slot].oth_flags & ENOTHER_SWSL) == 0) {
2841 EN_COUNT(sc->swadd);
2842 need_softserv = 1;
2843 sc->rxslot[slot].oth_flags |= ENOTHER_SWSL;
2844 sc->swslist[sc->swsl_tail] = slot;
2845 EN_WRAPADD(0, MID_SL_N, sc->swsl_tail, 1);
2846 sc->swsl_size++;
2847 #ifdef EN_DEBUG
2848 printf("%s: added VCI %d to swslist\n", device_xname(&sc->sc_dev), vci);
2849 #endif
2850 }
2851 };
2852 }
2853
2854 /*
2855 * now service (function too big to include here)
2856 */
2857
2858 if (need_softserv)
2859 en_service(sc);
2860
2861 /*
2862 * keep our stats
2863 */
2864
2865 if (reg & MID_INT_DMA_OVR) {
2866 EN_COUNT(sc->dmaovr);
2867 #ifdef EN_DEBUG
2868 printf("%s: MID_INT_DMA_OVR\n", device_xname(&sc->sc_dev));
2869 #endif
2870 }
2871 reg = EN_READ(sc, MID_STAT);
2872 #ifdef EN_STAT
2873 sc->otrash += MID_OTRASH(reg);
2874 sc->vtrash += MID_VTRASH(reg);
2875 #endif
2876
2877 EN_INTR_RET(1); /* for us */
2878 }
2879
2880
2881 /*
2882 * en_service: handle a service interrupt
2883 *
2884 * Q: why do we need a software service list?
2885 *
2886 * A: if we remove a VCI from the hardware list and we find that we are
2887 * out of DRQs we must defer processing until some DRQs become free.
2888 * so we must remember to look at this RX VCI/slot later, but we can't
2889 * put it back on the hardware service list (since that isn't allowed).
2890 * so we instead save it on the software service list. it would be nice
2891 * if we could peek at the VCI on top of the hwservice list without removing
2892 * it, however this leads to a race condition: if we peek at it and
2893 * decide we are done with it new data could come in before we have a
2894 * chance to remove it from the hwslist. by the time we get it out of
2895 * the list the interrupt for the new data will be lost. oops!
2896 *
2897 */
2898
2899 STATIC void en_service(struct en_softc *sc)
2900 {
2901 struct mbuf *m, *tmp;
2902 u_int32_t cur, dstart, rbd, pdu, *sav, dma, bcode, count, *data, *datastop;
2903 u_int32_t start, stop, cnt, needalign;
2904 int slot, raw, aal5, vci, fill, mlen, tlen, drqneed, need, needfill, end;
2905
2906 aal5 = 0; /* Silence gcc */
2907 next_vci:
2908 if (sc->swsl_size == 0) {
2909 #ifdef EN_DEBUG
2910 printf("%s: en_service done\n", device_xname(&sc->sc_dev));
2911 #endif
2912 return; /* >>> exit here if swsl now empty <<< */
2913 }
2914
2915 /*
2916 * get slot/vci to service
2917 */
2918
2919 slot = sc->swslist[sc->swsl_head];
2920 vci = sc->rxslot[slot].atm_vci;
2921 #ifdef EN_DIAG
2922 if (sc->rxvc2slot[vci] != slot) panic("en_service rx slot/vci sync");
2923 #endif
2924
2925 /*
2926 * determine our mode and if we've got any work to do
2927 */
2928
2929 raw = sc->rxslot[slot].oth_flags & ENOTHER_RAW;
2930 start= sc->rxslot[slot].start;
2931 stop= sc->rxslot[slot].stop;
2932 cur = sc->rxslot[slot].cur;
2933
2934 #ifdef EN_DEBUG
2935 printf("%s: rx%d: service vci=%d raw=%d start/stop/cur=0x%x 0x%x 0x%x\n",
2936 device_xname(&sc->sc_dev), slot, vci, raw, start, stop, cur);
2937 #endif
2938
2939 same_vci:
2940 dstart = MIDV_DSTART(EN_READ(sc, MID_DST_RP(vci)));
2941 dstart = (dstart * sizeof(u_int32_t)) + start;
2942
2943 /* check to see if there is any data at all */
2944 if (dstart == cur) {
2945 defer: /* defer processing */
2946 EN_WRAPADD(0, MID_SL_N, sc->swsl_head, 1);
2947 sc->rxslot[slot].oth_flags &= ~ENOTHER_SWSL;
2948 sc->swsl_size--;
2949 /* >>> remove from swslist <<< */
2950 #ifdef EN_DEBUG
2951 printf("%s: rx%d: remove vci %d from swslist\n",
2952 device_xname(&sc->sc_dev), slot, vci);
2953 #endif
2954 goto next_vci;
2955 }
2956
2957 /*
2958 * figure out how many bytes we need
2959 * [mlen = # bytes to go in mbufs, fill = # bytes to dump (MIDDMA_JK)]
2960 */
2961
2962 if (raw) {
2963
2964 /* raw mode (aka boodi mode) */
2965 fill = 0;
2966 if (dstart > cur)
2967 mlen = dstart - cur;
2968 else
2969 mlen = (dstart + (EN_RXSZ*1024)) - cur;
2970
2971 if (mlen < sc->rxslot[slot].raw_threshold)
2972 goto defer; /* too little data to deal with */
2973
2974 } else {
2975
2976 /* normal mode */
2977 aal5 = (sc->rxslot[slot].atm_flags & ATM_PH_AAL5);
2978 rbd = EN_READ(sc, cur);
2979 if (MID_RBD_ID(rbd) != MID_RBD_STDID)
2980 panic("en_service: id mismatch");
2981
2982 if (rbd & MID_RBD_T) {
2983 mlen = 0; /* we've got trash */
2984 fill = MID_RBD_SIZE;
2985 EN_COUNT(sc->ttrash);
2986 #ifdef EN_DEBUG
2987 printf("RX overflow lost %d cells!\n", MID_RBD_CNT(rbd));
2988 #endif
2989 } else if (!aal5) {
2990 mlen = MID_RBD_SIZE + MID_CHDR_SIZE + MID_ATMDATASZ; /* 1 cell (ick!) */
2991 fill = 0;
2992 } else {
2993 struct ifnet *ifp;
2994
2995 tlen = (MID_RBD_CNT(rbd) * MID_ATMDATASZ) + MID_RBD_SIZE;
2996 pdu = cur + tlen - MID_PDU_SIZE;
2997 if (pdu >= stop)
2998 pdu -= (EN_RXSZ*1024);
2999 pdu = EN_READ(sc, pdu); /* get PDU in correct byte order */
3000 fill = tlen - MID_RBD_SIZE - MID_PDU_LEN(pdu);
3001 if (fill < 0 || (rbd & MID_RBD_CRCERR) != 0) {
3002 static int first = 1;
3003
3004 if (first) {
3005 printf("%s: %s, dropping frame\n", device_xname(&sc->sc_dev),
3006 (rbd & MID_RBD_CRCERR) ?
3007 "CRC error" : "invalid AAL5 PDU length");
3008 printf("%s: got %d cells (%d bytes), AAL5 len is %d bytes (pdu=0x%x)\n",
3009 device_xname(&sc->sc_dev), MID_RBD_CNT(rbd),
3010 tlen - MID_RBD_SIZE, MID_PDU_LEN(pdu), pdu);
3011 #ifndef EN_DEBUG
3012 printf("CRC error report disabled from now on!\n");
3013 first = 0;
3014 #endif
3015 }
3016 fill = tlen;
3017
3018 #ifdef ATM_PVCEXT
3019 ifp = en_vci2ifp(sc, vci);
3020 #else
3021 ifp = &sc->enif;
3022 #endif
3023 ifp->if_ierrors++;
3024
3025 }
3026 mlen = tlen - fill;
3027 }
3028
3029 }
3030
3031 /*
3032 * now allocate mbufs for mlen bytes of data, if out of mbufs, trash all
3033 *
3034 * notes:
3035 * 1. it is possible that we've already allocated an mbuf for this pkt
3036 * but ran out of DRQs, in which case we saved the allocated mbuf on
3037 * "q".
3038 * 2. if we save an mbuf in "q" we store the "cur" (pointer) in the front
3039 * of the mbuf as an identity (that we can check later), and we also
3040 * store drqneed (so we don't have to recompute it).
3041 * 3. after this block of code, if m is still NULL then we ran out of mbufs
3042 */
3043
3044 m = sc->rxslot[slot].q.ifq_head;
3045 drqneed = 1;
3046 if (m) {
3047 sav = mtod(m, u_int32_t *);
3048 if (sav[0] != cur) {
3049 #ifdef EN_DEBUG
3050 printf("%s: rx%d: q'ed mbuf %p not ours\n",
3051 device_xname(&sc->sc_dev), slot, m);
3052 #endif
3053 m = NULL; /* wasn't ours */
3054 EN_COUNT(sc->rxqnotus);
3055 } else {
3056 EN_COUNT(sc->rxqus);
3057 IF_DEQUEUE(&sc->rxslot[slot].q, m);
3058 drqneed = sav[1];
3059 #ifdef EN_DEBUG
3060 printf("%s: rx%d: recovered q'ed mbuf %p (drqneed=%d)\n",
3061 device_xname(&sc->sc_dev), slot, m, drqneed);
3062 #endif
3063 }
3064 }
3065
3066 if (mlen != 0 && m == NULL) {
3067 m = en_mget(sc, mlen, &drqneed); /* allocate! */
3068 if (m == NULL) {
3069 fill += mlen;
3070 mlen = 0;
3071 EN_COUNT(sc->rxmbufout);
3072 #ifdef EN_DEBUG
3073 printf("%s: rx%d: out of mbufs\n", device_xname(&sc->sc_dev), slot);
3074 #endif
3075 }
3076 #ifdef EN_DEBUG
3077 printf("%s: rx%d: allocate mbuf %p, mlen=%d, drqneed=%d\n",
3078 device_xname(&sc->sc_dev), slot, m, mlen, drqneed);
3079 #endif
3080 }
3081
3082 #ifdef EN_DEBUG
3083 printf("%s: rx%d: VCI %d, mbuf_chain %p, mlen %d, fill %d\n",
3084 device_xname(&sc->sc_dev), slot, vci, m, mlen, fill);
3085 #endif
3086
3087 /*
3088 * now check to see if we've got the DRQs needed. if we are out of
3089 * DRQs we must quit (saving our mbuf, if we've got one).
3090 */
3091
3092 needfill = (fill) ? 1 : 0;
3093 if (drqneed + needfill > sc->drq_free) {
3094 sc->need_drqs = 1; /* flag condition */
3095 if (m == NULL) {
3096 EN_COUNT(sc->rxoutboth);
3097 #ifdef EN_DEBUG
3098 printf("%s: rx%d: out of DRQs *and* mbufs!\n", device_xname(&sc->sc_dev), slot);
3099 #endif
3100 return; /* >>> exit here if out of both mbufs and DRQs <<< */
3101 }
3102 sav = mtod(m, u_int32_t *);
3103 sav[0] = cur;
3104 sav[1] = drqneed;
3105 IF_ENQUEUE(&sc->rxslot[slot].q, m);
3106 EN_COUNT(sc->rxdrqout);
3107 #ifdef EN_DEBUG
3108 printf("%s: rx%d: out of DRQs\n", device_xname(&sc->sc_dev), slot);
3109 #endif
3110 return; /* >>> exit here if out of DRQs <<< */
3111 }
3112
3113 /*
3114 * at this point all resources have been allocated and we are commited
3115 * to servicing this slot.
3116 *
3117 * dma = last location we told chip about
3118 * cur = current location
3119 * mlen = space in the mbuf we want
3120 * need = bytes to xfer in (decrs to zero)
3121 * fill = how much fill we need
3122 * tlen = how much data to transfer to this mbuf
3123 * cnt/bcode/count = <same as xmit>
3124 *
3125 * 'needfill' not used after this point
3126 */
3127
3128 dma = cur; /* dma = last location we told chip about */
3129 need = roundup(mlen, sizeof(u_int32_t));
3130 fill = fill - (need - mlen); /* note: may invalidate 'needfill' */
3131
3132 for (tmp = m ; tmp != NULL && need > 0 ; tmp = tmp->m_next) {
3133 tlen = roundup(tmp->m_len, sizeof(u_int32_t)); /* m_len set by en_mget */
3134 data = mtod(tmp, u_int32_t *);
3135
3136 #ifdef EN_DEBUG
3137 printf("%s: rx%d: load mbuf %p, m_len=%d, m_data=%p, tlen=%d\n",
3138 device_xname(&sc->sc_dev), slot, tmp, tmp->m_len, tmp->m_data, tlen);
3139 #endif
3140
3141 /* copy data */
3142 if (EN_NORXDMA || !en_dma || tlen < EN_MINDMA) {
3143 datastop = (u_int32_t *)((u_char *) data + tlen);
3144 /* copy loop: preserve byte order!!! use READDAT */
3145 while (data != datastop) {
3146 *data = EN_READDAT(sc, cur);
3147 data++;
3148 EN_WRAPADD(start, stop, cur, 4);
3149 }
3150 need -= tlen;
3151 #ifdef EN_DEBUG
3152 printf("%s: rx%d: vci%d: copied %d bytes (%d left)\n",
3153 device_xname(&sc->sc_dev), slot, vci, tlen, need);
3154 #endif
3155 continue;
3156 }
3157
3158 /* DMA data (check to see if we need to sync DRQ first) */
3159 if (dma != cur) {
3160 EN_DRQADD(sc, WORD_IDX(start,cur), vci, MIDDMA_JK, 0, 0, 0, 0);
3161 #ifdef EN_DEBUG
3162 printf("%s: rx%d: vci%d: drq_sync: advance pointer to %d\n",
3163 device_xname(&sc->sc_dev), slot, vci, cur);
3164 #endif
3165 }
3166
3167 #if !defined(MIDWAY_ENIONLY)
3168
3169 /*
3170 * the adaptec DMA engine is smart and handles everything for us.
3171 */
3172
3173 if (sc->is_adaptec) {
3174 need -= tlen;
3175 EN_WRAPADD(start, stop, cur, tlen);
3176 #ifdef EN_DEBUG
3177 printf("%s: rx%d: vci%d: adp_dma %d bytes (%d left)\n",
3178 device_xname(&sc->sc_dev), slot, vci, tlen, need);
3179 #endif
3180 end = (need == 0 && !fill) ? MID_DMA_END : 0;
3181 EN_DRQADD(sc, tlen, vci, 0, vtophys((vaddr_t)data), mlen, slot, end);
3182 if (end)
3183 goto done;
3184 dma = cur; /* update DMA pointer */
3185 continue;
3186 }
3187 #endif /* !MIDWAY_ENIONLY */
3188
3189
3190 #if !defined(MIDWAY_ADPONLY)
3191
3192 /*
3193 * the ENI DMA engine is not so smart and need more help from us
3194 */
3195
3196 /* do we need to do a DMA op to align? */
3197 if (sc->alburst &&
3198 (needalign = (((unsigned long) data) & sc->bestburstmask)) != 0) {
3199 cnt = sc->bestburstlen - needalign;
3200 if (cnt > tlen) {
3201 cnt = tlen;
3202 count = cnt / sizeof(u_int32_t);
3203 bcode = MIDDMA_WORD;
3204 } else {
3205 count = cnt / sizeof(u_int32_t);
3206 bcode = en_dmaplan[count].bcode;
3207 count = cnt >> en_dmaplan[count].divshift;
3208 }
3209 need -= cnt;
3210 EN_WRAPADD(start, stop, cur, cnt);
3211 #ifdef EN_DEBUG
3212 printf("%s: rx%d: vci%d: al_dma %d bytes (%d left)\n",
3213 device_xname(&sc->sc_dev), slot, vci, cnt, need);
3214 #endif
3215 tlen -= cnt;
3216 end = (need == 0 && !fill) ? MID_DMA_END : 0;
3217 EN_DRQADD(sc, count, vci, bcode, vtophys((vaddr_t)data), mlen, slot, end);
3218 if (end)
3219 goto done;
3220 data = (u_int32_t *)((u_char *) data + cnt);
3221 }
3222
3223 /* do we need a max-sized burst? */
3224 if (tlen >= sc->bestburstlen) {
3225 count = tlen >> sc->bestburstshift;
3226 cnt = count << sc->bestburstshift;
3227 bcode = sc->bestburstcode;
3228 need -= cnt;
3229 EN_WRAPADD(start, stop, cur, cnt);
3230 #ifdef EN_DEBUG
3231 printf("%s: rx%d: vci%d: best_dma %d bytes (%d left)\n",
3232 device_xname(&sc->sc_dev), slot, vci, cnt, need);
3233 #endif
3234 tlen -= cnt;
3235 end = (need == 0 && !fill) ? MID_DMA_END : 0;
3236 EN_DRQADD(sc, count, vci, bcode, vtophys((vaddr_t)data), mlen, slot, end);
3237 if (end)
3238 goto done;
3239 data = (u_int32_t *)((u_char *) data + cnt);
3240 }
3241
3242 /* do we need to do a cleanup burst? */
3243 if (tlen) {
3244 count = tlen / sizeof(u_int32_t);
3245 bcode = en_dmaplan[count].bcode;
3246 count = tlen >> en_dmaplan[count].divshift;
3247 need -= tlen;
3248 EN_WRAPADD(start, stop, cur, tlen);
3249 #ifdef EN_DEBUG
3250 printf("%s: rx%d: vci%d: cleanup_dma %d bytes (%d left)\n",
3251 device_xname(&sc->sc_dev), slot, vci, tlen, need);
3252 #endif
3253 end = (need == 0 && !fill) ? MID_DMA_END : 0;
3254 EN_DRQADD(sc, count, vci, bcode, vtophys((vaddr_t)data), mlen, slot, end);
3255 if (end)
3256 goto done;
3257 }
3258
3259 dma = cur; /* update DMA pointer */
3260
3261 #endif /* !MIDWAY_ADPONLY */
3262
3263 }
3264
3265 /* skip the end */
3266 if (fill || dma != cur) {
3267 #ifdef EN_DEBUG
3268 if (fill)
3269 printf("%s: rx%d: vci%d: skipping %d bytes of fill\n",
3270 device_xname(&sc->sc_dev), slot, vci, fill);
3271 else
3272 printf("%s: rx%d: vci%d: syncing chip from 0x%x to 0x%x [cur]\n",
3273 device_xname(&sc->sc_dev), slot, vci, dma, cur);
3274 #endif
3275 EN_WRAPADD(start, stop, cur, fill);
3276 EN_DRQADD(sc, WORD_IDX(start,cur), vci, MIDDMA_JK, 0, mlen,
3277 slot, MID_DMA_END);
3278 /* dma = cur; */ /* not necessary since we are done */
3279 }
3280
3281 /*
3282 * done, remove stuff we don't want to pass up:
3283 * raw mode (boodi mode): pass everything up for later processing
3284 * aal5: remove RBD
3285 * aal0: remove RBD + cell header
3286 */
3287
3288 done:
3289 if (m) {
3290 if (!raw) {
3291 cnt = MID_RBD_SIZE;
3292 if (!aal5) cnt += MID_CHDR_SIZE;
3293 m->m_len -= cnt; /* chop! */
3294 m->m_pkthdr.len -= cnt;
3295 m->m_data += cnt;
3296 }
3297 IF_ENQUEUE(&sc->rxslot[slot].indma, m);
3298 }
3299 sc->rxslot[slot].cur = cur; /* update master copy of 'cur' */
3300
3301 #ifdef EN_DEBUG
3302 printf("%s: rx%d: vci%d: DONE! cur now =0x%x\n",
3303 device_xname(&sc->sc_dev), slot, vci, cur);
3304 #endif
3305
3306 goto same_vci; /* get next packet in this slot */
3307 }
3308
3309
3310 #ifdef EN_DDBHOOK
3311 /*
3312 * functions we can call from ddb
3313 */
3314
3315 /*
3316 * en_dump: dump the state
3317 */
3318
3319 #define END_SWSL 0x00000040 /* swsl state */
3320 #define END_DRQ 0x00000020 /* drq state */
3321 #define END_DTQ 0x00000010 /* dtq state */
3322 #define END_RX 0x00000008 /* rx state */
3323 #define END_TX 0x00000004 /* tx state */
3324 #define END_MREGS 0x00000002 /* registers */
3325 #define END_STATS 0x00000001 /* dump stats */
3326
3327 #define END_BITS "\20\7SWSL\6DRQ\5DTQ\4RX\3TX\2MREGS\1STATS"
3328
3329 int en_dump(int unit, int level)
3330 {
3331 struct en_softc *sc;
3332 int lcv, cnt, slot;
3333 u_int32_t ptr, reg;
3334
3335 for (lcv = 0 ; lcv < en_cd.cd_ndevs ; lcv++) {
3336 char sbuf[256];
3337
3338 sc = device_lookup_private(&en_cd, lcv);
3339 if (sc == NULL) continue;
3340 if (unit != -1 && unit != lcv)
3341 continue;
3342
3343 snprintb(sbuf, sizeof(sbuf), END_BITS, level);
3344 printf("dumping device %s at level 0x%s\n", device_xname(&sc->sc_dev), sbuf);
3345
3346 if (sc->dtq_us == 0) {
3347 printf("<hasn't been en_init'd yet>\n");
3348 continue;
3349 }
3350
3351 if (level & END_STATS) {
3352 printf(" en_stats:\n");
3353 printf(" %d mfix (%d failed); %d/%d head/tail byte DMAs, %d flushes\n",
3354 sc->mfix, sc->mfixfail, sc->headbyte, sc->tailbyte, sc->tailflush);
3355 printf(" %d rx DMA overflow interrupts\n", sc->dmaovr);
3356 printf(" %d times we ran out of TX space and stalled\n",
3357 sc->txoutspace);
3358 printf(" %d times we ran out of DTQs\n", sc->txdtqout);
3359 printf(" %d times we launched a packet\n", sc->launch);
3360 printf(" %d times we launched without on-board header\n", sc->lheader);
3361 printf(" %d times we launched without on-board tail\n", sc->ltail);
3362 printf(" %d times we pulled the hw service list\n", sc->hwpull);
3363 printf(" %d times we pushed a vci on the sw service list\n",
3364 sc->swadd);
3365 printf(" %d times RX pulled an mbuf from Q that wasn't ours\n",
3366 sc->rxqnotus);
3367 printf(" %d times RX pulled a good mbuf from Q\n", sc->rxqus);
3368 printf(" %d times we ran out of mbufs *and* DRQs\n", sc->rxoutboth);
3369 printf(" %d times we ran out of DRQs\n", sc->rxdrqout);
3370
3371 printf(" %d transmit packets dropped due to mbsize\n", sc->txmbovr);
3372 printf(" %d cells trashed due to turned off rxvc\n", sc->vtrash);
3373 printf(" %d cells trashed due to totally full buffer\n", sc->otrash);
3374 printf(" %d cells trashed due almost full buffer\n", sc->ttrash);
3375 printf(" %d rx mbuf allocation failures\n", sc->rxmbufout);
3376 #ifdef NATM
3377 printf(" %d drops at natmintrq\n", natmintrq.ifq_drops);
3378 #ifdef NATM_STAT
3379 printf(" natmintr so_rcv: ok/drop cnt: %d/%d, ok/drop bytes: %d/%d\n",
3380 natm_sookcnt, natm_sodropcnt, natm_sookbytes, natm_sodropbytes);
3381 #endif
3382 #endif
3383 }
3384
3385 if (level & END_MREGS) {
3386 char ybuf[256];
3387
3388 printf("mregs:\n");
3389 printf("resid = 0x%x\n", EN_READ(sc, MID_RESID));
3390
3391 snprintb(ybuf, sizeof(ybuf), MID_INTBITS, EN_READ(sc, MID_INTSTAT));
3392 printf("interrupt status = 0x%s\n", ybuf);
3393
3394 snprintb(ybuf, sizeof(ybuf), MID_INTBITS, EN_READ(sc, MID_INTENA));
3395 printf("interrupt enable = 0x%s\n", ybuf);
3396
3397 snprintb(ybuf, sizeof(ybuf), MID_MCSRBITS, EN_READ(sc, MID_MAST_CSR));
3398 printf("mcsr = 0x%s\n", ybuf);
3399
3400 printf("serv_write = [chip=%d] [us=%d]\n", EN_READ(sc, MID_SERV_WRITE),
3401 MID_SL_A2REG(sc->hwslistp));
3402 printf("DMA addr = 0x%x\n", EN_READ(sc, MID_DMA_ADDR));
3403 printf("DRQ: chip[rd=0x%x,wr=0x%x], sc[chip=0x%x,us=0x%x]\n",
3404 MID_DRQ_REG2A(EN_READ(sc, MID_DMA_RDRX)),
3405 MID_DRQ_REG2A(EN_READ(sc, MID_DMA_WRRX)), sc->drq_chip, sc->drq_us);
3406 printf("DTQ: chip[rd=0x%x,wr=0x%x], sc[chip=0x%x,us=0x%x]\n",
3407 MID_DTQ_REG2A(EN_READ(sc, MID_DMA_RDTX)),
3408 MID_DTQ_REG2A(EN_READ(sc, MID_DMA_WRTX)), sc->dtq_chip, sc->dtq_us);
3409
3410 printf(" unusal txspeeds: ");
3411 for (cnt = 0 ; cnt < MID_N_VC ; cnt++)
3412 if (sc->txspeed[cnt])
3413 printf(" vci%d=0x%x", cnt, sc->txspeed[cnt]);
3414 printf("\n");
3415
3416 printf(" rxvc slot mappings: ");
3417 for (cnt = 0 ; cnt < MID_N_VC ; cnt++)
3418 if (sc->rxvc2slot[cnt] != RX_NONE)
3419 printf(" %d->%d", cnt, sc->rxvc2slot[cnt]);
3420 printf("\n");
3421
3422 }
3423
3424 if (level & END_TX) {
3425 printf("tx:\n");
3426 for (slot = 0 ; slot < EN_NTX; slot++) {
3427 printf("tx%d: start/stop/cur=0x%x/0x%x/0x%x [%d] ", slot,
3428 sc->txslot[slot].start, sc->txslot[slot].stop, sc->txslot[slot].cur,
3429 (sc->txslot[slot].cur - sc->txslot[slot].start)/4);
3430 printf("mbsize=%d, bfree=%d\n", sc->txslot[slot].mbsize,
3431 sc->txslot[slot].bfree);
3432 printf("txhw: base_address=0x%lx, size=%d, read=%d, descstart=%d\n",
3433 (u_long)MIDX_BASE(EN_READ(sc, MIDX_PLACE(slot))),
3434 MIDX_SZ(EN_READ(sc, MIDX_PLACE(slot))),
3435 EN_READ(sc, MIDX_READPTR(slot)), EN_READ(sc, MIDX_DESCSTART(slot)));
3436 }
3437 }
3438
3439 if (level & END_RX) {
3440 printf(" recv slots:\n");
3441 for (slot = 0 ; slot < sc->en_nrx; slot++) {
3442 printf("rx%d: vci=%d: start/stop/cur=0x%x/0x%x/0x%x ", slot,
3443 sc->rxslot[slot].atm_vci, sc->rxslot[slot].start,
3444 sc->rxslot[slot].stop, sc->rxslot[slot].cur);
3445 printf("mode=0x%x, atm_flags=0x%x, oth_flags=0x%x\n",
3446 sc->rxslot[slot].mode, sc->rxslot[slot].atm_flags,
3447 sc->rxslot[slot].oth_flags);
3448 printf("RXHW: mode=0x%x, DST_RP=0x%x, WP_ST_CNT=0x%x\n",
3449 EN_READ(sc, MID_VC(sc->rxslot[slot].atm_vci)),
3450 EN_READ(sc, MID_DST_RP(sc->rxslot[slot].atm_vci)),
3451 EN_READ(sc, MID_WP_ST_CNT(sc->rxslot[slot].atm_vci)));
3452 }
3453 }
3454
3455 if (level & END_DTQ) {
3456 printf(" dtq [need_dtqs=%d,dtq_free=%d]:\n",
3457 sc->need_dtqs, sc->dtq_free);
3458 ptr = sc->dtq_chip;
3459 while (ptr != sc->dtq_us) {
3460 reg = EN_READ(sc, ptr);
3461 printf("\t0x%x=[cnt=%d, chan=%d, end=%d, type=%d @ 0x%x]\n",
3462 sc->dtq[MID_DTQ_A2REG(ptr)], MID_DMA_CNT(reg), MID_DMA_TXCHAN(reg),
3463 (reg & MID_DMA_END) != 0, MID_DMA_TYPE(reg), EN_READ(sc, ptr+4));
3464 EN_WRAPADD(MID_DTQOFF, MID_DTQEND, ptr, 8);
3465 }
3466 }
3467
3468 if (level & END_DRQ) {
3469 printf(" drq [need_drqs=%d,drq_free=%d]:\n",
3470 sc->need_drqs, sc->drq_free);
3471 ptr = sc->drq_chip;
3472 while (ptr != sc->drq_us) {
3473 reg = EN_READ(sc, ptr);
3474 printf("\t0x%x=[cnt=%d, chan=%d, end=%d, type=%d @ 0x%x]\n",
3475 sc->drq[MID_DRQ_A2REG(ptr)], MID_DMA_CNT(reg), MID_DMA_RXVCI(reg),
3476 (reg & MID_DMA_END) != 0, MID_DMA_TYPE(reg), EN_READ(sc, ptr+4));
3477 EN_WRAPADD(MID_DRQOFF, MID_DRQEND, ptr, 8);
3478 }
3479 }
3480
3481 if (level & END_SWSL) {
3482 printf(" swslist [size=%d]: ", sc->swsl_size);
3483 for (cnt = sc->swsl_head ; cnt != sc->swsl_tail ;
3484 cnt = (cnt + 1) % MID_SL_N)
3485 printf("0x%x ", sc->swslist[cnt]);
3486 printf("\n");
3487 }
3488 }
3489 return(0);
3490 }
3491
3492 /*
3493 * en_dumpmem: dump the memory
3494 */
3495
3496 int en_dumpmem(int unit, int addr, int len)
3497 {
3498 struct en_softc *sc;
3499 u_int32_t reg;
3500
3501 sc = device_lookup_private(&en_cd, unit);
3502 if (sc == NULL) {
3503 printf("invalid unit number: %d\n", unit);
3504 return(0);
3505 }
3506 addr = addr & ~3;
3507 if (addr < MID_RAMOFF || addr + len*4 > MID_MAXOFF || len <= 0) {
3508 printf("invalid addr/len number: %d, %d\n", addr, len);
3509 return(0);
3510 }
3511 printf("dumping %d words starting at offset 0x%x\n", len, addr);
3512 while (len--) {
3513 reg = EN_READ(sc, addr);
3514 printf("mem[0x%x] = 0x%x\n", addr, reg);
3515 addr += 4;
3516 }
3517 return(0);
3518 }
3519 #endif
3520
3521 #ifdef ATM_PVCEXT
3522 /*
3523 * ATM PVC extension: shaper control and pvc subinterfaces
3524 */
3525
3526 /*
3527 * the list of the interfaces sharing the physical device.
3528 * in order to avoid starvation, the interfaces are scheduled in
3529 * a round-robin fashion when en_start is called from tx complete
3530 * interrupts.
3531 */
3532 static void rrp_add(struct en_softc *sc, struct ifnet *ifp)
3533 {
3534 struct rrp *head, *p, *new;
3535
3536 head = sc->txrrp;
3537 if ((p = head) != NULL) {
3538 while (1) {
3539 if (p->ifp == ifp) {
3540 /* an entry for this ifp already exits */
3541 p->nref++;
3542 return;
3543 }
3544 if (p->next == head)
3545 break;
3546 p = p->next;
3547 }
3548 }
3549
3550 /* create a new entry */
3551 new = malloc(sizeof(struct rrp), M_DEVBUF, M_WAITOK);
3552 if (new == NULL) {
3553 printf("en_rrp_add: malloc failed!\n");
3554 return;
3555 }
3556
3557 new->ifp = ifp;
3558 new->nref = 1;
3559
3560 if (p == NULL) {
3561 /* this is the only one in the list */
3562 new->next = new;
3563 sc->txrrp = new;
3564 }
3565 else {
3566 /* add the new entry at the tail of the list */
3567 new->next = p->next;
3568 p->next = new;
3569 }
3570 }
3571
3572 #if 0 /* not used */
3573 static void rrp_delete(struct en_softc *sc, struct ifnet *ifp)
3574 {
3575 struct rrp *head, *p, *prev;
3576
3577 head = sc->txrrp;
3578
3579 prev = head;
3580 if (prev == NULL) {
3581 printf("rrp_delete: no list!\n");
3582 return;
3583 }
3584 p = prev->next;
3585
3586 while (1) {
3587 if (p->ifp == ifp) {
3588 p->nref--;
3589 if (p->nref > 0)
3590 return;
3591 /* remove this entry */
3592 if (p == prev) {
3593 /* this is the only entry in the list */
3594 sc->txrrp = NULL;
3595 }
3596 else {
3597 prev->next = p->next;
3598 if (head == p)
3599 sc->txrrp = p->next;
3600 }
3601 free(p, M_DEVBUF);
3602 }
3603 prev = p;
3604 p = prev->next;
3605 if (prev == head) {
3606 printf("rrp_delete: no matching entry!\n");
3607 return;
3608 }
3609 }
3610 }
3611 #endif
3612
3613 static struct ifnet *
3614 en_vci2ifp(struct en_softc *sc, int vci)
3615 {
3616 struct pvcsif *pvcsif;
3617
3618 LIST_FOREACH(pvcsif, &sc->sif_list, sif_links) {
3619 if (vci == pvcsif->sif_vci)
3620 return (&pvcsif->sif_if);
3621 }
3622 return (&sc->enif);
3623 }
3624
3625 /*
3626 * create and attach per pvc subinterface
3627 * (currently detach is not supported)
3628 */
3629 static struct ifnet *
3630 en_pvcattach(struct ifnet *ifp)
3631 {
3632 struct en_softc *sc = (struct en_softc *) ifp->if_softc;
3633 struct ifnet *pvc_ifp;
3634 int s;
3635
3636 if ((pvc_ifp = pvcsif_alloc()) == NULL)
3637 return (NULL);
3638
3639 pvc_ifp->if_softc = sc;
3640 pvc_ifp->if_ioctl = en_ioctl;
3641 pvc_ifp->if_start = en_start;
3642 pvc_ifp->if_flags = (IFF_POINTOPOINT|IFF_MULTICAST) |
3643 (ifp->if_flags & (IFF_RUNNING|IFF_SIMPLEX|IFF_NOTRAILERS));
3644
3645 s = splnet();
3646 LIST_INSERT_HEAD(&sc->sif_list, (struct pvcsif *)pvc_ifp, sif_links);
3647 if_attach(pvc_ifp);
3648 atm_ifattach(pvc_ifp);
3649
3650 #ifdef ATM_PVCEXT
3651 rrp_add(sc, pvc_ifp);
3652 #endif
3653 splx(s);
3654
3655 return (pvc_ifp);
3656 }
3657
3658
3659 /* txspeed conversion derived from linux drivers/atm/eni.c
3660 by Werner Almesberger, EPFL LRC */
3661 static const int pre_div[] = { 4,16,128,2048 };
3662
3663 static int en_pcr2txspeed(int pcr)
3664 {
3665 int pre, res, div;
3666
3667 if (pcr == 0 || pcr > 347222)
3668 pre = res = 0; /* max rate */
3669 else {
3670 for (pre = 0; pre < 3; pre++)
3671 if (25000000/pre_div[pre]/64 <= pcr)
3672 break;
3673 div = pre_div[pre]*(pcr);
3674 #if 1
3675 /*
3676 * the shaper value should be rounded down,
3677 * instead of rounded up.
3678 * (which means "res" should be rounded up.)
3679 */
3680 res = (25000000 + div -1)/div - 1;
3681 #else
3682 res = 25000000/div-1;
3683 #endif
3684 if (res < 0)
3685 res = 0;
3686 if (res > 63)
3687 res = 63;
3688 }
3689 return ((pre << 6) + res);
3690 }
3691
3692 static int en_txspeed2pcr(int txspeed)
3693 {
3694 int pre, res, pcr;
3695
3696 pre = (txspeed >> 6) & 0x3;
3697 res = txspeed & 0x3f;
3698 pcr = 25000000 / pre_div[pre] / (res+1);
3699 return (pcr);
3700 }
3701
3702 /*
3703 * en_txctl selects a hardware transmit channel and sets the shaper value.
3704 * en_txctl should be called after enabling the vc by en_rxctl
3705 * since it assumes a transmit channel is already assigned by en_rxctl
3706 * to the vc.
3707 */
3708 static int en_txctl(struct en_softc *sc, int vci, int joint_vci, int pcr)
3709 {
3710 int txspeed, txchan, s;
3711
3712 if (pcr)
3713 txspeed = en_pcr2txspeed(pcr);
3714 else
3715 txspeed = 0;
3716
3717 s = splnet();
3718 txchan = sc->txvc2slot[vci];
3719 sc->txslot[txchan].nref--;
3720
3721 /* select a slot */
3722 if (joint_vci != 0)
3723 /* use the same channel */
3724 txchan = sc->txvc2slot[joint_vci];
3725 else if (pcr == 0)
3726 txchan = 0;
3727 else {
3728 for (txchan = 1; txchan < EN_NTX; txchan++) {
3729 if (sc->txslot[txchan].nref == 0)
3730 break;
3731 }
3732 }
3733 if (txchan == EN_NTX) {
3734 #if 1
3735 /* no free slot! */
3736 splx(s);
3737 return (ENOSPC);
3738 #else
3739 /*
3740 * to allow multiple vc's to share a slot,
3741 * use a slot with the smallest reference count
3742 */
3743 int slot = 1;
3744 txchan = 1;
3745 for (slot = 2; slot < EN_NTX; slot++)
3746 if (sc->txslot[slot].nref < sc->txslot[txchan].nref)
3747 txchan = slot;
3748 #endif
3749 }
3750
3751 sc->txvc2slot[vci] = txchan;
3752 sc->txslot[txchan].nref++;
3753
3754 /* set the shaper parameter */
3755 sc->txspeed[vci] = (u_int8_t)txspeed;
3756
3757 splx(s);
3758 #ifdef EN_DEBUG
3759 printf("VCI:%d PCR set to %d, tx channel %d\n", vci, pcr, txchan);
3760 if (joint_vci != 0)
3761 printf(" slot shared with VCI:%d\n", joint_vci);
3762 #endif
3763 return (0);
3764 }
3765
3766 static int en_pvctx(struct en_softc *sc, struct pvctxreq *pvcreq)
3767 {
3768 struct ifnet *ifp;
3769 struct atm_pseudoioctl api;
3770 struct atm_pseudohdr *pvc_aph, *pvc_joint;
3771 int vci, joint_vci, pcr;
3772 int error = 0;
3773
3774 /* check vpi:vci values */
3775 pvc_aph = &pvcreq->pvc_aph;
3776 pvc_joint = &pvcreq->pvc_joint;
3777
3778 vci = ATM_PH_VCI(pvc_aph);
3779 joint_vci = ATM_PH_VCI(pvc_joint);
3780 pcr = pvcreq->pvc_pcr;
3781
3782 if (ATM_PH_VPI(pvc_aph) != 0 || vci >= MID_N_VC ||
3783 ATM_PH_VPI(pvc_joint) != 0 || joint_vci >= MID_N_VC)
3784 return (EADDRNOTAVAIL);
3785
3786 if ((ifp = ifunit(pvcreq->pvc_ifname)) == NULL)
3787 return (ENXIO);
3788
3789 if (pcr < 0) {
3790 /* negative pcr means disable the vc. */
3791 if (sc->rxvc2slot[vci] == RX_NONE)
3792 /* already disabled */
3793 return 0;
3794
3795 ATM_PH_FLAGS(&api.aph) = 0;
3796 ATM_PH_VPI(&api.aph) = 0;
3797 ATM_PH_SETVCI(&api.aph, vci);
3798 api.rxhand = NULL;
3799
3800 error = en_rxctl(sc, &api, 0);
3801
3802 if (error == 0 && &sc->enif != ifp) {
3803 /* clear vc info of this subinterface */
3804 struct pvcsif *pvcsif = (struct pvcsif *)ifp;
3805
3806 ATM_PH_SETVCI(&api.aph, 0);
3807 pvcsif->sif_aph = api.aph;
3808 pvcsif->sif_vci = 0;
3809 }
3810 return (error);
3811 }
3812
3813 if (&sc->enif == ifp) {
3814 /* called for an en interface */
3815 if (sc->rxvc2slot[vci] == RX_NONE) {
3816 /* vc is not active */
3817 #ifdef __NetBSD__
3818 printf("%s: en_pvctx: rx not active! vci=%d\n",
3819 ifp->if_xname, vci);
3820 #else
3821 printf("%s%d: en_pvctx: rx not active! vci=%d\n",
3822 ifp->if_name, ifp->if_unit, vci);
3823 #endif
3824 return (EINVAL);
3825 }
3826 }
3827 else {
3828 /* called for a pvc subinterface */
3829 struct pvcsif *pvcsif = (struct pvcsif *)ifp;
3830
3831 #ifdef __NetBSD__
3832 strlcpy(pvcreq->pvc_ifname, sc->enif.if_xname,
3833 sizeof(pvcreq->pvc_ifname));
3834 #else
3835 snprintf(pvcreq->pvc_ifname, sizeof(pvcreq->pvc_ifname), "%s%d",
3836 sc->enif.if_name, sc->enif.if_unit);
3837 #endif
3838 ATM_PH_FLAGS(&api.aph) =
3839 (ATM_PH_FLAGS(pvc_aph) & (ATM_PH_AAL5|ATM_PH_LLCSNAP));
3840 ATM_PH_VPI(&api.aph) = 0;
3841 ATM_PH_SETVCI(&api.aph, vci);
3842 api.rxhand = NULL;
3843 pvcsif->sif_aph = api.aph;
3844 pvcsif->sif_vci = ATM_PH_VCI(&api.aph);
3845
3846 if (sc->rxvc2slot[vci] == RX_NONE) {
3847 /* vc is not active, enable rx */
3848 error = en_rxctl(sc, &api, 1);
3849 if (error)
3850 return error;
3851 }
3852 else {
3853 /* vc is already active, update aph in softc */
3854 sc->rxslot[sc->rxvc2slot[vci]].atm_flags =
3855 ATM_PH_FLAGS(&api.aph);
3856 }
3857 }
3858
3859 error = en_txctl(sc, vci, joint_vci, pcr);
3860
3861 if (error == 0) {
3862 if (sc->txspeed[vci] != 0)
3863 pvcreq->pvc_pcr = en_txspeed2pcr(sc->txspeed[vci]);
3864 else
3865 pvcreq->pvc_pcr = 0;
3866 }
3867
3868 return error;
3869 }
3870
3871 static int en_pvctxget(struct en_softc *sc, struct pvctxreq *pvcreq)
3872 {
3873 struct pvcsif *pvcsif;
3874 struct ifnet *ifp;
3875 int vci, slot;
3876
3877 if ((ifp = ifunit(pvcreq->pvc_ifname)) == NULL)
3878 return (ENXIO);
3879
3880 if (ifp == &sc->enif) {
3881 /* physical interface: assume vci is specified */
3882 struct atm_pseudohdr *pvc_aph;
3883
3884 pvc_aph = &pvcreq->pvc_aph;
3885 vci = ATM_PH_VCI(pvc_aph);
3886 if ((slot = sc->rxvc2slot[vci]) == RX_NONE)
3887 ATM_PH_FLAGS(pvc_aph) = 0;
3888 else
3889 ATM_PH_FLAGS(pvc_aph) = sc->rxslot[slot].atm_flags;
3890 ATM_PH_VPI(pvc_aph) = 0;
3891 }
3892 else {
3893 /* pvc subinterface */
3894 #ifdef __NetBSD__
3895 strlcpy(pvcreq->pvc_ifname, sc->enif.if_xname,
3896 sizeof(pvcreq->pvc_ifname));
3897 #else
3898 snprintf(pvcreq->pvc_ifname, sizeof(pvcreq->pvc_ifname), "%s%d",
3899 sc->enif.if_name, sc->enif.if_unit);
3900 #endif
3901
3902 pvcsif = (struct pvcsif *)ifp;
3903 pvcreq->pvc_aph = pvcsif->sif_aph;
3904 vci = pvcsif->sif_vci;
3905 }
3906
3907 if ((slot = sc->rxvc2slot[vci]) == RX_NONE) {
3908 /* vc is not active */
3909 ATM_PH_FLAGS(&pvcreq->pvc_aph) = 0;
3910 pvcreq->pvc_pcr = -1;
3911 }
3912 else if (sc->txspeed[vci])
3913 pvcreq->pvc_pcr = en_txspeed2pcr(sc->txspeed[vci]);
3914 else
3915 pvcreq->pvc_pcr = 0;
3916
3917 return (0);
3918 }
3919
3920 #endif /* ATM_PVCEXT */
3921
3922 #endif /* NEN > 0 || !defined(__FreeBSD__) */
NetBSD on the FriendlyARM MINI2440