1 /* $NetBSD: mtd803reg.h,v 1.2 2006/03/07 18:15:28 wiz Exp $ */
4 * Copyright (c) 2002 The NetBSD Foundation, Inc.
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Peter Bex <Peter.Bex@student.kun.nl>.
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
32 /* Command and Status Register */
33 #define MTD_PAR0 0x00 /* Physical address 0-3 */
34 #define MTD_PAR1 0x04 /* Physical address 4-5 */
35 #define MTD_MAR0 0x08 /* Multicast address 0-3 */
36 #define MTD_MAR1 0x0c /* Multicast address 4-7 */
37 #define MTD_FAR0 0x10 /* Flowctrl address 0-3 */
38 #define MTD_FAR1 0x14 /* Flowctrl address 4-5 */
39 #define MTD_RXTXR 0x18 /* Receive-transmit config */
40 #define MTD_BCR 0x1c /* Bus command */
41 #define MTD_TXPDR 0x20 /* Transmit polling demand */
42 #define MTD_RXPDR 0x24 /* Receive polling demand */
43 #define MTD_RCWP 0x28 /* Receive word pointer */
44 #define MTD_TXLBA 0x2c /* Transmit list base addr */
45 #define MTD_RXLBA 0x30 /* Receive list base addr */
46 #define MTD_ISR 0x34 /* Interrupt Status Register */
47 #define MTD_IMR 0x38 /* Interrupt Mask Register */
48 #define MTD_FHLT 0x3c /* Flow ctrl high/low thresh */
49 #define MTD_MIIMGT 0x40 /* ROM and MII management */
50 #define MTD_TALLY 0x44 /* Tally ctr for CRC & MPA */
51 #define MTD_TSR 0x48 /* Tally ctr for TSR */
52 #define MTD_PHYBASE 0x4c /* PHY status & control */
53 #define MTD_OUI 0x50 /* OUI register */
54 #define MTD_LPAR 0x54 /* Link Partner, Advertisement */
55 #define MTD_WUECSR 0x5c /* Wake-up Events CSR */
57 #define MTD_ALL_ADDR 0xffffffff /* Mask all addresses */
58 #define MTD_TXPDR_DEMAND 0xffffffff /* Demand transmit polling */
59 #define MTD_RXPDR_DEMAND 0xffffffff /* Demand receive polling */
62 /* Basic mode control register */
63 #define MTD_PHY_BMCR 0x00
65 /* Bus Command Register */
66 #define MTD_BCR_RSRVD1 0xfffffc00 /* Bits [31:10] are reserved */
67 #define MTD_BCR_PROG 0x00000200 /* Programming */
68 #define MTD_BCR_RLE 0x00000100 /* Read Line command Enable */
69 #define MTD_BCR_RME 0x00000080 /* Read Multiple cmd Enable */
70 #define MTD_BCR_WIE 0x00000040 /* Write and Inval. cmd Enab. */
71 #define MTD_BCR_BLEN1 0x00000000 /* 1 dword burst length */
72 #define MTD_BCR_BLEN4 0x00000008 /* 4 dwords burst length */
73 #define MTD_BCR_BLEN8 0x00000010 /* 8 dwords burst length */
74 #define MTD_BCR_BLEN16 0x00000018 /* 16 dwords burst length */
75 #define MTD_BCR_BLEN32 0x00000020 /* 32 dwords burst length */
76 #define MTD_BCR_BLEN64 0x00000028 /* 64 dwords burst length */
77 #define MTD_BCR_BLEN128 0x00000030 /* 128 dwords burst length */
78 #define MTD_BCR_BLEN512 0x00000038 /* 512 dwords burst length */
79 #define MTD_BCR_RSVRD0 0x00000006 /* Bits [2:1] are reserved */
80 #define MTD_BCR_RESET 0x00000001 /* Software reset */
82 #define MTD_TIMEOUT 1000 /* Timeout when resetting */
84 /* Transmit configuration register */
85 #define MTD_TX_RUN 0x80000000 /* Transmit running status */
86 #define MTD_TX_RSRVD1 0x60000000 /* Bits [14:13] are reserved */
87 #define MTD_TX_BACKOPT 0x10000000 /* Optional backoff */
88 #define MTD_TX_FASTBACK 0x08000000 /* Fast back-off */
89 #define MTD_TX_RSRVD0 0x04000000 /* Bit 10 is reserved */
90 #define MTD_TX_ENH 0x02000000 /* Enhanced mode */
91 #define MTD_TX_FCTL 0x01000000 /* Transmit fctl packet enable*/
92 #define MTD_TX_64 0x00000000 /* 64 bytes */
93 #define MTD_TX_32 0x00200000 /* 32 bytes */
94 #define MTD_TX_128 0x00400000 /* 128 bytes */
95 #define MTD_TX_256 0x00600000 /* 256 bytes */
96 #define MTD_TX_512 0x00800000 /* 512 bytes */
97 #define MTD_TX_768 0x00a00000 /* 768 bytes */
98 #define MTD_TX_1024 0x00c00000 /* 1024 bytes */
99 #define MTD_TX_STFWD 0x00e00000 /* Store and forward */
100 #define MTD_TX_FDPLX 0x00100000 /* Full duplex mode */
101 #define MTD_TX_SPD10 0x00080000 /* Port speed is 10M */
102 #define MTD_TX_ENABLE 0x00040000 /* Transmit enable */
103 #define MTD_TX_LPBACK 0x00020000 /* Loopback mode bit 1 */
104 #define MTD_TX_LPBACKZERO 0x00010000 /* Loopback mode bit 0 */
106 /* Receive configuration register */
107 #define MTD_RX_RUN 0x00008000 /* Receive running status */
108 #define MTD_RX_EARLY 0x00004000 /* Early interrupt enable */
109 #define MTD_RX_FCTL 0x00002000 /* Receive fctl packet enable */
110 #define MTD_RX_FANA 0x00001000 /* Fctl address undefined(n/a)*/
111 #define MTD_RX_BLEN 0x00000800 /* Receive burst len enable */
112 #define MTD_RX_512 0x00000700 /* 512 words */
113 #define MTD_RX_128 0x00000600 /* 128 words */
114 #define MTD_RX_64 0x00000500 /* 64 words */
115 #define MTD_RX_32 0x00000400 /* 32 words */
116 #define MTD_RX_16 0x00000300 /* 16 words */
117 #define MTD_RX_8 0x00000200 /* 8 words */
118 #define MTD_RX_4 0x00000100 /* 4 words */
119 #define MTD_RX_1 0x00000000 /* 1 word */
120 #define MTD_RX_PROM 0x00000080 /* Promiscuous mode */
121 #define MTD_RX_ABROAD 0x00000040 /* Accept broadcast */
122 #define MTD_RX_AMULTI 0x00000020 /* Accept multicast */
123 #define MTD_RX_ARP 0x00000008 /* Receive runt packet */
124 #define MTD_RX_ALP 0x00000004 /* Receive long packet */
125 #define MTD_RX_ERRP 0x00000002 /* Receive error packet */
126 #define MTD_RX_ENABLE 0x00000001 /* Receive enable */
128 /* Interrupt Status Register */
129 #define MTD_ISR_RSRVD1 0xfff80000 /* Bits [31:19] are reserved */
130 #define MTD_ISR_PDF 0x00040000 /* Parallel Detection Fault */
131 #define MTD_ISR_RFCON 0x00020000 /* Receive FCtl xON packet */
132 #define MRD_ISR_RFCOFF 0x00010000 /* Receive FCtl xOFF packet */
133 #define MTD_ISR_LSC 0x00008000 /* Link Status Change */
134 #define MTD_ISR_ANC 0x00004000 /* Autonegotiation complete */
135 #define MTD_ISR_FBUSERR 0x00002000 /* Fatal bus error */
136 #define MTD_ISR_PARERR 0x00000000 /* Parity error */
137 #define MTD_ISR_MASTERR 0x00000800 /* Master error */
138 #define MTD_ISR_TARERR 0x00001000 /* Target error */
139 #define MTD_ISR_TXUNDER 0x00000400 /* Transmit underflow */
140 #define MTD_ISR_RXOVER 0x00000200 /* Receive overflow */
141 #define MTD_ISR_TXEARLY 0x00000100 /* Transmit early int */
142 #define MTD_ISR_RXEARLY 0x00000080 /* Receive early int */
143 #define MTD_ISR_CTROVER 0x00000040 /* Counter overflow */
144 #define MTD_ISR_RXBUN 0x00000020 /* Receive buffer n/a */
145 #define MTD_ISR_TXBUN 0x00000010 /* Transmit buffer n/a */
146 #define MTD_ISR_TXIRQ 0x00000008 /* Transmit interrupt */
147 #define MTD_ISR_RXIRQ 0x00000004 /* Receive interrupt */
148 #define MTD_ISR_RXERR 0x00000002 /* Receive error */
149 #define MTD_ISR_RSRVD0 0x00000001 /* Bit 1 is reserved */
151 #define MTD_ISR_MASK MTD_ISR_TXIRQ | MTD_ISR_RXIRQ | MTD_ISR_RXBUN \
152 | MTD_ISR_RXERR | MTD_ISR_PDF \
153 | MTD_ISR_FBUSERR | MTD_ISR_TXUNDER \
154 | MTD_ISR_RXOVER | MTD_ISR_PARERR \
155 | MTD_ISR_MASTERR | MTD_ISR_TARERR
157 #define MTD_ISR_ENABLE 0xffffffff /* Enable interrupts */
159 /* Interrupt Mask Register. Essentially the same as ISR */
160 #define MTD_IMR_RSRVD2 0xfff80000 /* Bits [31:19] are reserved */
161 #define MTD_IMR_PDF 0x00040000 /* Parallel Detection Fault */
162 #define MTD_IMR_RFCON 0x00020000 /* Receive FCtl xON packet */
163 #define MRD_IMR_RFCOFF 0x00010000 /* Receive FCtl xOFF packet */
164 #define MTD_IMR_LSC 0x00008000 /* Link Status Change */
165 #define MTD_IMR_ANC 0x00004000 /* Autonegotiation complete */
166 #define MTD_IMR_FBUSERR 0x00002000 /* Fatal bus error */
167 #define MTD_IMR_RSRVD1 0x00001800 /* Bits [12:11] are reserved */
168 #define MTD_IMR_TXUNDER 0x00000400 /* Transmit underflow */
169 #define MTD_IMR_RXOVER 0x00000200 /* Receive overflow */
170 #define MTD_IMR_TXEARLY 0x00000100 /* Transmit early int */
171 #define MTD_IMR_RXEARLY 0x00000080 /* Receive early int */
172 #define MTD_IMR_CTROVER 0x00000040 /* Counter overflow */
173 #define MTD_IMR_RXBUN 0x00000020 /* Receive buffer n/a */
174 #define MTD_IMR_TXBUN 0x00000010 /* Transmit buffer n/a */
175 #define MTD_IMR_TXIRQ 0x00000008 /* Transmit interrupt */
176 #define MTD_IMR_RXIRQ 0x00000004 /* Receive interrupt */
177 #define MTD_IMR_RXERR 0x00000002 /* Receive error */
178 #define MTD_IMR_RSRVD0 0x00000001 /* Bit 1 is reserved */
180 #define MTD_IMR_MASK MTD_IMR_TXIRQ | MTD_IMR_RXIRQ | MTD_IMR_RXBUN \
181 | MTD_IMR_RXERR | MTD_IMR_PDF \
182 | MTD_IMR_FBUSERR | MTD_IMR_TXUNDER \
185 /* Tally counters for CRC and MPA */
186 #define MTD_TALLY_CRCOVER 0x80000000 /* CRC tally ctr overflow */
187 #define MTD_TALLY_NCRCERR 0x7fff0000 /* Number of CRC errors */
188 #define MTD_TALLY_MPAOVER 0x00008000 /* MPA tally ctr overflow */
189 #define MTD_TALLY_NMPAERR 0x00007fff /* Number of MPA errors */
191 /* Tally counters for Transmit Status Report */
192 #define MTD_TSR_NABORT 0xff000000 /* Number of aborted packets */
193 #define MTD_TSR_NLCOL 0x00ff0000 /* Number of late collisions */
194 #define MTD_TSR_NRETRY 0x0000ffff /* Number of transm. retries */
196 /* Wake-Up Events Control and Status Register */
197 #define MTD_WUECSR_RSRVD1 0xfffff000 /* Bits [31:12] are reserved */
198 #define MTD_WUECSR_FRCWKUP 0x00000800 /* Force Wake Up LAN mode */
199 #define MTD_WUECSR_STATCHG 0x00000400 /* Status Change enable */
200 #define MTD_WUECSR_AGU 0x00000200 /* Accept Global Unicast */
201 #define MTD_WUECSR_WUPOP 0x00000100 /* Wake Up Pin Output Pattern */
202 #define MTD_WUECSR_WUPPROP 0x00000080 /* Wake Up Pin Property */
203 #define MTD_WUECSR_LCD 0x00000040 /* Link Change Detected */
204 #define MTD_WUECSR_MPR 0x00000020 /* Magic Packet Received */
205 #define MTD_WUECSR_WUFR 0x00000010 /* Wake Up Frame Received */
206 #define MTD_WUECSR_RSRVD0 0x00000008 /* Unspecified! */
207 #define MTD_WUECSR_LCE 0x00000004 /* Link Change Enable */
208 #define MTD_WUECSR_MPE 0x00000002 /* Magic Packet Enable */
209 #define MTD_WUECSR_WUFE 0x00000001 /* Wake Up Frame Enable */
213 * Note: We should probably move the following info to a new PHY driver.
214 * Or maybe remove them anyway, but we might need them someday so leave them
217 /* PHY Control and Status Register */
218 #define MTD_PHY_T4 0x80000000 /* T4 operation capability */
219 #define MTD_PHY_TXFD 0x40000000 /* 100-TX Full Duplex cap. */
220 #define MTD_PHY_TXHD 0x20000000 /* 100-TX Half Duplex cap. */
221 #define MTD_PHY_TPFD 0x10000000 /* 10-TP Full Duplex cap. */
222 #define MTD_PHY_TPHD 0x08000000 /* 10-TP Half Duplex cap. */
223 #define MTD_PHY_RSRVD2 0x07c00000 /* Bits [16:22] are reserved */
224 #define MTD_PHY_ANC 0x00200000 /* Autonegotiation complete */
225 #define MTD_PHY_RMTFAULT 0x00100000 /* Remote fault */
226 #define MTD_PHY_AUTONEG 0x00080000 /* Autonegotiation */
227 #define MTD_PHY_LINK 0x00040000 /* Link status */
228 #define MTD_PHY_JABBER 0x00020000 /* Jabber detected */
229 #define MTD_PHY_EXTREG 0x00010000 /* Extended register exists */
230 #define MTD_PHY_RESET 0x00008000 /* Reset PHY registers */
231 #define MTD_PHY_LPBACK 0x00004000 /* Loopback select */
232 #define MTD_PHY_SPEED 0x00002000 /* Speed select */
233 #define MTD_PHY_ANEN 0x00001000 /* Autoneg enable */
234 #define MTD_PHY_POWDWN 0x00000800 /* Power-down */
235 #define MTD_PHY_RSRVD1 0x00000400 /* Bit 10 is reserved */
236 #define MTD_PHY_RESTAN 0x00000200 /* Restart Autoneg */
237 #define MTD_PHY_DUPLEX 0x00000100 /* Duplex select */
238 #define MTD_PHY_COLTST 0x00000080 /* Collision test enable */
239 #define MTD_PHY_RSRVD0 0x0000007f /* Bits [6:0] are reserved */
242 #define MTD_OUI_HIGH 0xfc000000 /* OUI High register (0x34) */
243 #define MTD_OUI_PARTNO 0x02f00000 /* Part number (0x0) */
244 #define MTD_OUI_REVISION 0x000f0000 /* Revision number (0x0) */
245 #define MTD_OUI_LOW 0x0000ffff /* OUI Low register (0x0302) */
247 /* Link Partner Ability Register and Advertisement Register */
248 #define MTD_LPAR_LP_NEXTPAGE 0x80000000 /* Next page */
249 #define MTD_LPAR_LP_ACK 0x40000000 /* Acknowledge */
250 #define MTD_LPAR_LP_RMTFAULT 0x20000000 /* Remote fault detected */
251 #define MTD_LPAR_RSRVD1 0x1c000000 /* Bits [28:26] are reserved */
252 #define MTD_LPAR_LP_T4 0x02000000 /* Capable of T4 operation */
253 #define MTD_LPAR_LP_TXFD 0x01000000 /* Cap. of 100-TX Full Duplex */
254 #define MTD_LPAR_LP_TXHD 0x00800000 /* Cap. of 100-TX Half Duplex */
255 #define MTD_LPAR_LP_TPFD 0x00400000 /* Cap. of 10-TP Full Duplex */
256 #define MTD_LPAR_LP_TPHD 0x00200000 /* Cap. of 10-TP Half Duplex */
257 #define MTD_LPAR_SELECTOR1 0x001f0000 /* Selector field 1 */
258 #define MTD_LPAR_AD_NEXTPAGE 0x00008000 /* Next page */
259 #define MTD_LPAR_AD_ACK 0x00004000 /* Acknowledge */
260 #define MTD_LPAR_AD_RMTFAULT 0x00002000 /* Remote fault detected */
261 #define MTD_LPAR_RSRVD0 0x00001c00 /* Bits [12:10] are reserved */
262 #define MTD_LPAR_AD_T4 0x00000200 /* Capable of T4 operation */
263 #define MTD_LPAR_AD_TXFD 0x00000100 /* Cap. of 100-TX Full Duplex */
264 #define MTD_LPAR_AD_TXHD 0x00000080 /* Cap. of 100-TX Half Duplex */
265 #define MTD_LPAR_AD_TPFD 0x00000040 /* Cap. of 10-TP Full Duplex */
266 #define MTD_LPAR_AD_TPHD 0x00000020 /* Cap. of 10-TP Half Duplex */
267 #define MTD_LPAR_SELECTOR0 0x0000001f /* Selector field 0 */
