sys/dev/ic/mtd803var.h

   1 /* $NetBSD: mtd803var.h,v 1.5 2007/03/04 06:01:59 christos Exp $ */
   2
   3 /*-
   4  * Copyright (c) 2002 The NetBSD Foundation, Inc.
   5  * All rights reserved.
   6  *
   7  * This code is derived from software contributed to The NetBSD Foundation
   8  * by Peter Bex <Peter.Bex@student.kun.nl>.
   9  *
  10  * Redistribution and use in source and binary forms, with or without
  11  * modification, are permitted provided that the following conditions
  12  * are met:
  13  * 1. Redistributions of source code must retain the above copyright
  14  *    notice, this list of conditions and the following disclaimer.
  15  * 2. Redistributions in binary form must reproduce the above copyright
  16  *    notice, this list of conditions and the following disclaimer in the
  17  *    documentation and/or other materials provided with the distribution.
  18  *
  19  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
  20  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  21  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  22  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
  23  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  29  * POSSIBILITY OF SUCH DAMAGE.
  30  */
  31
  32 #include <sys/device.h>
  33 #include <sys/socket.h>
  34 #include <net/if.h>
  35 #include <net/if_ether.h>
  36 #include <net/if_media.h>
  37 #include <dev/mii/miivar.h>
  38
  39
  40 /* Number of Tx and Rx descriptors */
  41 #define MTD_NUM_TXD             64
  42 #define MTD_NUM_RXD             64
  43 /* Tx and Rx buffer size */
  44 #define MTD_RXBUF_SIZE          1536
  45 #define MTD_TXBUF_SIZE          1536
  46
  47 /* DMA mem must be longword (4 bytes) aligned */
  48 #define MTD_DMA_ALIGN           4
  49
  50
  51 /* Descriptor structure */
  52 struct mtd_desc {
  53         u_int32_t stat;                 /* Status field */
  54         u_int32_t conf;                 /* Config field */
  55         u_int32_t data;                 /* Data buffer start address */
  56         u_int32_t next;                 /* Next descriptor address */
  57 };
  58
  59 /* Softc struct */
  60 struct mtd_softc {
  61         struct device           dev;
  62         struct mii_data         mii;
  63         struct ethercom         ethercom;
  64         bus_space_tag_t         bus_tag;
  65         bus_space_handle_t      bus_handle;
  66         void *                  sd_hook;
  67         u_int8_t                eaddr[ETHER_ADDR_LEN];
  68         volatile unsigned int   cur_tx;
  69         volatile unsigned int   cur_rx;
  70
  71         bus_dma_tag_t           dma_tag;
  72         struct mtd_desc *       desc;
  73         bus_dmamap_t            desc_dma_map;
  74         void *                  buf;
  75         bus_dmamap_t            buf_dma_map;
  76
  77 #if NRND > 0
  78         rndsource_element_t     rnd_src;
  79 #endif
  80 };
  81
  82
  83 /* Transmit descriptor layout */
  84         /* Status register */
  85 #define MTD_TXD_OWNER           0x80000000      /* Owner bit */
  86 #define MTD_TXD_RSRVD0          0x7fffc000      /* Bits [30:14] are reserved */
  87 #define MTD_TXD_ABORT           0x00002000      /* Transmit aborted */
  88 #define MTD_TXD_CSL             0x00001000      /* Carrier Sense Loss */
  89 #define MTD_TXD_LCOL            0x00000800      /* Late collision */
  90 #define MTD_TXD_EXCOL           0x00000400      /* Excessive collisions */
  91 #define MTD_TXD_DFD             0x00000200      /* Deferred */
  92 #define MTD_TXD_HBFAIL          0x00000100      /* Heart-beat failure */
  93 #define MTD_TXD_NRC             0x000000ff      /* Collision Retry Count */
  94         /* Configuration register */
  95 #define MTD_TXD_CONF_IRQC       0x80000000      /* Interrupt control */
  96 #define MTD_TXD_CONF_EIRQC      0x40000000      /* Early interrupt control */
  97 #define MTD_TXD_CONF_LSD        0x20000000      /* Last descriptor */
  98 #define MTD_TXD_CONF_FSD        0x10000000      /* First descriptor */
  99 #define MTD_TXD_CONF_CRC        0x08000000      /* CRC append */
 100 #define MTD_TXD_CONF_PAD        0x04000000      /* Pad control */
 101 #define MTD_TXD_CONF_RLCOL      0x02000000      /* Retry Late Collision */
 102 #define MTD_TXD_CONF_RSRVD0     0x01c00000      /* Bits [24:22] are reserved */
 103 #define MTD_TXD_CONF_PKTS       0x003ff800      /* Packet size */
 104 #define MTD_TXD_CONF_BUFS       0x000007ff      /* Transmit buffer size */
 105
 106 #define MTD_TXD_PKTS_SHIFT      11
 107
 108 /* Receive descriptor layout */
 109         /* Status register */
 110 #define MTD_RXD_OWNER           0x80000000      /* Owner bit */
 111 #define MTD_RXD_RSRVD3          0x70000000      /* Bits [30:28] are reserved */
 112 #define MTD_RXD_FLEN            0x0fff0000      /* Frame length */
 113 #define MTD_RXD_RSRVD2          0x00008000      /* Bit 15 is reserved */
 114 #define MTD_RXD_MAR             0x00004000      /* Multicast Address Received */
 115 #define MTD_RXD_BAR             0x00002000      /* Broadcast Address Received */
 116 #define MTD_RXD_PAR             0x00001000      /* Physical Address Received */
 117 #define MTD_RXD_FSD             0x00000800      /* First Descriptor */
 118 #define MTD_RXD_LSD             0x00000400      /* Last Descriptor */
 119 #define MTD_RXD_RSRVD1          0x00000300      /* Bits [9:8] are reserved */
 120 #define MTD_RXD_ERRSUM          0x00000080      /* Error summary */
 121 #define MTD_RXD_RUNT            0x00000040      /* Runt packet received */
 122 #define MTD_RXD_LONG            0x00000020      /* Long packet received */
 123 #define MTD_RXD_FALERR          0x00000010      /* Frame alignment error */
 124 #define MTD_RXD_CRC             0x00000008      /* CRC error. See manual :) */
 125 #define MTD_RXD_RXERR           0x00000004      /* Receive error */
 126 #define MTD_RXD_RSRVD0          0x00000003      /* Bits [1:0] are reserved */
 127         /* Configuration register */
 128 #define MTD_RXD_CONF_RSRVD0     0xfffff800      /* Bits [31:11] are reserved */
 129 #define MTD_RXD_CONF_BUFS       0x000007ff      /* Receive buffer size */
 130
 131 #define MTD_RXD_FLEN_SHIFT      16
 132
 133 extern int mtd_config(struct mtd_softc *);
 134 extern int mtd_irq_h(void *);