sys/dev/ic/mvsatavar.h

   1 /*      $NetBSD$        */
   2 /*
   3  * Copyright (c) 2008 KIYOHARA Takashi
   4  * All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  *
  15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  16  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  17  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  18  * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
  19  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  20  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  21  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  23  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
  24  * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  25  * POSSIBILITY OF SUCH DAMAGE.
  26  */
  27
  28 #ifndef _MVSATAVAR_H_
  29 #define _MVSATAVAR_H_
  30
  31 #define MVSATA_EDMAQ_LEN        32      /* keep compatibility to gen1 */
  32 #define MVSATA_EDMAQ_INC(i)     ((i) = ((i) + 1) % MVSATA_EDMAQ_LEN)
  33 #define MVSATA_HC_MAX           2
  34 #define MVSATA_PORT_MAX         4
  35 #define MVSATA_CHANNEL_MAX      (MVSATA_HC_MAX * MVSATA_PORT_MAX)
  36
  37
  38 struct mvsata_port;
  39
  40 union mvsata_crqb {
  41         struct crqb crqb;
  42         struct crqb_gen2e crqb_gen2e;
  43 };
  44
  45 struct _fix_phy_param {
  46         uint32_t pre_amps;              /* Pre/SignalAmps */
  47
  48         void (*_fix_phy)(struct mvsata_port *);
  49 };
  50
  51 struct mvsata_port {
  52         struct ata_channel port_ata_channel;
  53
  54         int port;
  55         struct mvsata_hc *port_hc;
  56
  57         enum {
  58                 nodma,
  59                 dma,
  60                 queued,
  61                 ncq,
  62         } port_edmamode;
  63
  64         int port_quetagidx;             /* Host Queue Tag valiable */
  65
  66         int port_prev_erqqop;           /* previous Req Queue Out-Pointer */
  67         bus_dma_tag_t port_dmat;
  68         union mvsata_crqb *port_crqb;   /* EDMA Command Request Block */
  69         bus_dmamap_t port_crqb_dmamap;
  70         struct crpb *port_crpb;         /* EDMA Command Response Block */
  71         bus_dmamap_t port_crpb_dmamap;
  72         struct eprd *port_eprd;         /* EDMA Phy Region Description Table */
  73         bus_dmamap_t port_eprd_dmamap;
  74         struct {
  75                 struct ata_xfer *xfer;          /* queued xfer */
  76                 bus_dmamap_t data_dmamap;       /* DMA data buffer */
  77                 bus_size_t eprd_offset;         /* offset of ePRD buffer */
  78                 struct eprd *eprd;              /* ePRD buffer */
  79         } port_reqtbl[MVSATA_EDMAQ_LEN];
  80
  81         bus_space_tag_t port_iot;
  82         bus_space_handle_t port_ioh;
  83         bus_space_handle_t port_sata_scontrol;  /* SATA Interface control reg */
  84         bus_space_handle_t port_sata_serror;    /* SATA Interface error reg */
  85         bus_space_handle_t port_sata_sstatus;   /* SATA Interface status reg */
  86         struct ata_queue port_ata_queue;
  87
  88         struct _fix_phy_param _fix_phy_param;
  89 };
  90
  91 struct mvsata_hc {
  92         int hc;
  93         struct mvsata_softc *hc_sc;
  94
  95         bus_space_tag_t hc_iot;         /* Tag for SATAHC Arbiter */
  96         bus_space_handle_t hc_ioh;      /* Handle for SATAHC Arbiter */
  97
  98         struct mvsata_port *hc_ports[MVSATA_CHANNEL_MAX];
  99 };
 100
 101 struct mvsata_softc {
 102         struct wdc_softc sc_wdcdev;     /* common wdc definitions */
 103
 104         int sc_model;
 105         int sc_rev;
 106         enum {
 107                 gen_unknown = 0,
 108                 gen1,
 109                 gen2,
 110                 gen2e
 111         } sc_gen;                       /* Generation for LSI */
 112         int sc_hc;                      /* number of host controller */
 113         int sc_port;                    /* number of port/host */
 114
 115         bus_space_tag_t sc_iot;
 116         bus_space_handle_t sc_ioh;
 117         bus_dma_tag_t sc_dmat;
 118
 119         struct wdc_regs *sc_wdc_regs;
 120         struct ata_channel *sc_ata_channels[MVSATA_CHANNEL_MAX];
 121         struct mvsata_hc sc_hcs[MVSATA_HC_MAX];
 122
 123         int sc_flags;
 124 #define MVSATA_FLAGS_PCIE       (1 << 0)
 125
 126         void (*sc_edma_setup_crqb)(struct mvsata_port *, int, int,
 127                                    struct ata_bio *);
 128         void (*sc_enable_intr)(struct mvsata_port *, int);
 129 };
 130
 131 int mvsata_attach(struct mvsata_softc *,
 132                   int (*mvsata_sreset)(struct mvsata_softc *),
 133                   int (*mvsata_misc_reset)(struct mvsata_softc *), int);
 134 int mvsata_intr(struct mvsata_hc *);
 135 int mvsata_error(struct mvsata_port *);
 136
 137 #endif  /* _MVSATAVAR_H_ */