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[netbsd-mini2440.git] / sys / dev / ic / ninjaata32.c
blobb35e982a79be2e873b5dbe10dbba2a11dbed89ee
1 /* $NetBSD: ninjaata32.c,v 1.10 2008/03/18 20:46:36 cube Exp $ */
2
3 /*
4 * Copyright (c) 2006 ITOH Yasufumi <itohy@NetBSD.org>.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS AND CONTRIBUTORS ``AS IS''
17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
18 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS OR CONTRIBUTORS
20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
26 * THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29 #include <sys/cdefs.h>
30 __KERNEL_RCSID(0, "$NetBSD: ninjaata32.c,v 1.10 2008/03/18 20:46:36 cube Exp $");
31
32 #include <sys/param.h>
33 #include <sys/kernel.h>
34 #include <sys/device.h>
35 #include <sys/proc.h>
36
37 #include <sys/bus.h>
38 #include <sys/intr.h>
39
40 #include <uvm/uvm_extern.h>
41
42 #include <dev/ata/atavar.h>
43 #include <dev/ic/wdcreg.h>
44 #include <dev/ic/wdcvar.h>
45
46 #include <dev/ic/ninjaata32reg.h>
47 #include <dev/ic/ninjaata32var.h>
48
49 #ifdef NJATA32_DEBUG
50 #define DPRINTF(x) printf x
51 #else
52 #define DPRINTF(x)
53 #endif
54
55 static void njata32_init(struct njata32_softc *, int nosleep);
56 static void njata32_irqack(struct ata_channel *);
57 static void njata32_clearirq(struct ata_channel *, int);
58 static void njata32_setup_channel(struct ata_channel *);
59 static int njata32_dma_init(void *, int channel, int drive,
60 void *databuf, size_t datalen, int flags);
61 static void njata32_piobm_start(void *, int channel, int drive, int skip,
62 int xferlen, int flags);
63 static int njata32_dma_finish(void *, int channel, int drive, int force);
64 static void njata32_piobm_done(void *, int channel, int drive);
65
66 #if 0 /* ATA DMA is currently unused */
67 static const uint8_t njata32_timing_dma[NJATA32_MODE_MAX_DMA + 1] = {
68 NJATA32_TIMING_DMA0, NJATA32_TIMING_DMA1, NJATA32_TIMING_DMA2
69 };
70 #endif
71 static const uint8_t njata32_timing_pio[NJATA32_MODE_MAX_PIO + 1] = {
72 NJATA32_TIMING_PIO0, NJATA32_TIMING_PIO1, NJATA32_TIMING_PIO2,
73 NJATA32_TIMING_PIO3, NJATA32_TIMING_PIO4
74 };
75
76 static void
77 njata32_init(struct njata32_softc *sc, int nosleep)
78 {
79
80 /* disable interrupts */
81 bus_space_write_1(NJATA32_REGT(sc), NJATA32_REGH(sc),
82 NJATA32_REG_IRQ_SELECT, 0);
83
84 /* bus reset */
85 bus_space_write_1(NJATA32_REGT(sc), NJATA32_REGH(sc), NJATA32_REG_AS,
86 NJATA32_AS_WAIT0 | NJATA32_AS_BUS_RESET);
87 if (nosleep)
88 delay(50000);
89 else
90 tsleep(sc, PRIBIO, "njaini", mstohz(50));
91 bus_space_write_1(NJATA32_REGT(sc), NJATA32_REGH(sc), NJATA32_REG_AS,
92 NJATA32_AS_WAIT0);
93
94 /* initial transfer speed */
95 bus_space_write_1(NJATA32_REGT(sc), NJATA32_REGH(sc),
96 NJATA32_REG_TIMING, NJATA32_TIMING_PIO0 + sc->sc_atawait);
97
98 /* setup busmaster mode */
99 bus_space_write_1(NJATA32_REGT(sc), NJATA32_REGH(sc), NJATA32_REG_IOBM,
100 NJATA32_IOBM_DEFAULT);
101
102 /* enable interrupts */
103 bus_space_write_1(NJATA32_REGT(sc), NJATA32_REGH(sc),
104 NJATA32_REG_IRQ_SELECT, NJATA32_IRQ_XFER | NJATA32_IRQ_DEV);
105 }
106
107 void
108 njata32_attach(struct njata32_softc *sc)
109 {
110 bus_addr_t dmaaddr;
111 int i, devno, error;
112 struct wdc_regs *wdr;
113
114 /*
115 * allocate DMA resource
116 */
117 if ((error = bus_dmamem_alloc(sc->sc_dmat,
118 sizeof(struct njata32_dma_page), PAGE_SIZE, 0,
119 &sc->sc_sgt_seg, 1, &sc->sc_sgt_nsegs, BUS_DMA_NOWAIT)) != 0) {
120 aprint_error("%s: unable to allocate sgt page, error = %d\n",
121 NJATA32NAME(sc), error);
122 return;
123 }
124 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_sgt_seg,
125 sc->sc_sgt_nsegs, sizeof(struct njata32_dma_page),
126 (void **)&sc->sc_sgtpg,
127 BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) {
128 aprint_error("%s: unable to map sgt page, error = %d\n",
129 NJATA32NAME(sc), error);
130 goto fail1;
131 }
132 if ((error = bus_dmamap_create(sc->sc_dmat,
133 sizeof(struct njata32_dma_page), 1,
134 sizeof(struct njata32_dma_page), 0, BUS_DMA_NOWAIT,
135 &sc->sc_dmamap_sgt)) != 0) {
136 aprint_error("%s: unable to create sgt DMA map, error = %d\n",
137 NJATA32NAME(sc), error);
138 goto fail2;
139 }
140 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap_sgt,
141 sc->sc_sgtpg, sizeof(struct njata32_dma_page),
142 NULL, BUS_DMA_NOWAIT)) != 0) {
143 aprint_error("%s: unable to load sgt DMA map, error = %d\n",
144 NJATA32NAME(sc), error);
145 goto fail3;
146 }
147
148 dmaaddr = sc->sc_dmamap_sgt->dm_segs[0].ds_addr;
149
150 for (devno = 0; devno < NJATA32_NUM_DEV; devno++) {
151 sc->sc_dev[devno].d_sgt = sc->sc_sgtpg->dp_sg[devno];
152 sc->sc_dev[devno].d_sgt_dma = dmaaddr +
153 offsetof(struct njata32_dma_page, dp_sg[devno]);
154
155 error = bus_dmamap_create(sc->sc_dmat,
156 NJATA32_MAX_XFER, /* max total map size */
157 NJATA32_NUM_SG, /* max number of segments */
158 NJATA32_SGT_MAXSEGLEN, /* max size of a segment */
159 0, /* boundary */
160 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW,
161 &sc->sc_dev[devno].d_dmamap_xfer);
162 if (error) {
163 aprint_error("%s: failed to create DMA map "
164 "(error = %d)\n", NJATA32NAME(sc), error);
165 goto fail4;
166 }
167 }
168
169 /* device properties */
170 sc->sc_wdcdev.sc_atac.atac_cap =
171 ATAC_CAP_DATA16 | ATAC_CAP_DATA32 | ATAC_CAP_PIOBM;
172 sc->sc_wdcdev.irqack = njata32_irqack;
173 sc->sc_wdcdev.sc_atac.atac_channels = sc->sc_wdc_chanarray;
174 sc->sc_wdcdev.sc_atac.atac_nchannels = NJATA32_NCHAN; /* 1 */
175 sc->sc_wdcdev.sc_atac.atac_pio_cap = NJATA32_MODE_MAX_PIO;
176 #if 0 /* ATA DMA is currently unused */
177 sc->sc_wdcdev.sc_atac.atac_dma_cap = NJATA32_MODE_MAX_DMA;
178 #endif
179 sc->sc_wdcdev.sc_atac.atac_set_modes = njata32_setup_channel;
180
181 /* DMA control functions */
182 sc->sc_wdcdev.dma_arg = sc;
183 sc->sc_wdcdev.dma_init = njata32_dma_init;
184 sc->sc_wdcdev.piobm_start = njata32_piobm_start;
185 sc->sc_wdcdev.dma_finish = njata32_dma_finish;
186 sc->sc_wdcdev.piobm_done = njata32_piobm_done;
187
188 sc->sc_wdcdev.cap |= WDC_CAPABILITY_NO_EXTRA_RESETS;
189
190 sc->sc_wdcdev.regs = wdr = &sc->sc_wdc_regs;
191
192 /* only one channel */
193 sc->sc_wdc_chanarray[0] = &sc->sc_ch[0].ch_ata_channel;
194 sc->sc_ch[0].ch_ata_channel.ch_channel = 0;
195 sc->sc_ch[0].ch_ata_channel.ch_atac = &sc->sc_wdcdev.sc_atac;
196 sc->sc_ch[0].ch_ata_channel.ch_queue = &sc->sc_wdc_chqueue;
197 sc->sc_ch[0].ch_ata_channel.ch_ndrive = 2; /* max number of drives */
198
199 /* map ATA registers */
200 for (i = 0; i < WDC_NREG; i++) {
201 if (bus_space_subregion(NJATA32_REGT(sc), NJATA32_REGH(sc),
202 NJATA32_OFFSET_WDCREGS + i,
203 i == wd_data ? 4 : 1, &wdr->cmd_iohs[i]) != 0) {
204 aprint_error("%s: couldn't subregion cmd regs\n",
205 NJATA32NAME(sc));
206 goto fail4;
207 }
208 }
209 wdc_init_shadow_regs(&sc->sc_ch[0].ch_ata_channel);
210 wdr->data32iot = NJATA32_REGT(sc);
211 wdr->data32ioh = wdr->cmd_iohs[wd_data];
212
213 /* map ATA ctl reg */
214 wdr->ctl_iot = NJATA32_REGT(sc);
215 if (bus_space_subregion(NJATA32_REGT(sc), NJATA32_REGH(sc),
216 NJATA32_REG_WD_ALTSTATUS, 1, &wdr->ctl_ioh) != 0) {
217 aprint_error("%s: couldn't subregion ctl regs\n",
218 NJATA32NAME(sc));
219 goto fail4;
220 }
221
222 sc->sc_flags |= NJATA32_CMDPG_MAPPED;
223
224 /* use flags value as busmaster wait */
225 if ((sc->sc_atawait =
226 (uint8_t)device_cfdata(sc->sc_wdcdev.sc_atac.atac_dev)->cf_flags))
227 aprint_normal("%s: ATA wait = %#x\n",
228 NJATA32NAME(sc), sc->sc_atawait);
229
230 njata32_init(sc, cold);
231
232 wdcattach(&sc->sc_ch[0].ch_ata_channel);
233
234 return;
235
236 /*
237 * cleanup
238 */
239 fail4: while (--devno >= 0) {
240 bus_dmamap_destroy(sc->sc_dmat,
241 sc->sc_dev[devno].d_dmamap_xfer);
242 }
243 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap_sgt);
244 fail3: bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap_sgt);
245 fail2: bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_sgtpg,
246 sizeof(struct njata32_dma_page));
247 fail1: bus_dmamem_free(sc->sc_dmat, &sc->sc_sgt_seg, sc->sc_sgt_nsegs);
248 }
249
250 int
251 njata32_detach(struct njata32_softc *sc, int flags)
252 {
253 int rv, devno;
254
255 if (sc->sc_flags & NJATA32_CMDPG_MAPPED) {
256 if ((rv = wdcdetach(sc->sc_wdcdev.sc_atac.atac_dev, flags)))
257 return rv;
258
259 /* free DMA resource */
260 for (devno = 0; devno < NJATA32_NUM_DEV; devno++) {
261 bus_dmamap_destroy(sc->sc_dmat,
262 sc->sc_dev[devno].d_dmamap_xfer);
263 }
264 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap_sgt);
265 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap_sgt);
266 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_sgtpg,
267 sizeof(struct njata32_dma_page));
268 bus_dmamem_free(sc->sc_dmat, &sc->sc_sgt_seg, sc->sc_sgt_nsegs);
269 }
270
271 return 0;
272 }
273
274 static void
275 njata32_irqack(struct ata_channel *chp)
276 {
277 struct njata32_softc *sc = (void *)chp->ch_atac;
278
279 /* disable busmaster */
280 bus_space_write_1(NJATA32_REGT(sc), NJATA32_REGH(sc),
281 NJATA32_REG_BM, NJATA32_BM_WAIT0);
282 }
283
284 static void
285 njata32_clearirq(struct ata_channel *chp, int irq)
286 {
287 struct njata32_softc *sc = (void *)chp->ch_atac;
288
289 aprint_error("%s: unhandled intr: irq %#x, bm %#x, ",
290 NJATA32NAME(sc), irq,
291 bus_space_read_1(NJATA32_REGT(sc), NJATA32_REGH(sc),
292 NJATA32_REG_BM));
293
294 /* disable busmaster */
295 njata32_irqack(chp);
296
297 /* clear device interrupt */
298 aprint_normal("err %#x, seccnt %#x, cyl %#x, sdh %#x, ",
299 bus_space_read_1(NJATA32_REGT(sc), NJATA32_REGH(sc),
300 NJATA32_REG_WD_ERROR),
301 bus_space_read_1(NJATA32_REGT(sc), NJATA32_REGH(sc),
302 NJATA32_REG_WD_SECCNT),
303 bus_space_read_1(NJATA32_REGT(sc), NJATA32_REGH(sc),
304 NJATA32_REG_WD_CYL_LO) |
305 (bus_space_read_1(NJATA32_REGT(sc), NJATA32_REGH(sc),
306 NJATA32_REG_WD_CYL_HI) << 8),
307 bus_space_read_1(NJATA32_REGT(sc), NJATA32_REGH(sc),
308 NJATA32_REG_WD_SDH));
309 aprint_normal("status %#x\n",
310 bus_space_read_1(NJATA32_REGT(sc), NJATA32_REGH(sc),
311 NJATA32_REG_WD_STATUS));
312 }
313
314 static void
315 njata32_setup_channel(struct ata_channel *chp)
316 {
317 struct njata32_softc *sc = (void *)chp->ch_atac;
318 struct ata_drive_datas *drvp;
319 int drive;
320 uint8_t mode;
321
322 KASSERT(chp->ch_ndrive != 0);
323
324 sc->sc_timing_pio = 0;
325 #if 0 /* ATA DMA is currently unused */
326 sc->sc_timing_dma = 0;
327 #endif
328
329 for (drive = 0; drive < chp->ch_ndrive; drive++) {
330 drvp = &chp->ch_drive[drive];
331 if ((drvp->drive_flags & DRIVE) == 0)
332 continue; /* no drive */
333
334 #if 0 /* ATA DMA is currently unused */
335 if ((drvp->drive_flags & DRIVE_DMA) != 0) {
336 /*
337 * Multiword DMA
338 */
339 if ((mode = drvp->DMA_mode) > NJATA32_MODE_MAX_DMA)
340 mode = NJATA32_MODE_MAX_DMA;
341 if (sc->sc_timing_dma < njata32_timing_dma[mode])
342 sc->sc_timing_dma = njata32_timing_dma[mode];
343 }
344 #endif
345 /*
346 * PIO
347 */
348 if ((mode = drvp->PIO_mode) > NJATA32_MODE_MAX_PIO)
349 mode = NJATA32_MODE_MAX_PIO;
350 if (sc->sc_timing_pio < njata32_timing_pio[mode])
351 sc->sc_timing_pio = njata32_timing_pio[mode];
352 }
353
354 sc->sc_timing_pio += sc->sc_atawait;
355
356 /* set timing for PIO */
357 bus_space_write_1(NJATA32_REGT(sc), NJATA32_REGH(sc),
358 NJATA32_REG_TIMING, sc->sc_timing_pio);
359 }
360
361 /*
362 * map DMA buffer
363 */
364 int
365 njata32_dma_init(void *v, int channel, int drive, void *databuf,
366 size_t datalen, int flags)
367 {
368 struct njata32_softc *sc = v;
369 int error;
370 struct njata32_device *dev = &sc->sc_dev[drive];
371
372 KASSERT(channel == 0);
373 KASSERT((dev->d_flags & NJATA32_DEV_DMA_MAPPED) == 0);
374 KASSERT((dev->d_flags & NJATA32_DEV_DMA_STARTED) == 0);
375
376 KASSERT(flags & (WDC_DMA_PIOBM_ATA | WDC_DMA_PIOBM_ATAPI));
377
378 /* use PIO for short transfer */
379 if (datalen < 64 /* needs tune */) {
380 DPRINTF(("%s: njata32_dma_init: short transfer (%u)\n",
381 NJATA32NAME(sc), (unsigned)datalen));
382 bus_space_write_1(NJATA32_REGT(sc), NJATA32_REGH(sc),
383 NJATA32_REG_TIMING, sc->sc_timing_pio);
384 return EINVAL;
385 }
386
387 /* use PIO for unaligned transfer (word alignment seems OK) */
388 if (((uintptr_t)databuf & 1) || (datalen & 1)) {
389 DPRINTF(("%s: njata32_dma_init: unaligned: buf %p, len %u\n",
390 NJATA32NAME(sc), databuf, (unsigned)datalen));
391 return EINVAL;
392 }
393
394 DPRINTF(("%s: njata32_dma_init: %s: databuf %p, datalen %u\n",
395 NJATA32NAME(sc), (flags & WDC_DMA_READ) ? "read" : "write",
396 databuf, (unsigned)datalen));
397
398 error = bus_dmamap_load(sc->sc_dmat, dev->d_dmamap_xfer,
399 databuf, datalen, NULL, BUS_DMA_NOWAIT | BUS_DMA_STREAMING |
400 ((flags & WDC_DMA_READ) ? BUS_DMA_READ : BUS_DMA_WRITE));
401 if (error) {
402 printf("%s: load xfer failed, error %d\n",
403 NJATA32NAME(sc), error);
404 return error;
405 }
406
407 bus_dmamap_sync(sc->sc_dmat, dev->d_dmamap_xfer, 0,
408 dev->d_dmamap_xfer->dm_mapsize,
409 (flags & WDC_DMA_READ) ?
410 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE);
411
412 dev->d_flags =
413 ((flags & WDC_DMA_READ) ? NJATA32_DEV_DMA_READ : 0) |
414 ((flags & WDC_DMA_PIOBM_ATAPI) ? NJATA32_DEV_DMA_ATAPI : 0) |
415 NJATA32_DEV_DMA_MAPPED;
416
417 return 0;
418 }
419
420 /*
421 * start DMA
422 *
423 * top: databuf + skip
424 * size: xferlen
425 */
426 void
427 njata32_piobm_start(void *v, int channel, int drive,
428 int skip, int xferlen, int flags)
429 {
430 struct njata32_softc *sc = v;
431 struct njata32_device *dev = &sc->sc_dev[drive];
432 int i, nsegs, seglen;
433 uint8_t bmreg;
434
435 DPRINTF(("%s: njata32_piobm_start: ch%d, dv%d, skip %d, xferlen %d\n",
436 NJATA32NAME(sc), channel, drive, skip, xferlen));
437
438 KASSERT(channel == 0);
439 KASSERT(dev->d_flags & NJATA32_DEV_DMA_MAPPED);
440 KASSERT((dev->d_flags & NJATA32_DEV_DMA_STARTED) == 0);
441
442 /*
443 * create scatter/gather table
444 * XXX this code may be slow
445 */
446 for (i = nsegs = 0;
447 i < dev->d_dmamap_xfer->dm_nsegs && xferlen > 0; i++) {
448 if (dev->d_dmamap_xfer->dm_segs[i].ds_len <= skip) {
449 skip -= dev->d_dmamap_xfer->dm_segs[i].ds_len;
450 continue;
451 }
452
453 seglen = dev->d_dmamap_xfer->dm_segs[i].ds_len - skip;
454 if (seglen > xferlen)
455 seglen = xferlen;
456
457 dev->d_sgt[nsegs].sg_addr =
458 htole32(dev->d_dmamap_xfer->dm_segs[i].ds_addr + skip);
459 dev->d_sgt[nsegs].sg_len = htole32(seglen);
460
461 xferlen -= seglen;
462 nsegs++;
463 skip = 0;
464 }
465 sc->sc_piobm_nsegs = nsegs;
466 /* end mark */
467 dev->d_sgt[nsegs - 1].sg_len |= htole32(NJATA32_SGT_ENDMARK);
468
469 #ifdef DIAGNOSTIC
470 if (xferlen)
471 panic("%s: njata32_piobm_start: xferlen residue %d\n",
472 NJATA32NAME(sc), xferlen);
473 #endif
474
475 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap_sgt,
476 (char *)dev->d_sgt - (char *)sc->sc_sgtpg,
477 sizeof(struct njata32_sgtable) * nsegs,
478 BUS_DMASYNC_PREWRITE);
479
480 /* set timing for PIO */
481 bus_space_write_1(NJATA32_REGT(sc), NJATA32_REGH(sc),
482 NJATA32_REG_TIMING, sc->sc_timing_pio);
483
484 bus_space_write_1(NJATA32_REGT(sc), NJATA32_REGH(sc), NJATA32_REG_IOBM,
485 NJATA32_IOBM_DEFAULT);
486 bus_space_write_1(NJATA32_REGT(sc), NJATA32_REGH(sc), NJATA32_REG_AS,
487 NJATA32_AS_WAIT0);
488
489 /*
490 * interrupt configuration
491 */
492 if ((dev->d_flags & (NJATA32_DEV_DMA_READ | NJATA32_DEV_DMA_ATAPI)) ==
493 NJATA32_DEV_DMA_READ) {
494 /*
495 * ATA piobm read is executed while device interrupt is active,
496 * so disable device interrupt here
497 */
498 bus_space_write_1(NJATA32_REGT(sc), NJATA32_REGH(sc),
499 NJATA32_REG_IRQ_SELECT, NJATA32_IRQ_XFER);
500 }
501
502 /* enable scatter/gather busmaster transfer */
503 bmreg = NJATA32_BM_EN | NJATA32_BM_SG | NJATA32_BM_WAIT0 |
504 ((dev->d_flags & NJATA32_DEV_DMA_READ) ? NJATA32_BM_RD : 0);
505 bus_space_write_1(NJATA32_REGT(sc), NJATA32_REGH(sc), NJATA32_REG_BM,
506 bmreg);
507
508 /* load scatter/gather table */
509 bus_space_write_4(NJATA32_REGT(sc), NJATA32_REGH(sc),
510 NJATA32_REG_DMAADDR, dev->d_sgt_dma);
511 bus_space_write_4(NJATA32_REGT(sc), NJATA32_REGH(sc),
512 NJATA32_REG_DMALENGTH, sizeof(struct njata32_sgtable) * nsegs);
513
514 /* start transfer */
515 bus_space_write_1(NJATA32_REGT(sc), NJATA32_REGH(sc), NJATA32_REG_BM,
516 (bus_space_read_1(NJATA32_REGT(sc), NJATA32_REGH(sc),
517 NJATA32_REG_BM)
518 & ~(NJATA32_BM_RD|NJATA32_BM_SG|NJATA32_BM_WAIT_MASK)) |
519 bmreg | NJATA32_BM_GO);
520
521 sc->sc_devflags = dev->d_flags;
522 if (flags & WDC_PIOBM_XFER_IRQ)
523 sc->sc_devflags |= NJATA32_DEV_XFER_INTR;
524 #ifdef DIAGNOSTIC
525 dev->d_flags |= NJATA32_DEV_DMA_STARTED;
526 #endif
527 }
528
529 /*
530 * end of DMA
531 */
532 int
533 njata32_dma_finish(void *v, int channel, int drive,
534 int force)
535 {
536 struct njata32_softc *sc = v;
537 struct njata32_device *dev = &sc->sc_dev[drive];
538 int bm;
539 int error = 0;
540
541 DPRINTF(("%s: njata32_dma_finish: bm = %#x\n", NJATA32NAME(sc),
542 bus_space_read_1(NJATA32_REGT(sc), NJATA32_REGH(sc),
543 NJATA32_REG_BM)));
544
545 KASSERT(channel == 0);
546 KASSERT(dev->d_flags & NJATA32_DEV_DMA_MAPPED);
547 KASSERT(dev->d_flags & NJATA32_DEV_DMA_STARTED);
548
549 bm = bus_space_read_1(NJATA32_REGT(sc), NJATA32_REGH(sc),
550 NJATA32_REG_BM);
551
552 #ifdef NJATA32_DEBUG
553 printf("%s: irq %#x, bm %#x, 18 %#x, 1c %#x\n", NJATA32NAME(sc),
554 bus_space_read_1(NJATA32_REGT(sc), NJATA32_REGH(sc),
555 NJATA32_REG_IRQ_STAT),
556 bm,
557 bus_space_read_4(NJATA32_REGT(sc), NJATA32_REGH(sc), 0x18),
558 bus_space_read_1(NJATA32_REGT(sc), NJATA32_REGH(sc), 0x1c));
559 #endif
560
561 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap_sgt,
562 (char *)dev->d_sgt - (char *)sc->sc_sgtpg,
563 sizeof(struct njata32_sgtable) * sc->sc_piobm_nsegs,
564 BUS_DMASYNC_POSTWRITE);
565
566 /* check if DMA is active */
567 if (bm & NJATA32_BM_GO) {
568 error = WDC_DMAST_NOIRQ;
569
570 switch (force) {
571 case WDC_DMAEND_END:
572 return error;
573
574 case WDC_DMAEND_ABRT:
575 printf("%s: aborting DMA\n", NJATA32NAME(sc));
576 break;
577 }
578 }
579
580 /*
581 * ???
582 * For unknown reason, PIOBM transfer sometimes fails in the middle,
583 * in which case the bit #7 of BM register becomes 0.
584 * Increasing the wait value seems to improve the situation.
585 *
586 * XXX
587 * PIO transfer may also fail, but it seems it can't be detected.
588 */
589 if ((bm & NJATA32_BM_DONE) == 0) {
590 error |= WDC_DMAST_ERR;
591 printf("%s: busmaster error", NJATA32NAME(sc));
592 if (sc->sc_atawait < 0x11) {
593 if ((sc->sc_atawait & 0xf) == 0)
594 sc->sc_atawait++;
595 else
596 sc->sc_atawait += 0x10;
597 printf(", new ATA wait = %#x", sc->sc_atawait);
598 njata32_setup_channel(&sc->sc_ch[0].ch_ata_channel);
599 }
600 printf("\n");
601 }
602
603 /* stop command */
604 bus_space_write_1(NJATA32_REGT(sc), NJATA32_REGH(sc), NJATA32_REG_AS,
605 NJATA32_AS_WAIT0);
606 bus_space_write_1(NJATA32_REGT(sc), NJATA32_REGH(sc), NJATA32_REG_BM,
607 NJATA32_BM_WAIT0);
608
609 /* set timing for PIO */
610 bus_space_write_1(NJATA32_REGT(sc), NJATA32_REGH(sc),
611 NJATA32_REG_TIMING, sc->sc_timing_pio);
612
613 /*
614 * reenable device interrupt in case it was disabled for
615 * this transfer
616 */
617 bus_space_write_1(NJATA32_REGT(sc), NJATA32_REGH(sc),
618 NJATA32_REG_IRQ_SELECT, NJATA32_IRQ_XFER | NJATA32_IRQ_DEV);
619
620 #if 1 /* should be? */
621 if ((sc->sc_devflags & NJATA32_DEV_GOT_XFER_INTR) == 0)
622 error |= WDC_DMAST_ERR;
623 #endif
624 sc->sc_devflags = 0;
625
626 #ifdef DIAGNOSTIC
627 dev->d_flags &= ~NJATA32_DEV_DMA_STARTED;
628 #endif
629
630 return error;
631 }
632
633 /*
634 * unmap DMA buffer
635 */
636 void
637 njata32_piobm_done(void *v, int channel, int drive)
638 {
639 struct njata32_softc *sc = v;
640 struct njata32_device *dev = &sc->sc_dev[drive];
641
642 DPRINTF(("%s: njata32_piobm_done: ch%d dv%d\n",
643 NJATA32NAME(sc), channel, drive));
644
645 KASSERT(channel == 0);
646 KASSERT(dev->d_flags & NJATA32_DEV_DMA_MAPPED);
647 KASSERT((dev->d_flags & NJATA32_DEV_DMA_STARTED) == 0);
648
649 /* unload dma map */
650 bus_dmamap_sync(sc->sc_dmat, dev->d_dmamap_xfer,
651 0, dev->d_dmamap_xfer->dm_mapsize,
652 (dev->d_flags & NJATA32_DEV_DMA_READ) ?
653 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
654
655 bus_dmamap_unload(sc->sc_dmat, dev->d_dmamap_xfer);
656 dev->d_flags &= ~NJATA32_DEV_DMA_MAPPED;
657 }
658
659 int
660 njata32_intr(void *arg)
661 {
662 struct njata32_softc *sc = arg;
663 struct ata_channel *chp;
664 int irq;
665
666 irq = bus_space_read_1(NJATA32_REGT(sc), NJATA32_REGH(sc),
667 NJATA32_REG_IRQ_STAT);
668 if ((irq & (NJATA32_IRQ_XFER | NJATA32_IRQ_DEV)) == 0)
669 return 0; /* not mine */
670
671 DPRINTF(("%s: njata32_intr: irq = %#x, altstatus = %#x\n",
672 NJATA32NAME(sc), irq,
673 bus_space_read_1(NJATA32_REGT(sc), NJATA32_REGH(sc),
674 NJATA32_REG_WD_ALTSTATUS)));
675
676 chp = &sc->sc_ch[0].ch_ata_channel;
677
678 if (irq & NJATA32_IRQ_XFER)
679 sc->sc_devflags |= NJATA32_DEV_GOT_XFER_INTR;
680
681 if ((irq & (NJATA32_IRQ_XFER | NJATA32_IRQ_DEV)) == NJATA32_IRQ_XFER &&
682 (sc->sc_devflags & NJATA32_DEV_XFER_INTR) == 0) {
683 /*
684 * transfer done, wait for device interrupt
685 */
686 bus_space_write_1(NJATA32_REGT(sc), NJATA32_REGH(sc),
687 NJATA32_REG_BM, NJATA32_BM_WAIT0);
688 return 1;
689 }
690
691 /*
692 * If both transfer done interrupt and device interrupt are
693 * active for ATAPI transfer, call wdcintr() twice.
694 */
695 if ((sc->sc_devflags & NJATA32_DEV_DMA_ATAPI) &&
696 (irq & (NJATA32_IRQ_XFER | NJATA32_IRQ_DEV)) ==
697 (NJATA32_IRQ_XFER | NJATA32_IRQ_DEV) &&
698 (sc->sc_devflags & NJATA32_DEV_XFER_INTR)) {
699 if (wdcintr(chp) == 0) {
700 njata32_clearirq(&sc->sc_ch[0].ch_ata_channel, irq);
701 }
702 }
703
704 if (wdcintr(chp) == 0) {
705 njata32_clearirq(&sc->sc_ch[0].ch_ata_channel, irq);
706 }
707
708 return 1;
709 }
NetBSD on the FriendlyARM MINI2440