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[netbsd-mini2440.git] / sys / dev / ic / rtl8169.c
blob1f7d6c0b845dc6fa0554f3e231203420e69f9fbe
1 /* $NetBSD: rtl8169.c,v 1.127 2009/09/05 08:23:24 tsutsui Exp $ */
2
3 /*
4 * Copyright (c) 1997, 1998-2003
5 * Bill Paul <wpaul@windriver.com>. All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. All advertising materials mentioning features or use of this software
16 * must display the following acknowledgement:
17 * This product includes software developed by Bill Paul.
18 * 4. Neither the name of the author nor the names of any co-contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
32 * THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35 #include <sys/cdefs.h>
36 __KERNEL_RCSID(0, "$NetBSD: rtl8169.c,v 1.127 2009/09/05 08:23:24 tsutsui Exp $");
37 /* $FreeBSD: /repoman/r/ncvs/src/sys/dev/re/if_re.c,v 1.20 2004/04/11 20:34:08 ru Exp $ */
38
39 /*
40 * RealTek 8139C+/8169/8169S/8110S PCI NIC driver
41 *
42 * Written by Bill Paul <wpaul@windriver.com>
43 * Senior Networking Software Engineer
44 * Wind River Systems
45 */
46
47 /*
48 * This driver is designed to support RealTek's next generation of
49 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently
50 * four devices in this family: the RTL8139C+, the RTL8169, the RTL8169S
51 * and the RTL8110S.
52 *
53 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible
54 * with the older 8139 family, however it also supports a special
55 * C+ mode of operation that provides several new performance enhancing
56 * features. These include:
57 *
58 * o Descriptor based DMA mechanism. Each descriptor represents
59 * a single packet fragment. Data buffers may be aligned on
60 * any byte boundary.
61 *
62 * o 64-bit DMA
63 *
64 * o TCP/IP checksum offload for both RX and TX
65 *
66 * o High and normal priority transmit DMA rings
67 *
68 * o VLAN tag insertion and extraction
69 *
70 * o TCP large send (segmentation offload)
71 *
72 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+
73 * programming API is fairly straightforward. The RX filtering, EEPROM
74 * access and PHY access is the same as it is on the older 8139 series
75 * chips.
76 *
77 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the
78 * same programming API and feature set as the 8139C+ with the following
79 * differences and additions:
80 *
81 * o 1000Mbps mode
82 *
83 * o Jumbo frames
84 *
85 * o GMII and TBI ports/registers for interfacing with copper
86 * or fiber PHYs
87 *
88 * o RX and TX DMA rings can have up to 1024 descriptors
89 * (the 8139C+ allows a maximum of 64)
90 *
91 * o Slight differences in register layout from the 8139C+
92 *
93 * The TX start and timer interrupt registers are at different locations
94 * on the 8169 than they are on the 8139C+. Also, the status word in the
95 * RX descriptor has a slightly different bit layout. The 8169 does not
96 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska'
97 * copper gigE PHY.
98 *
99 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs
100 * (the 'S' stands for 'single-chip'). These devices have the same
101 * programming API as the older 8169, but also have some vendor-specific
102 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard
103 * part designed to be pin-compatible with the RealTek 8100 10/100 chip.
104 *
105 * This driver takes advantage of the RX and TX checksum offload and
106 * VLAN tag insertion/extraction features. It also implements TX
107 * interrupt moderation using the timer interrupt registers, which
108 * significantly reduces TX interrupt load. There is also support
109 * for jumbo frames, however the 8169/8169S/8110S can not transmit
110 * jumbo frames larger than 7.5K, so the max MTU possible with this
111 * driver is 7500 bytes.
112 */
113
114 #include "bpfilter.h"
115
116 #include <sys/param.h>
117 #include <sys/endian.h>
118 #include <sys/systm.h>
119 #include <sys/sockio.h>
120 #include <sys/mbuf.h>
121 #include <sys/malloc.h>
122 #include <sys/kernel.h>
123 #include <sys/socket.h>
124 #include <sys/device.h>
125
126 #include <net/if.h>
127 #include <net/if_arp.h>
128 #include <net/if_dl.h>
129 #include <net/if_ether.h>
130 #include <net/if_media.h>
131 #include <net/if_vlanvar.h>
132
133 #include <netinet/in_systm.h> /* XXX for IP_MAXPACKET */
134 #include <netinet/in.h> /* XXX for IP_MAXPACKET */
135 #include <netinet/ip.h> /* XXX for IP_MAXPACKET */
136
137 #if NBPFILTER > 0
138 #include <net/bpf.h>
139 #endif
140
141 #include <sys/bus.h>
142
143 #include <dev/mii/mii.h>
144 #include <dev/mii/miivar.h>
145
146 #include <dev/ic/rtl81x9reg.h>
147 #include <dev/ic/rtl81x9var.h>
148
149 #include <dev/ic/rtl8169var.h>
150
151 static inline void re_set_bufaddr(struct re_desc *, bus_addr_t);
152
153 static int re_newbuf(struct rtk_softc *, int, struct mbuf *);
154 static int re_rx_list_init(struct rtk_softc *);
155 static int re_tx_list_init(struct rtk_softc *);
156 static void re_rxeof(struct rtk_softc *);
157 static void re_txeof(struct rtk_softc *);
158 static void re_tick(void *);
159 static void re_start(struct ifnet *);
160 static int re_ioctl(struct ifnet *, u_long, void *);
161 static int re_init(struct ifnet *);
162 static void re_stop(struct ifnet *, int);
163 static void re_watchdog(struct ifnet *);
164
165 static int re_enable(struct rtk_softc *);
166 static void re_disable(struct rtk_softc *);
167
168 static int re_gmii_readreg(device_t, int, int);
169 static void re_gmii_writereg(device_t, int, int, int);
170
171 static int re_miibus_readreg(device_t, int, int);
172 static void re_miibus_writereg(device_t, int, int, int);
173 static void re_miibus_statchg(device_t);
174
175 static void re_reset(struct rtk_softc *);
176
177 static inline void
178 re_set_bufaddr(struct re_desc *d, bus_addr_t addr)
179 {
180
181 d->re_bufaddr_lo = htole32((uint32_t)addr);
182 if (sizeof(bus_addr_t) == sizeof(uint64_t))
183 d->re_bufaddr_hi = htole32((uint64_t)addr >> 32);
184 else
185 d->re_bufaddr_hi = 0;
186 }
187
188 static int
189 re_gmii_readreg(device_t dev, int phy, int reg)
190 {
191 struct rtk_softc *sc = device_private(dev);
192 uint32_t rval;
193 int i;
194
195 if (phy != 7)
196 return 0;
197
198 /* Let the rgephy driver read the GMEDIASTAT register */
199
200 if (reg == RTK_GMEDIASTAT) {
201 rval = CSR_READ_1(sc, RTK_GMEDIASTAT);
202 return rval;
203 }
204
205 CSR_WRITE_4(sc, RTK_PHYAR, reg << 16);
206 DELAY(1000);
207
208 for (i = 0; i < RTK_TIMEOUT; i++) {
209 rval = CSR_READ_4(sc, RTK_PHYAR);
210 if (rval & RTK_PHYAR_BUSY)
211 break;
212 DELAY(100);
213 }
214
215 if (i == RTK_TIMEOUT) {
216 printf("%s: PHY read failed\n", device_xname(sc->sc_dev));
217 return 0;
218 }
219
220 return rval & RTK_PHYAR_PHYDATA;
221 }
222
223 static void
224 re_gmii_writereg(device_t dev, int phy, int reg, int data)
225 {
226 struct rtk_softc *sc = device_private(dev);
227 uint32_t rval;
228 int i;
229
230 CSR_WRITE_4(sc, RTK_PHYAR, (reg << 16) |
231 (data & RTK_PHYAR_PHYDATA) | RTK_PHYAR_BUSY);
232 DELAY(1000);
233
234 for (i = 0; i < RTK_TIMEOUT; i++) {
235 rval = CSR_READ_4(sc, RTK_PHYAR);
236 if (!(rval & RTK_PHYAR_BUSY))
237 break;
238 DELAY(100);
239 }
240
241 if (i == RTK_TIMEOUT) {
242 printf("%s: PHY write reg %x <- %x failed\n",
243 device_xname(sc->sc_dev), reg, data);
244 }
245 }
246
247 static int
248 re_miibus_readreg(device_t dev, int phy, int reg)
249 {
250 struct rtk_softc *sc = device_private(dev);
251 uint16_t rval = 0;
252 uint16_t re8139_reg = 0;
253 int s;
254
255 s = splnet();
256
257 if ((sc->sc_quirk & RTKQ_8139CPLUS) == 0) {
258 rval = re_gmii_readreg(dev, phy, reg);
259 splx(s);
260 return rval;
261 }
262
263 /* Pretend the internal PHY is only at address 0 */
264 if (phy) {
265 splx(s);
266 return 0;
267 }
268 switch (reg) {
269 case MII_BMCR:
270 re8139_reg = RTK_BMCR;
271 break;
272 case MII_BMSR:
273 re8139_reg = RTK_BMSR;
274 break;
275 case MII_ANAR:
276 re8139_reg = RTK_ANAR;
277 break;
278 case MII_ANER:
279 re8139_reg = RTK_ANER;
280 break;
281 case MII_ANLPAR:
282 re8139_reg = RTK_LPAR;
283 break;
284 case MII_PHYIDR1:
285 case MII_PHYIDR2:
286 splx(s);
287 return 0;
288 /*
289 * Allow the rlphy driver to read the media status
290 * register. If we have a link partner which does not
291 * support NWAY, this is the register which will tell
292 * us the results of parallel detection.
293 */
294 case RTK_MEDIASTAT:
295 rval = CSR_READ_1(sc, RTK_MEDIASTAT);
296 splx(s);
297 return rval;
298 default:
299 printf("%s: bad phy register\n", device_xname(sc->sc_dev));
300 splx(s);
301 return 0;
302 }
303 rval = CSR_READ_2(sc, re8139_reg);
304 if ((sc->sc_quirk & RTKQ_8139CPLUS) != 0 && re8139_reg == RTK_BMCR) {
305 /* 8139C+ has different bit layout. */
306 rval &= ~(BMCR_LOOP | BMCR_ISO);
307 }
308 splx(s);
309 return rval;
310 }
311
312 static void
313 re_miibus_writereg(device_t dev, int phy, int reg, int data)
314 {
315 struct rtk_softc *sc = device_private(dev);
316 uint16_t re8139_reg = 0;
317 int s;
318
319 s = splnet();
320
321 if ((sc->sc_quirk & RTKQ_8139CPLUS) == 0) {
322 re_gmii_writereg(dev, phy, reg, data);
323 splx(s);
324 return;
325 }
326
327 /* Pretend the internal PHY is only at address 0 */
328 if (phy) {
329 splx(s);
330 return;
331 }
332 switch (reg) {
333 case MII_BMCR:
334 re8139_reg = RTK_BMCR;
335 if ((sc->sc_quirk & RTKQ_8139CPLUS) != 0) {
336 /* 8139C+ has different bit layout. */
337 data &= ~(BMCR_LOOP | BMCR_ISO);
338 }
339 break;
340 case MII_BMSR:
341 re8139_reg = RTK_BMSR;
342 break;
343 case MII_ANAR:
344 re8139_reg = RTK_ANAR;
345 break;
346 case MII_ANER:
347 re8139_reg = RTK_ANER;
348 break;
349 case MII_ANLPAR:
350 re8139_reg = RTK_LPAR;
351 break;
352 case MII_PHYIDR1:
353 case MII_PHYIDR2:
354 splx(s);
355 return;
356 break;
357 default:
358 printf("%s: bad phy register\n", device_xname(sc->sc_dev));
359 splx(s);
360 return;
361 }
362 CSR_WRITE_2(sc, re8139_reg, data);
363 splx(s);
364 return;
365 }
366
367 static void
368 re_miibus_statchg(device_t dev)
369 {
370
371 return;
372 }
373
374 static void
375 re_reset(struct rtk_softc *sc)
376 {
377 int i;
378
379 CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_RESET);
380
381 for (i = 0; i < RTK_TIMEOUT; i++) {
382 DELAY(10);
383 if ((CSR_READ_1(sc, RTK_COMMAND) & RTK_CMD_RESET) == 0)
384 break;
385 }
386 if (i == RTK_TIMEOUT)
387 printf("%s: reset never completed!\n",
388 device_xname(sc->sc_dev));
389
390 /*
391 * NB: Realtek-supplied FreeBSD driver does this only for MACFG_3,
392 * but also says "Rtl8169s sigle chip detected".
393 */
394 if ((sc->sc_quirk & RTKQ_MACLDPS) != 0)
395 CSR_WRITE_1(sc, RTK_LDPS, 1);
396
397 }
398
399 /*
400 * The following routine is designed to test for a defect on some
401 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64#
402 * lines connected to the bus, however for a 32-bit only card, they
403 * should be pulled high. The result of this defect is that the
404 * NIC will not work right if you plug it into a 64-bit slot: DMA
405 * operations will be done with 64-bit transfers, which will fail
406 * because the 64-bit data lines aren't connected.
407 *
408 * There's no way to work around this (short of talking a soldering
409 * iron to the board), however we can detect it. The method we use
410 * here is to put the NIC into digital loopback mode, set the receiver
411 * to promiscuous mode, and then try to send a frame. We then compare
412 * the frame data we sent to what was received. If the data matches,
413 * then the NIC is working correctly, otherwise we know the user has
414 * a defective NIC which has been mistakenly plugged into a 64-bit PCI
415 * slot. In the latter case, there's no way the NIC can work correctly,
416 * so we print out a message on the console and abort the device attach.
417 */
418
419 int
420 re_diag(struct rtk_softc *sc)
421 {
422 struct ifnet *ifp = &sc->ethercom.ec_if;
423 struct mbuf *m0;
424 struct ether_header *eh;
425 struct re_rxsoft *rxs;
426 struct re_desc *cur_rx;
427 bus_dmamap_t dmamap;
428 uint16_t status;
429 uint32_t rxstat;
430 int total_len, i, s, error = 0;
431 static const uint8_t dst[] = { 0x00, 'h', 'e', 'l', 'l', 'o' };
432 static const uint8_t src[] = { 0x00, 'w', 'o', 'r', 'l', 'd' };
433
434 /* Allocate a single mbuf */
435
436 MGETHDR(m0, M_DONTWAIT, MT_DATA);
437 if (m0 == NULL)
438 return ENOBUFS;
439
440 /*
441 * Initialize the NIC in test mode. This sets the chip up
442 * so that it can send and receive frames, but performs the
443 * following special functions:
444 * - Puts receiver in promiscuous mode
445 * - Enables digital loopback mode
446 * - Leaves interrupts turned off
447 */
448
449 ifp->if_flags |= IFF_PROMISC;
450 sc->re_testmode = 1;
451 re_init(ifp);
452 re_stop(ifp, 0);
453 DELAY(100000);
454 re_init(ifp);
455
456 /* Put some data in the mbuf */
457
458 eh = mtod(m0, struct ether_header *);
459 memcpy(eh->ether_dhost, (char *)&dst, ETHER_ADDR_LEN);
460 memcpy(eh->ether_shost, (char *)&src, ETHER_ADDR_LEN);
461 eh->ether_type = htons(ETHERTYPE_IP);
462 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN;
463
464 /*
465 * Queue the packet, start transmission.
466 */
467
468 CSR_WRITE_2(sc, RTK_ISR, 0xFFFF);
469 s = splnet();
470 IF_ENQUEUE(&ifp->if_snd, m0);
471 re_start(ifp);
472 splx(s);
473 m0 = NULL;
474
475 /* Wait for it to propagate through the chip */
476
477 DELAY(100000);
478 for (i = 0; i < RTK_TIMEOUT; i++) {
479 status = CSR_READ_2(sc, RTK_ISR);
480 if ((status & (RTK_ISR_TIMEOUT_EXPIRED | RTK_ISR_RX_OK)) ==
481 (RTK_ISR_TIMEOUT_EXPIRED | RTK_ISR_RX_OK))
482 break;
483 DELAY(10);
484 }
485 if (i == RTK_TIMEOUT) {
486 aprint_error_dev(sc->sc_dev,
487 "diagnostic failed, failed to receive packet "
488 "in loopback mode\n");
489 error = EIO;
490 goto done;
491 }
492
493 /*
494 * The packet should have been dumped into the first
495 * entry in the RX DMA ring. Grab it from there.
496 */
497
498 rxs = &sc->re_ldata.re_rxsoft[0];
499 dmamap = rxs->rxs_dmamap;
500 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize,
501 BUS_DMASYNC_POSTREAD);
502 bus_dmamap_unload(sc->sc_dmat, dmamap);
503
504 m0 = rxs->rxs_mbuf;
505 rxs->rxs_mbuf = NULL;
506 eh = mtod(m0, struct ether_header *);
507
508 RE_RXDESCSYNC(sc, 0, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
509 cur_rx = &sc->re_ldata.re_rx_list[0];
510 rxstat = le32toh(cur_rx->re_cmdstat);
511 total_len = rxstat & sc->re_rxlenmask;
512
513 if (total_len != ETHER_MIN_LEN) {
514 aprint_error_dev(sc->sc_dev,
515 "diagnostic failed, received short packet\n");
516 error = EIO;
517 goto done;
518 }
519
520 /* Test that the received packet data matches what we sent. */
521
522 if (memcmp((char *)&eh->ether_dhost, (char *)&dst, ETHER_ADDR_LEN) ||
523 memcmp((char *)&eh->ether_shost, (char *)&src, ETHER_ADDR_LEN) ||
524 ntohs(eh->ether_type) != ETHERTYPE_IP) {
525 aprint_error_dev(sc->sc_dev, "WARNING, DMA FAILURE!\n"
526 "expected TX data: %s/%s/0x%x\n"
527 "received RX data: %s/%s/0x%x\n"
528 "You may have a defective 32-bit NIC plugged "
529 "into a 64-bit PCI slot.\n"
530 "Please re-install the NIC in a 32-bit slot "
531 "for proper operation.\n"
532 "Read the re(4) man page for more details.\n" ,
533 ether_sprintf(dst), ether_sprintf(src), ETHERTYPE_IP,
534 ether_sprintf(eh->ether_dhost),
535 ether_sprintf(eh->ether_shost), ntohs(eh->ether_type));
536 error = EIO;
537 }
538
539 done:
540 /* Turn interface off, release resources */
541
542 sc->re_testmode = 0;
543 ifp->if_flags &= ~IFF_PROMISC;
544 re_stop(ifp, 0);
545 if (m0 != NULL)
546 m_freem(m0);
547
548 return error;
549 }
550
551
552 /*
553 * Attach the interface. Allocate softc structures, do ifmedia
554 * setup and ethernet/BPF attach.
555 */
556 void
557 re_attach(struct rtk_softc *sc)
558 {
559 uint8_t eaddr[ETHER_ADDR_LEN];
560 uint16_t val;
561 struct ifnet *ifp;
562 int error = 0, i, addr_len;
563
564 if ((sc->sc_quirk & RTKQ_8139CPLUS) == 0) {
565 uint32_t hwrev;
566
567 /* Revision of 8169/8169S/8110s in bits 30..26, 23 */
568 hwrev = CSR_READ_4(sc, RTK_TXCFG) & RTK_TXCFG_HWREV;
569 switch (hwrev) {
570 case RTK_HWREV_8169:
571 sc->sc_quirk |= RTKQ_8169NONS;
572 break;
573 case RTK_HWREV_8169S:
574 case RTK_HWREV_8110S:
575 case RTK_HWREV_8169_8110SB:
576 case RTK_HWREV_8169_8110SC:
577 sc->sc_quirk |= RTKQ_MACLDPS;
578 break;
579 case RTK_HWREV_8168_SPIN1:
580 case RTK_HWREV_8168_SPIN2:
581 case RTK_HWREV_8168_SPIN3:
582 sc->sc_quirk |= RTKQ_MACSTAT;
583 break;
584 case RTK_HWREV_8168C:
585 case RTK_HWREV_8168C_SPIN2:
586 case RTK_HWREV_8168CP:
587 case RTK_HWREV_8168D:
588 case RTK_HWREV_8168DP:
589 sc->sc_quirk |= RTKQ_DESCV2 | RTKQ_NOEECMD |
590 RTKQ_MACSTAT | RTKQ_CMDSTOP;
591 /*
592 * From FreeBSD driver:
593 *
594 * These (8168/8111) controllers support jumbo frame
595 * but it seems that enabling it requires touching
596 * additional magic registers. Depending on MAC
597 * revisions some controllers need to disable
598 * checksum offload. So disable jumbo frame until
599 * I have better idea what it really requires to
600 * make it support.
601 * RTL8168C/CP : supports up to 6KB jumbo frame.
602 * RTL8111C/CP : supports up to 9KB jumbo frame.
603 */
604 sc->sc_quirk |= RTKQ_NOJUMBO;
605 break;
606 case RTK_HWREV_8100E:
607 case RTK_HWREV_8100E_SPIN2:
608 case RTK_HWREV_8101E:
609 sc->sc_quirk |= RTKQ_NOJUMBO;
610 break;
611 case RTK_HWREV_8102E:
612 case RTK_HWREV_8102EL:
613 case RTK_HWREV_8103E:
614 sc->sc_quirk |= RTKQ_DESCV2 | RTKQ_NOEECMD |
615 RTKQ_MACSTAT | RTKQ_CMDSTOP | RTKQ_NOJUMBO;
616 break;
617 default:
618 aprint_normal_dev(sc->sc_dev,
619 "Unknown revision (0x%08x)\n", hwrev);
620 /* assume the latest features */
621 sc->sc_quirk |= RTKQ_DESCV2 | RTKQ_NOEECMD;
622 sc->sc_quirk |= RTKQ_NOJUMBO;
623 }
624
625 /* Set RX length mask */
626 sc->re_rxlenmask = RE_RDESC_STAT_GFRAGLEN;
627 sc->re_ldata.re_tx_desc_cnt = RE_TX_DESC_CNT_8169;
628 } else {
629 sc->sc_quirk |= RTKQ_NOJUMBO;
630
631 /* Set RX length mask */
632 sc->re_rxlenmask = RE_RDESC_STAT_FRAGLEN;
633 sc->re_ldata.re_tx_desc_cnt = RE_TX_DESC_CNT_8139;
634 }
635
636 /* Reset the adapter. */
637 re_reset(sc);
638
639 if ((sc->sc_quirk & RTKQ_NOEECMD) != 0) {
640 /*
641 * Get station address from ID registers.
642 */
643 for (i = 0; i < ETHER_ADDR_LEN; i++)
644 eaddr[i] = CSR_READ_1(sc, RTK_IDR0 + i);
645 } else {
646 /*
647 * Get station address from the EEPROM.
648 */
649 if (rtk_read_eeprom(sc, RTK_EE_ID, RTK_EEADDR_LEN1) == 0x8129)
650 addr_len = RTK_EEADDR_LEN1;
651 else
652 addr_len = RTK_EEADDR_LEN0;
653
654 /*
655 * Get station address from the EEPROM.
656 */
657 for (i = 0; i < ETHER_ADDR_LEN / 2; i++) {
658 val = rtk_read_eeprom(sc, RTK_EE_EADDR0 + i, addr_len);
659 eaddr[(i * 2) + 0] = val & 0xff;
660 eaddr[(i * 2) + 1] = val >> 8;
661 }
662 }
663
664 aprint_normal_dev(sc->sc_dev, "Ethernet address %s\n",
665 ether_sprintf(eaddr));
666
667 if (sc->re_ldata.re_tx_desc_cnt >
668 PAGE_SIZE / sizeof(struct re_desc)) {
669 sc->re_ldata.re_tx_desc_cnt =
670 PAGE_SIZE / sizeof(struct re_desc);
671 }
672
673 aprint_verbose_dev(sc->sc_dev, "using %d tx descriptors\n",
674 sc->re_ldata.re_tx_desc_cnt);
675 KASSERT(RE_NEXT_TX_DESC(sc, RE_TX_DESC_CNT(sc) - 1) == 0);
676
677 /* Allocate DMA'able memory for the TX ring */
678 if ((error = bus_dmamem_alloc(sc->sc_dmat, RE_TX_LIST_SZ(sc),
679 RE_RING_ALIGN, 0, &sc->re_ldata.re_tx_listseg, 1,
680 &sc->re_ldata.re_tx_listnseg, BUS_DMA_NOWAIT)) != 0) {
681 aprint_error_dev(sc->sc_dev,
682 "can't allocate tx listseg, error = %d\n", error);
683 goto fail_0;
684 }
685
686 /* Load the map for the TX ring. */
687 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->re_ldata.re_tx_listseg,
688 sc->re_ldata.re_tx_listnseg, RE_TX_LIST_SZ(sc),
689 (void **)&sc->re_ldata.re_tx_list,
690 BUS_DMA_COHERENT | BUS_DMA_NOWAIT)) != 0) {
691 aprint_error_dev(sc->sc_dev,
692 "can't map tx list, error = %d\n", error);
693 goto fail_1;
694 }
695 memset(sc->re_ldata.re_tx_list, 0, RE_TX_LIST_SZ(sc));
696
697 if ((error = bus_dmamap_create(sc->sc_dmat, RE_TX_LIST_SZ(sc), 1,
698 RE_TX_LIST_SZ(sc), 0, 0,
699 &sc->re_ldata.re_tx_list_map)) != 0) {
700 aprint_error_dev(sc->sc_dev,
701 "can't create tx list map, error = %d\n", error);
702 goto fail_2;
703 }
704
705
706 if ((error = bus_dmamap_load(sc->sc_dmat,
707 sc->re_ldata.re_tx_list_map, sc->re_ldata.re_tx_list,
708 RE_TX_LIST_SZ(sc), NULL, BUS_DMA_NOWAIT)) != 0) {
709 aprint_error_dev(sc->sc_dev,
710 "can't load tx list, error = %d\n", error);
711 goto fail_3;
712 }
713
714 /* Create DMA maps for TX buffers */
715 for (i = 0; i < RE_TX_QLEN; i++) {
716 error = bus_dmamap_create(sc->sc_dmat,
717 round_page(IP_MAXPACKET),
718 RE_TX_DESC_CNT(sc), RE_TDESC_CMD_FRAGLEN,
719 0, 0, &sc->re_ldata.re_txq[i].txq_dmamap);
720 if (error) {
721 aprint_error_dev(sc->sc_dev,
722 "can't create DMA map for TX\n");
723 goto fail_4;
724 }
725 }
726
727 /* Allocate DMA'able memory for the RX ring */
728 /* XXX see also a comment about RE_RX_DMAMEM_SZ in rtl81x9var.h */
729 if ((error = bus_dmamem_alloc(sc->sc_dmat,
730 RE_RX_DMAMEM_SZ, RE_RING_ALIGN, 0, &sc->re_ldata.re_rx_listseg, 1,
731 &sc->re_ldata.re_rx_listnseg, BUS_DMA_NOWAIT)) != 0) {
732 aprint_error_dev(sc->sc_dev,
733 "can't allocate rx listseg, error = %d\n", error);
734 goto fail_4;
735 }
736
737 /* Load the map for the RX ring. */
738 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->re_ldata.re_rx_listseg,
739 sc->re_ldata.re_rx_listnseg, RE_RX_DMAMEM_SZ,
740 (void **)&sc->re_ldata.re_rx_list,
741 BUS_DMA_COHERENT | BUS_DMA_NOWAIT)) != 0) {
742 aprint_error_dev(sc->sc_dev,
743 "can't map rx list, error = %d\n", error);
744 goto fail_5;
745 }
746 memset(sc->re_ldata.re_rx_list, 0, RE_RX_DMAMEM_SZ);
747
748 if ((error = bus_dmamap_create(sc->sc_dmat,
749 RE_RX_DMAMEM_SZ, 1, RE_RX_DMAMEM_SZ, 0, 0,
750 &sc->re_ldata.re_rx_list_map)) != 0) {
751 aprint_error_dev(sc->sc_dev,
752 "can't create rx list map, error = %d\n", error);
753 goto fail_6;
754 }
755
756 if ((error = bus_dmamap_load(sc->sc_dmat,
757 sc->re_ldata.re_rx_list_map, sc->re_ldata.re_rx_list,
758 RE_RX_DMAMEM_SZ, NULL, BUS_DMA_NOWAIT)) != 0) {
759 aprint_error_dev(sc->sc_dev,
760 "can't load rx list, error = %d\n", error);
761 goto fail_7;
762 }
763
764 /* Create DMA maps for RX buffers */
765 for (i = 0; i < RE_RX_DESC_CNT; i++) {
766 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES,
767 0, 0, &sc->re_ldata.re_rxsoft[i].rxs_dmamap);
768 if (error) {
769 aprint_error_dev(sc->sc_dev,
770 "can't create DMA map for RX\n");
771 goto fail_8;
772 }
773 }
774
775 /*
776 * Record interface as attached. From here, we should not fail.
777 */
778 sc->sc_flags |= RTK_ATTACHED;
779
780 ifp = &sc->ethercom.ec_if;
781 ifp->if_softc = sc;
782 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ);
783 ifp->if_mtu = ETHERMTU;
784 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
785 ifp->if_ioctl = re_ioctl;
786 sc->ethercom.ec_capabilities |=
787 ETHERCAP_VLAN_MTU | ETHERCAP_VLAN_HWTAGGING;
788 ifp->if_start = re_start;
789 ifp->if_stop = re_stop;
790
791 /*
792 * IFCAP_CSUM_IPv4_Tx on re(4) is broken for small packets,
793 * so we have a workaround to handle the bug by padding
794 * such packets manually.
795 */
796 ifp->if_capabilities |=
797 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx |
798 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx |
799 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx |
800 IFCAP_TSOv4;
801
802 /*
803 * XXX
804 * Still have no idea how to make TSO work on 8168C, 8168CP,
805 * 8102E, 8111C and 8111CP.
806 */
807 if ((sc->sc_quirk & RTKQ_DESCV2) != 0)
808 ifp->if_capabilities &= ~IFCAP_TSOv4;
809
810 ifp->if_watchdog = re_watchdog;
811 ifp->if_init = re_init;
812 ifp->if_snd.ifq_maxlen = RE_IFQ_MAXLEN;
813 ifp->if_capenable = ifp->if_capabilities;
814 IFQ_SET_READY(&ifp->if_snd);
815
816 callout_init(&sc->rtk_tick_ch, 0);
817
818 /* Do MII setup */
819 sc->mii.mii_ifp = ifp;
820 sc->mii.mii_readreg = re_miibus_readreg;
821 sc->mii.mii_writereg = re_miibus_writereg;
822 sc->mii.mii_statchg = re_miibus_statchg;
823 sc->ethercom.ec_mii = &sc->mii;
824 ifmedia_init(&sc->mii.mii_media, IFM_IMASK, ether_mediachange,
825 ether_mediastatus);
826 mii_attach(sc->sc_dev, &sc->mii, 0xffffffff, MII_PHY_ANY,
827 MII_OFFSET_ANY, 0);
828 ifmedia_set(&sc->mii.mii_media, IFM_ETHER | IFM_AUTO);
829
830 /*
831 * Call MI attach routine.
832 */
833 if_attach(ifp);
834 ether_ifattach(ifp, eaddr);
835
836 if (pmf_device_register(sc->sc_dev, NULL, NULL))
837 pmf_class_network_register(sc->sc_dev, ifp);
838 else
839 aprint_error_dev(sc->sc_dev,
840 "couldn't establish power handler\n");
841
842 return;
843
844 fail_8:
845 /* Destroy DMA maps for RX buffers. */
846 for (i = 0; i < RE_RX_DESC_CNT; i++)
847 if (sc->re_ldata.re_rxsoft[i].rxs_dmamap != NULL)
848 bus_dmamap_destroy(sc->sc_dmat,
849 sc->re_ldata.re_rxsoft[i].rxs_dmamap);
850
851 /* Free DMA'able memory for the RX ring. */
852 bus_dmamap_unload(sc->sc_dmat, sc->re_ldata.re_rx_list_map);
853 fail_7:
854 bus_dmamap_destroy(sc->sc_dmat, sc->re_ldata.re_rx_list_map);
855 fail_6:
856 bus_dmamem_unmap(sc->sc_dmat,
857 (void *)sc->re_ldata.re_rx_list, RE_RX_DMAMEM_SZ);
858 fail_5:
859 bus_dmamem_free(sc->sc_dmat,
860 &sc->re_ldata.re_rx_listseg, sc->re_ldata.re_rx_listnseg);
861
862 fail_4:
863 /* Destroy DMA maps for TX buffers. */
864 for (i = 0; i < RE_TX_QLEN; i++)
865 if (sc->re_ldata.re_txq[i].txq_dmamap != NULL)
866 bus_dmamap_destroy(sc->sc_dmat,
867 sc->re_ldata.re_txq[i].txq_dmamap);
868
869 /* Free DMA'able memory for the TX ring. */
870 bus_dmamap_unload(sc->sc_dmat, sc->re_ldata.re_tx_list_map);
871 fail_3:
872 bus_dmamap_destroy(sc->sc_dmat, sc->re_ldata.re_tx_list_map);
873 fail_2:
874 bus_dmamem_unmap(sc->sc_dmat,
875 (void *)sc->re_ldata.re_tx_list, RE_TX_LIST_SZ(sc));
876 fail_1:
877 bus_dmamem_free(sc->sc_dmat,
878 &sc->re_ldata.re_tx_listseg, sc->re_ldata.re_tx_listnseg);
879 fail_0:
880 return;
881 }
882
883
884 /*
885 * re_activate:
886 * Handle device activation/deactivation requests.
887 */
888 int
889 re_activate(device_t self, enum devact act)
890 {
891 struct rtk_softc *sc = device_private(self);
892
893 switch (act) {
894 case DVACT_DEACTIVATE:
895 if_deactivate(&sc->ethercom.ec_if);
896 return 0;
897 default:
898 return EOPNOTSUPP;
899 }
900 }
901
902 /*
903 * re_detach:
904 * Detach a rtk interface.
905 */
906 int
907 re_detach(struct rtk_softc *sc)
908 {
909 struct ifnet *ifp = &sc->ethercom.ec_if;
910 int i;
911
912 /*
913 * Succeed now if there isn't any work to do.
914 */
915 if ((sc->sc_flags & RTK_ATTACHED) == 0)
916 return 0;
917
918 /* Unhook our tick handler. */
919 callout_stop(&sc->rtk_tick_ch);
920
921 /* Detach all PHYs. */
922 mii_detach(&sc->mii, MII_PHY_ANY, MII_OFFSET_ANY);
923
924 /* Delete all remaining media. */
925 ifmedia_delete_instance(&sc->mii.mii_media, IFM_INST_ANY);
926
927 ether_ifdetach(ifp);
928 if_detach(ifp);
929
930 /* Destroy DMA maps for RX buffers. */
931 for (i = 0; i < RE_RX_DESC_CNT; i++)
932 if (sc->re_ldata.re_rxsoft[i].rxs_dmamap != NULL)
933 bus_dmamap_destroy(sc->sc_dmat,
934 sc->re_ldata.re_rxsoft[i].rxs_dmamap);
935
936 /* Free DMA'able memory for the RX ring. */
937 bus_dmamap_unload(sc->sc_dmat, sc->re_ldata.re_rx_list_map);
938 bus_dmamap_destroy(sc->sc_dmat, sc->re_ldata.re_rx_list_map);
939 bus_dmamem_unmap(sc->sc_dmat,
940 (void *)sc->re_ldata.re_rx_list, RE_RX_DMAMEM_SZ);
941 bus_dmamem_free(sc->sc_dmat,
942 &sc->re_ldata.re_rx_listseg, sc->re_ldata.re_rx_listnseg);
943
944 /* Destroy DMA maps for TX buffers. */
945 for (i = 0; i < RE_TX_QLEN; i++)
946 if (sc->re_ldata.re_txq[i].txq_dmamap != NULL)
947 bus_dmamap_destroy(sc->sc_dmat,
948 sc->re_ldata.re_txq[i].txq_dmamap);
949
950 /* Free DMA'able memory for the TX ring. */
951 bus_dmamap_unload(sc->sc_dmat, sc->re_ldata.re_tx_list_map);
952 bus_dmamap_destroy(sc->sc_dmat, sc->re_ldata.re_tx_list_map);
953 bus_dmamem_unmap(sc->sc_dmat,
954 (void *)sc->re_ldata.re_tx_list, RE_TX_LIST_SZ(sc));
955 bus_dmamem_free(sc->sc_dmat,
956 &sc->re_ldata.re_tx_listseg, sc->re_ldata.re_tx_listnseg);
957
958 pmf_device_deregister(sc->sc_dev);
959
960 return 0;
961 }
962
963 /*
964 * re_enable:
965 * Enable the RTL81X9 chip.
966 */
967 static int
968 re_enable(struct rtk_softc *sc)
969 {
970
971 if (RTK_IS_ENABLED(sc) == 0 && sc->sc_enable != NULL) {
972 if ((*sc->sc_enable)(sc) != 0) {
973 printf("%s: device enable failed\n",
974 device_xname(sc->sc_dev));
975 return EIO;
976 }
977 sc->sc_flags |= RTK_ENABLED;
978 }
979 return 0;
980 }
981
982 /*
983 * re_disable:
984 * Disable the RTL81X9 chip.
985 */
986 static void
987 re_disable(struct rtk_softc *sc)
988 {
989
990 if (RTK_IS_ENABLED(sc) && sc->sc_disable != NULL) {
991 (*sc->sc_disable)(sc);
992 sc->sc_flags &= ~RTK_ENABLED;
993 }
994 }
995
996 static int
997 re_newbuf(struct rtk_softc *sc, int idx, struct mbuf *m)
998 {
999 struct mbuf *n = NULL;
1000 bus_dmamap_t map;
1001 struct re_desc *d;
1002 struct re_rxsoft *rxs;
1003 uint32_t cmdstat;
1004 int error;
1005
1006 if (m == NULL) {
1007 MGETHDR(n, M_DONTWAIT, MT_DATA);
1008 if (n == NULL)
1009 return ENOBUFS;
1010
1011 MCLGET(n, M_DONTWAIT);
1012 if ((n->m_flags & M_EXT) == 0) {
1013 m_freem(n);
1014 return ENOBUFS;
1015 }
1016 m = n;
1017 } else
1018 m->m_data = m->m_ext.ext_buf;
1019
1020 /*
1021 * Initialize mbuf length fields and fixup
1022 * alignment so that the frame payload is
1023 * longword aligned.
1024 */
1025 m->m_len = m->m_pkthdr.len = MCLBYTES - RE_ETHER_ALIGN;
1026 m->m_data += RE_ETHER_ALIGN;
1027
1028 rxs = &sc->re_ldata.re_rxsoft[idx];
1029 map = rxs->rxs_dmamap;
1030 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m,
1031 BUS_DMA_READ|BUS_DMA_NOWAIT);
1032
1033 if (error)
1034 goto out;
1035
1036 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize,
1037 BUS_DMASYNC_PREREAD);
1038
1039 d = &sc->re_ldata.re_rx_list[idx];
1040 #ifdef DIAGNOSTIC
1041 RE_RXDESCSYNC(sc, idx, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
1042 cmdstat = le32toh(d->re_cmdstat);
1043 RE_RXDESCSYNC(sc, idx, BUS_DMASYNC_PREREAD);
1044 if (cmdstat & RE_RDESC_STAT_OWN) {
1045 panic("%s: tried to map busy RX descriptor",
1046 device_xname(sc->sc_dev));
1047 }
1048 #endif
1049
1050 rxs->rxs_mbuf = m;
1051
1052 d->re_vlanctl = 0;
1053 cmdstat = map->dm_segs[0].ds_len;
1054 if (idx == (RE_RX_DESC_CNT - 1))
1055 cmdstat |= RE_RDESC_CMD_EOR;
1056 re_set_bufaddr(d, map->dm_segs[0].ds_addr);
1057 d->re_cmdstat = htole32(cmdstat);
1058 RE_RXDESCSYNC(sc, idx, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
1059 cmdstat |= RE_RDESC_CMD_OWN;
1060 d->re_cmdstat = htole32(cmdstat);
1061 RE_RXDESCSYNC(sc, idx, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
1062
1063 return 0;
1064 out:
1065 if (n != NULL)
1066 m_freem(n);
1067 return ENOMEM;
1068 }
1069
1070 static int
1071 re_tx_list_init(struct rtk_softc *sc)
1072 {
1073 int i;
1074
1075 memset(sc->re_ldata.re_tx_list, 0, RE_TX_LIST_SZ(sc));
1076 for (i = 0; i < RE_TX_QLEN; i++) {
1077 sc->re_ldata.re_txq[i].txq_mbuf = NULL;
1078 }
1079
1080 bus_dmamap_sync(sc->sc_dmat,
1081 sc->re_ldata.re_tx_list_map, 0,
1082 sc->re_ldata.re_tx_list_map->dm_mapsize,
1083 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
1084 sc->re_ldata.re_txq_prodidx = 0;
1085 sc->re_ldata.re_txq_considx = 0;
1086 sc->re_ldata.re_txq_free = RE_TX_QLEN;
1087 sc->re_ldata.re_tx_free = RE_TX_DESC_CNT(sc);
1088 sc->re_ldata.re_tx_nextfree = 0;
1089
1090 return 0;
1091 }
1092
1093 static int
1094 re_rx_list_init(struct rtk_softc *sc)
1095 {
1096 int i;
1097
1098 memset(sc->re_ldata.re_rx_list, 0, RE_RX_LIST_SZ);
1099
1100 for (i = 0; i < RE_RX_DESC_CNT; i++) {
1101 if (re_newbuf(sc, i, NULL) == ENOBUFS)
1102 return ENOBUFS;
1103 }
1104
1105 sc->re_ldata.re_rx_prodidx = 0;
1106 sc->re_head = sc->re_tail = NULL;
1107
1108 return 0;
1109 }
1110
1111 /*
1112 * RX handler for C+ and 8169. For the gigE chips, we support
1113 * the reception of jumbo frames that have been fragmented
1114 * across multiple 2K mbuf cluster buffers.
1115 */
1116 static void
1117 re_rxeof(struct rtk_softc *sc)
1118 {
1119 struct mbuf *m;
1120 struct ifnet *ifp;
1121 int i, total_len;
1122 struct re_desc *cur_rx;
1123 struct re_rxsoft *rxs;
1124 uint32_t rxstat, rxvlan;
1125
1126 ifp = &sc->ethercom.ec_if;
1127
1128 for (i = sc->re_ldata.re_rx_prodidx;; i = RE_NEXT_RX_DESC(sc, i)) {
1129 cur_rx = &sc->re_ldata.re_rx_list[i];
1130 RE_RXDESCSYNC(sc, i,
1131 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
1132 rxstat = le32toh(cur_rx->re_cmdstat);
1133 rxvlan = le32toh(cur_rx->re_vlanctl);
1134 RE_RXDESCSYNC(sc, i, BUS_DMASYNC_PREREAD);
1135 if ((rxstat & RE_RDESC_STAT_OWN) != 0) {
1136 break;
1137 }
1138 total_len = rxstat & sc->re_rxlenmask;
1139 rxs = &sc->re_ldata.re_rxsoft[i];
1140 m = rxs->rxs_mbuf;
1141
1142 /* Invalidate the RX mbuf and unload its map */
1143
1144 bus_dmamap_sync(sc->sc_dmat,
1145 rxs->rxs_dmamap, 0, rxs->rxs_dmamap->dm_mapsize,
1146 BUS_DMASYNC_POSTREAD);
1147 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap);
1148
1149 if ((rxstat & RE_RDESC_STAT_EOF) == 0) {
1150 m->m_len = MCLBYTES - RE_ETHER_ALIGN;
1151 if (sc->re_head == NULL)
1152 sc->re_head = sc->re_tail = m;
1153 else {
1154 m->m_flags &= ~M_PKTHDR;
1155 sc->re_tail->m_next = m;
1156 sc->re_tail = m;
1157 }
1158 re_newbuf(sc, i, NULL);
1159 continue;
1160 }
1161
1162 /*
1163 * NOTE: for the 8139C+, the frame length field
1164 * is always 12 bits in size, but for the gigE chips,
1165 * it is 13 bits (since the max RX frame length is 16K).
1166 * Unfortunately, all 32 bits in the status word
1167 * were already used, so to make room for the extra
1168 * length bit, RealTek took out the 'frame alignment
1169 * error' bit and shifted the other status bits
1170 * over one slot. The OWN, EOR, FS and LS bits are
1171 * still in the same places. We have already extracted
1172 * the frame length and checked the OWN bit, so rather
1173 * than using an alternate bit mapping, we shift the
1174 * status bits one space to the right so we can evaluate
1175 * them using the 8169 status as though it was in the
1176 * same format as that of the 8139C+.
1177 */
1178 if ((sc->sc_quirk & RTKQ_8139CPLUS) == 0)
1179 rxstat >>= 1;
1180
1181 if (__predict_false((rxstat & RE_RDESC_STAT_RXERRSUM) != 0)) {
1182 #ifdef RE_DEBUG
1183 printf("%s: RX error (rxstat = 0x%08x)",
1184 device_xname(sc->sc_dev), rxstat);
1185 if (rxstat & RE_RDESC_STAT_FRALIGN)
1186 printf(", frame alignment error");
1187 if (rxstat & RE_RDESC_STAT_BUFOFLOW)
1188 printf(", out of buffer space");
1189 if (rxstat & RE_RDESC_STAT_FIFOOFLOW)
1190 printf(", FIFO overrun");
1191 if (rxstat & RE_RDESC_STAT_GIANT)
1192 printf(", giant packet");
1193 if (rxstat & RE_RDESC_STAT_RUNT)
1194 printf(", runt packet");
1195 if (rxstat & RE_RDESC_STAT_CRCERR)
1196 printf(", CRC error");
1197 printf("\n");
1198 #endif
1199 ifp->if_ierrors++;
1200 /*
1201 * If this is part of a multi-fragment packet,
1202 * discard all the pieces.
1203 */
1204 if (sc->re_head != NULL) {
1205 m_freem(sc->re_head);
1206 sc->re_head = sc->re_tail = NULL;
1207 }
1208 re_newbuf(sc, i, m);
1209 continue;
1210 }
1211
1212 /*
1213 * If allocating a replacement mbuf fails,
1214 * reload the current one.
1215 */
1216
1217 if (__predict_false(re_newbuf(sc, i, NULL) != 0)) {
1218 ifp->if_ierrors++;
1219 if (sc->re_head != NULL) {
1220 m_freem(sc->re_head);
1221 sc->re_head = sc->re_tail = NULL;
1222 }
1223 re_newbuf(sc, i, m);
1224 continue;
1225 }
1226
1227 if (sc->re_head != NULL) {
1228 m->m_len = total_len % (MCLBYTES - RE_ETHER_ALIGN);
1229 /*
1230 * Special case: if there's 4 bytes or less
1231 * in this buffer, the mbuf can be discarded:
1232 * the last 4 bytes is the CRC, which we don't
1233 * care about anyway.
1234 */
1235 if (m->m_len <= ETHER_CRC_LEN) {
1236 sc->re_tail->m_len -=
1237 (ETHER_CRC_LEN - m->m_len);
1238 m_freem(m);
1239 } else {
1240 m->m_len -= ETHER_CRC_LEN;
1241 m->m_flags &= ~M_PKTHDR;
1242 sc->re_tail->m_next = m;
1243 }
1244 m = sc->re_head;
1245 sc->re_head = sc->re_tail = NULL;
1246 m->m_pkthdr.len = total_len - ETHER_CRC_LEN;
1247 } else
1248 m->m_pkthdr.len = m->m_len =
1249 (total_len - ETHER_CRC_LEN);
1250
1251 ifp->if_ipackets++;
1252 m->m_pkthdr.rcvif = ifp;
1253
1254 /* Do RX checksumming */
1255 if ((sc->sc_quirk & RTKQ_DESCV2) == 0) {
1256 /* Check IP header checksum */
1257 if ((rxstat & RE_RDESC_STAT_PROTOID) != 0) {
1258 m->m_pkthdr.csum_flags |= M_CSUM_IPv4;
1259 if (rxstat & RE_RDESC_STAT_IPSUMBAD)
1260 m->m_pkthdr.csum_flags |=
1261 M_CSUM_IPv4_BAD;
1262
1263 /* Check TCP/UDP checksum */
1264 if (RE_TCPPKT(rxstat)) {
1265 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4;
1266 if (rxstat & RE_RDESC_STAT_TCPSUMBAD)
1267 m->m_pkthdr.csum_flags |=
1268 M_CSUM_TCP_UDP_BAD;
1269 } else if (RE_UDPPKT(rxstat)) {
1270 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4;
1271 if (rxstat & RE_RDESC_STAT_UDPSUMBAD)
1272 m->m_pkthdr.csum_flags |=
1273 M_CSUM_TCP_UDP_BAD;
1274 }
1275 }
1276 } else {
1277 /* Check IPv4 header checksum */
1278 if ((rxvlan & RE_RDESC_VLANCTL_IPV4) != 0) {
1279 m->m_pkthdr.csum_flags |= M_CSUM_IPv4;
1280 if (rxstat & RE_RDESC_STAT_IPSUMBAD)
1281 m->m_pkthdr.csum_flags |=
1282 M_CSUM_IPv4_BAD;
1283
1284 /* Check TCPv4/UDPv4 checksum */
1285 if (RE_TCPPKT(rxstat)) {
1286 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4;
1287 if (rxstat & RE_RDESC_STAT_TCPSUMBAD)
1288 m->m_pkthdr.csum_flags |=
1289 M_CSUM_TCP_UDP_BAD;
1290 } else if (RE_UDPPKT(rxstat)) {
1291 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4;
1292 if (rxstat & RE_RDESC_STAT_UDPSUMBAD)
1293 m->m_pkthdr.csum_flags |=
1294 M_CSUM_TCP_UDP_BAD;
1295 }
1296 }
1297 /* XXX Check TCPv6/UDPv6 checksum? */
1298 }
1299
1300 if (rxvlan & RE_RDESC_VLANCTL_TAG) {
1301 VLAN_INPUT_TAG(ifp, m,
1302 bswap16(rxvlan & RE_RDESC_VLANCTL_DATA),
1303 continue);
1304 }
1305 #if NBPFILTER > 0
1306 if (ifp->if_bpf)
1307 bpf_mtap(ifp->if_bpf, m);
1308 #endif
1309 (*ifp->if_input)(ifp, m);
1310 }
1311
1312 sc->re_ldata.re_rx_prodidx = i;
1313 }
1314
1315 static void
1316 re_txeof(struct rtk_softc *sc)
1317 {
1318 struct ifnet *ifp;
1319 struct re_txq *txq;
1320 uint32_t txstat;
1321 int idx, descidx;
1322
1323 ifp = &sc->ethercom.ec_if;
1324
1325 for (idx = sc->re_ldata.re_txq_considx;
1326 sc->re_ldata.re_txq_free < RE_TX_QLEN;
1327 idx = RE_NEXT_TXQ(sc, idx), sc->re_ldata.re_txq_free++) {
1328 txq = &sc->re_ldata.re_txq[idx];
1329 KASSERT(txq->txq_mbuf != NULL);
1330
1331 descidx = txq->txq_descidx;
1332 RE_TXDESCSYNC(sc, descidx,
1333 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
1334 txstat =
1335 le32toh(sc->re_ldata.re_tx_list[descidx].re_cmdstat);
1336 RE_TXDESCSYNC(sc, descidx, BUS_DMASYNC_PREREAD);
1337 KASSERT((txstat & RE_TDESC_CMD_EOF) != 0);
1338 if (txstat & RE_TDESC_CMD_OWN) {
1339 break;
1340 }
1341
1342 sc->re_ldata.re_tx_free += txq->txq_nsegs;
1343 KASSERT(sc->re_ldata.re_tx_free <= RE_TX_DESC_CNT(sc));
1344 bus_dmamap_sync(sc->sc_dmat, txq->txq_dmamap,
1345 0, txq->txq_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE);
1346 bus_dmamap_unload(sc->sc_dmat, txq->txq_dmamap);
1347 m_freem(txq->txq_mbuf);
1348 txq->txq_mbuf = NULL;
1349
1350 if (txstat & (RE_TDESC_STAT_EXCESSCOL | RE_TDESC_STAT_COLCNT))
1351 ifp->if_collisions++;
1352 if (txstat & RE_TDESC_STAT_TXERRSUM)
1353 ifp->if_oerrors++;
1354 else
1355 ifp->if_opackets++;
1356 }
1357
1358 sc->re_ldata.re_txq_considx = idx;
1359
1360 if (sc->re_ldata.re_txq_free > RE_NTXDESC_RSVD)
1361 ifp->if_flags &= ~IFF_OACTIVE;
1362
1363 /*
1364 * If not all descriptors have been released reaped yet,
1365 * reload the timer so that we will eventually get another
1366 * interrupt that will cause us to re-enter this routine.
1367 * This is done in case the transmitter has gone idle.
1368 */
1369 if (sc->re_ldata.re_txq_free < RE_TX_QLEN) {
1370 CSR_WRITE_4(sc, RTK_TIMERCNT, 1);
1371 if ((sc->sc_quirk & RTKQ_PCIE) != 0) {
1372 /*
1373 * Some chips will ignore a second TX request
1374 * issued while an existing transmission is in
1375 * progress. If the transmitter goes idle but
1376 * there are still packets waiting to be sent,
1377 * we need to restart the channel here to flush
1378 * them out. This only seems to be required with
1379 * the PCIe devices.
1380 */
1381 CSR_WRITE_1(sc, RTK_GTXSTART, RTK_TXSTART_START);
1382 }
1383 } else
1384 ifp->if_timer = 0;
1385 }
1386
1387 static void
1388 re_tick(void *arg)
1389 {
1390 struct rtk_softc *sc = arg;
1391 int s;
1392
1393 /* XXX: just return for 8169S/8110S with rev 2 or newer phy */
1394 s = splnet();
1395
1396 mii_tick(&sc->mii);
1397 splx(s);
1398
1399 callout_reset(&sc->rtk_tick_ch, hz, re_tick, sc);
1400 }
1401
1402 int
1403 re_intr(void *arg)
1404 {
1405 struct rtk_softc *sc = arg;
1406 struct ifnet *ifp;
1407 uint16_t status;
1408 int handled = 0;
1409
1410 if (!device_has_power(sc->sc_dev))
1411 return 0;
1412
1413 ifp = &sc->ethercom.ec_if;
1414
1415 if ((ifp->if_flags & IFF_UP) == 0)
1416 return 0;
1417
1418 for (;;) {
1419
1420 status = CSR_READ_2(sc, RTK_ISR);
1421 /* If the card has gone away the read returns 0xffff. */
1422 if (status == 0xffff)
1423 break;
1424 if (status) {
1425 handled = 1;
1426 CSR_WRITE_2(sc, RTK_ISR, status);
1427 }
1428
1429 if ((status & RTK_INTRS_CPLUS) == 0)
1430 break;
1431
1432 if (status & (RTK_ISR_RX_OK | RTK_ISR_RX_ERR))
1433 re_rxeof(sc);
1434
1435 if (status & (RTK_ISR_TIMEOUT_EXPIRED | RTK_ISR_TX_ERR |
1436 RTK_ISR_TX_DESC_UNAVAIL))
1437 re_txeof(sc);
1438
1439 if (status & RTK_ISR_SYSTEM_ERR) {
1440 re_init(ifp);
1441 }
1442
1443 if (status & RTK_ISR_LINKCHG) {
1444 callout_stop(&sc->rtk_tick_ch);
1445 re_tick(sc);
1446 }
1447 }
1448
1449 if (handled && !IFQ_IS_EMPTY(&ifp->if_snd))
1450 re_start(ifp);
1451
1452 return handled;
1453 }
1454
1455
1456
1457 /*
1458 * Main transmit routine for C+ and gigE NICs.
1459 */
1460
1461 static void
1462 re_start(struct ifnet *ifp)
1463 {
1464 struct rtk_softc *sc;
1465 struct mbuf *m;
1466 bus_dmamap_t map;
1467 struct re_txq *txq;
1468 struct re_desc *d;
1469 struct m_tag *mtag;
1470 uint32_t cmdstat, re_flags, vlanctl;
1471 int ofree, idx, error, nsegs, seg;
1472 int startdesc, curdesc, lastdesc;
1473 bool pad;
1474
1475 sc = ifp->if_softc;
1476 ofree = sc->re_ldata.re_txq_free;
1477
1478 for (idx = sc->re_ldata.re_txq_prodidx;; idx = RE_NEXT_TXQ(sc, idx)) {
1479
1480 IFQ_POLL(&ifp->if_snd, m);
1481 if (m == NULL)
1482 break;
1483
1484 if (sc->re_ldata.re_txq_free == 0 ||
1485 sc->re_ldata.re_tx_free == 0) {
1486 /* no more free slots left */
1487 ifp->if_flags |= IFF_OACTIVE;
1488 break;
1489 }
1490
1491 /*
1492 * Set up checksum offload. Note: checksum offload bits must
1493 * appear in all descriptors of a multi-descriptor transmit
1494 * attempt. (This is according to testing done with an 8169
1495 * chip. I'm not sure if this is a requirement or a bug.)
1496 */
1497
1498 vlanctl = 0;
1499 if ((m->m_pkthdr.csum_flags & M_CSUM_TSOv4) != 0) {
1500 uint32_t segsz = m->m_pkthdr.segsz;
1501
1502 re_flags = RE_TDESC_CMD_LGSEND |
1503 (segsz << RE_TDESC_CMD_MSSVAL_SHIFT);
1504 } else {
1505 /*
1506 * set RE_TDESC_CMD_IPCSUM if any checksum offloading
1507 * is requested. otherwise, RE_TDESC_CMD_TCPCSUM/
1508 * RE_TDESC_CMD_UDPCSUM doesn't make effects.
1509 */
1510 re_flags = 0;
1511 if ((m->m_pkthdr.csum_flags &
1512 (M_CSUM_IPv4 | M_CSUM_TCPv4 | M_CSUM_UDPv4))
1513 != 0) {
1514 if ((sc->sc_quirk & RTKQ_DESCV2) == 0) {
1515 re_flags |= RE_TDESC_CMD_IPCSUM;
1516 if (m->m_pkthdr.csum_flags &
1517 M_CSUM_TCPv4) {
1518 re_flags |=
1519 RE_TDESC_CMD_TCPCSUM;
1520 } else if (m->m_pkthdr.csum_flags &
1521 M_CSUM_UDPv4) {
1522 re_flags |=
1523 RE_TDESC_CMD_UDPCSUM;
1524 }
1525 } else {
1526 vlanctl |= RE_TDESC_VLANCTL_IPCSUM;
1527 if (m->m_pkthdr.csum_flags &
1528 M_CSUM_TCPv4) {
1529 vlanctl |=
1530 RE_TDESC_VLANCTL_TCPCSUM;
1531 } else if (m->m_pkthdr.csum_flags &
1532 M_CSUM_UDPv4) {
1533 vlanctl |=
1534 RE_TDESC_VLANCTL_UDPCSUM;
1535 }
1536 }
1537 }
1538 }
1539
1540 txq = &sc->re_ldata.re_txq[idx];
1541 map = txq->txq_dmamap;
1542 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m,
1543 BUS_DMA_WRITE|BUS_DMA_NOWAIT);
1544
1545 if (__predict_false(error)) {
1546 /* XXX try to defrag if EFBIG? */
1547 printf("%s: can't map mbuf (error %d)\n",
1548 device_xname(sc->sc_dev), error);
1549
1550 IFQ_DEQUEUE(&ifp->if_snd, m);
1551 m_freem(m);
1552 ifp->if_oerrors++;
1553 continue;
1554 }
1555
1556 nsegs = map->dm_nsegs;
1557 pad = false;
1558 if (__predict_false(m->m_pkthdr.len <= RE_IP4CSUMTX_PADLEN &&
1559 (re_flags & RE_TDESC_CMD_IPCSUM) != 0 &&
1560 (sc->sc_quirk & RTKQ_DESCV2) == 0)) {
1561 pad = true;
1562 nsegs++;
1563 }
1564
1565 if (nsegs > sc->re_ldata.re_tx_free) {
1566 /*
1567 * Not enough free descriptors to transmit this packet.
1568 */
1569 ifp->if_flags |= IFF_OACTIVE;
1570 bus_dmamap_unload(sc->sc_dmat, map);
1571 break;
1572 }
1573
1574 IFQ_DEQUEUE(&ifp->if_snd, m);
1575
1576 /*
1577 * Make sure that the caches are synchronized before we
1578 * ask the chip to start DMA for the packet data.
1579 */
1580 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize,
1581 BUS_DMASYNC_PREWRITE);
1582
1583 /*
1584 * Set up hardware VLAN tagging. Note: vlan tag info must
1585 * appear in all descriptors of a multi-descriptor
1586 * transmission attempt.
1587 */
1588 if ((mtag = VLAN_OUTPUT_TAG(&sc->ethercom, m)) != NULL)
1589 vlanctl |= bswap16(VLAN_TAG_VALUE(mtag)) |
1590 RE_TDESC_VLANCTL_TAG;
1591
1592 /*
1593 * Map the segment array into descriptors.
1594 * Note that we set the start-of-frame and
1595 * end-of-frame markers for either TX or RX,
1596 * but they really only have meaning in the TX case.
1597 * (In the RX case, it's the chip that tells us
1598 * where packets begin and end.)
1599 * We also keep track of the end of the ring
1600 * and set the end-of-ring bits as needed,
1601 * and we set the ownership bits in all except
1602 * the very first descriptor. (The caller will
1603 * set this descriptor later when it start
1604 * transmission or reception.)
1605 */
1606 curdesc = startdesc = sc->re_ldata.re_tx_nextfree;
1607 lastdesc = -1;
1608 for (seg = 0; seg < map->dm_nsegs;
1609 seg++, curdesc = RE_NEXT_TX_DESC(sc, curdesc)) {
1610 d = &sc->re_ldata.re_tx_list[curdesc];
1611 #ifdef DIAGNOSTIC
1612 RE_TXDESCSYNC(sc, curdesc,
1613 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
1614 cmdstat = le32toh(d->re_cmdstat);
1615 RE_TXDESCSYNC(sc, curdesc, BUS_DMASYNC_PREREAD);
1616 if (cmdstat & RE_TDESC_STAT_OWN) {
1617 panic("%s: tried to map busy TX descriptor",
1618 device_xname(sc->sc_dev));
1619 }
1620 #endif
1621
1622 d->re_vlanctl = htole32(vlanctl);
1623 re_set_bufaddr(d, map->dm_segs[seg].ds_addr);
1624 cmdstat = re_flags | map->dm_segs[seg].ds_len;
1625 if (seg == 0)
1626 cmdstat |= RE_TDESC_CMD_SOF;
1627 else
1628 cmdstat |= RE_TDESC_CMD_OWN;
1629 if (curdesc == (RE_TX_DESC_CNT(sc) - 1))
1630 cmdstat |= RE_TDESC_CMD_EOR;
1631 if (seg == nsegs - 1) {
1632 cmdstat |= RE_TDESC_CMD_EOF;
1633 lastdesc = curdesc;
1634 }
1635 d->re_cmdstat = htole32(cmdstat);
1636 RE_TXDESCSYNC(sc, curdesc,
1637 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
1638 }
1639 if (__predict_false(pad)) {
1640 d = &sc->re_ldata.re_tx_list[curdesc];
1641 d->re_vlanctl = htole32(vlanctl);
1642 re_set_bufaddr(d, RE_TXPADDADDR(sc));
1643 cmdstat = re_flags |
1644 RE_TDESC_CMD_OWN | RE_TDESC_CMD_EOF |
1645 (RE_IP4CSUMTX_PADLEN + 1 - m->m_pkthdr.len);
1646 if (curdesc == (RE_TX_DESC_CNT(sc) - 1))
1647 cmdstat |= RE_TDESC_CMD_EOR;
1648 d->re_cmdstat = htole32(cmdstat);
1649 RE_TXDESCSYNC(sc, curdesc,
1650 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
1651 lastdesc = curdesc;
1652 curdesc = RE_NEXT_TX_DESC(sc, curdesc);
1653 }
1654 KASSERT(lastdesc != -1);
1655
1656 /* Transfer ownership of packet to the chip. */
1657
1658 sc->re_ldata.re_tx_list[startdesc].re_cmdstat |=
1659 htole32(RE_TDESC_CMD_OWN);
1660 RE_TXDESCSYNC(sc, startdesc,
1661 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
1662
1663 /* update info of TX queue and descriptors */
1664 txq->txq_mbuf = m;
1665 txq->txq_descidx = lastdesc;
1666 txq->txq_nsegs = nsegs;
1667
1668 sc->re_ldata.re_txq_free--;
1669 sc->re_ldata.re_tx_free -= nsegs;
1670 sc->re_ldata.re_tx_nextfree = curdesc;
1671
1672 #if NBPFILTER > 0
1673 /*
1674 * If there's a BPF listener, bounce a copy of this frame
1675 * to him.
1676 */
1677 if (ifp->if_bpf)
1678 bpf_mtap(ifp->if_bpf, m);
1679 #endif
1680 }
1681
1682 if (sc->re_ldata.re_txq_free < ofree) {
1683 /*
1684 * TX packets are enqueued.
1685 */
1686 sc->re_ldata.re_txq_prodidx = idx;
1687
1688 /*
1689 * Start the transmitter to poll.
1690 *
1691 * RealTek put the TX poll request register in a different
1692 * location on the 8169 gigE chip. I don't know why.
1693 */
1694 if ((sc->sc_quirk & RTKQ_8139CPLUS) != 0)
1695 CSR_WRITE_1(sc, RTK_TXSTART, RTK_TXSTART_START);
1696 else
1697 CSR_WRITE_1(sc, RTK_GTXSTART, RTK_TXSTART_START);
1698
1699 /*
1700 * Use the countdown timer for interrupt moderation.
1701 * 'TX done' interrupts are disabled. Instead, we reset the
1702 * countdown timer, which will begin counting until it hits
1703 * the value in the TIMERINT register, and then trigger an
1704 * interrupt. Each time we write to the TIMERCNT register,
1705 * the timer count is reset to 0.
1706 */
1707 CSR_WRITE_4(sc, RTK_TIMERCNT, 1);
1708
1709 /*
1710 * Set a timeout in case the chip goes out to lunch.
1711 */
1712 ifp->if_timer = 5;
1713 }
1714 }
1715
1716 static int
1717 re_init(struct ifnet *ifp)
1718 {
1719 struct rtk_softc *sc = ifp->if_softc;
1720 const uint8_t *enaddr;
1721 uint32_t rxcfg = 0;
1722 uint32_t reg;
1723 uint16_t cfg;
1724 int error;
1725
1726 if ((error = re_enable(sc)) != 0)
1727 goto out;
1728
1729 /*
1730 * Cancel pending I/O and free all RX/TX buffers.
1731 */
1732 re_stop(ifp, 0);
1733
1734 re_reset(sc);
1735
1736 /*
1737 * Enable C+ RX and TX mode, as well as VLAN stripping and
1738 * RX checksum offload. We must configure the C+ register
1739 * before all others.
1740 */
1741 cfg = RE_CPLUSCMD_PCI_MRW;
1742
1743 /*
1744 * XXX: For old 8169 set bit 14.
1745 * For 8169S/8110S and above, do not set bit 14.
1746 */
1747 if ((sc->sc_quirk & RTKQ_8169NONS) != 0)
1748 cfg |= (0x1 << 14);
1749
1750 if ((ifp->if_capenable & ETHERCAP_VLAN_HWTAGGING) != 0)
1751 cfg |= RE_CPLUSCMD_VLANSTRIP;
1752 if ((ifp->if_capenable & (IFCAP_CSUM_IPv4_Rx |
1753 IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx)) != 0)
1754 cfg |= RE_CPLUSCMD_RXCSUM_ENB;
1755 if ((sc->sc_quirk & RTKQ_MACSTAT) != 0) {
1756 cfg |= RE_CPLUSCMD_MACSTAT_DIS;
1757 cfg |= RE_CPLUSCMD_TXENB;
1758 } else
1759 cfg |= RE_CPLUSCMD_RXENB | RE_CPLUSCMD_TXENB;
1760
1761 CSR_WRITE_2(sc, RTK_CPLUS_CMD, cfg);
1762
1763 /* XXX: from Realtek-supplied Linux driver. Wholly undocumented. */
1764 if ((sc->sc_quirk & RTKQ_8139CPLUS) == 0)
1765 CSR_WRITE_2(sc, RTK_IM, 0x0000);
1766
1767 DELAY(10000);
1768
1769 /*
1770 * Init our MAC address. Even though the chipset
1771 * documentation doesn't mention it, we need to enter "Config
1772 * register write enable" mode to modify the ID registers.
1773 */
1774 CSR_WRITE_1(sc, RTK_EECMD, RTK_EEMODE_WRITECFG);
1775 enaddr = CLLADDR(ifp->if_sadl);
1776 reg = enaddr[0] | (enaddr[1] << 8) |
1777 (enaddr[2] << 16) | (enaddr[3] << 24);
1778 CSR_WRITE_4(sc, RTK_IDR0, reg);
1779 reg = enaddr[4] | (enaddr[5] << 8);
1780 CSR_WRITE_4(sc, RTK_IDR4, reg);
1781 CSR_WRITE_1(sc, RTK_EECMD, RTK_EEMODE_OFF);
1782
1783 /*
1784 * For C+ mode, initialize the RX descriptors and mbufs.
1785 */
1786 re_rx_list_init(sc);
1787 re_tx_list_init(sc);
1788
1789 /*
1790 * Load the addresses of the RX and TX lists into the chip.
1791 */
1792 CSR_WRITE_4(sc, RTK_RXLIST_ADDR_HI,
1793 RE_ADDR_HI(sc->re_ldata.re_rx_list_map->dm_segs[0].ds_addr));
1794 CSR_WRITE_4(sc, RTK_RXLIST_ADDR_LO,
1795 RE_ADDR_LO(sc->re_ldata.re_rx_list_map->dm_segs[0].ds_addr));
1796
1797 CSR_WRITE_4(sc, RTK_TXLIST_ADDR_HI,
1798 RE_ADDR_HI(sc->re_ldata.re_tx_list_map->dm_segs[0].ds_addr));
1799 CSR_WRITE_4(sc, RTK_TXLIST_ADDR_LO,
1800 RE_ADDR_LO(sc->re_ldata.re_tx_list_map->dm_segs[0].ds_addr));
1801
1802 /*
1803 * Enable transmit and receive.
1804 */
1805 CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_TX_ENB | RTK_CMD_RX_ENB);
1806
1807 /*
1808 * Set the initial TX and RX configuration.
1809 */
1810 if (sc->re_testmode && (sc->sc_quirk & RTKQ_8169NONS) != 0) {
1811 /* test mode is needed only for old 8169 */
1812 CSR_WRITE_4(sc, RTK_TXCFG,
1813 RE_TXCFG_CONFIG | RTK_LOOPTEST_ON);
1814 } else
1815 CSR_WRITE_4(sc, RTK_TXCFG, RE_TXCFG_CONFIG);
1816
1817 CSR_WRITE_1(sc, RTK_EARLY_TX_THRESH, 16);
1818
1819 CSR_WRITE_4(sc, RTK_RXCFG, RE_RXCFG_CONFIG);
1820
1821 /* Set the individual bit to receive frames for this host only. */
1822 rxcfg = CSR_READ_4(sc, RTK_RXCFG);
1823 rxcfg |= RTK_RXCFG_RX_INDIV;
1824
1825 /* If we want promiscuous mode, set the allframes bit. */
1826 if (ifp->if_flags & IFF_PROMISC)
1827 rxcfg |= RTK_RXCFG_RX_ALLPHYS;
1828 else
1829 rxcfg &= ~RTK_RXCFG_RX_ALLPHYS;
1830 CSR_WRITE_4(sc, RTK_RXCFG, rxcfg);
1831
1832 /*
1833 * Set capture broadcast bit to capture broadcast frames.
1834 */
1835 if (ifp->if_flags & IFF_BROADCAST)
1836 rxcfg |= RTK_RXCFG_RX_BROAD;
1837 else
1838 rxcfg &= ~RTK_RXCFG_RX_BROAD;
1839 CSR_WRITE_4(sc, RTK_RXCFG, rxcfg);
1840
1841 /*
1842 * Program the multicast filter, if necessary.
1843 */
1844 rtk_setmulti(sc);
1845
1846 /*
1847 * Enable interrupts.
1848 */
1849 if (sc->re_testmode)
1850 CSR_WRITE_2(sc, RTK_IMR, 0);
1851 else
1852 CSR_WRITE_2(sc, RTK_IMR, RTK_INTRS_CPLUS);
1853
1854 /* Start RX/TX process. */
1855 CSR_WRITE_4(sc, RTK_MISSEDPKT, 0);
1856 #ifdef notdef
1857 /* Enable receiver and transmitter. */
1858 CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_TX_ENB | RTK_CMD_RX_ENB);
1859 #endif
1860
1861 /*
1862 * Initialize the timer interrupt register so that
1863 * a timer interrupt will be generated once the timer
1864 * reaches a certain number of ticks. The timer is
1865 * reloaded on each transmit. This gives us TX interrupt
1866 * moderation, which dramatically improves TX frame rate.
1867 */
1868
1869 if ((sc->sc_quirk & RTKQ_8139CPLUS) != 0)
1870 CSR_WRITE_4(sc, RTK_TIMERINT, 0x400);
1871 else {
1872 CSR_WRITE_4(sc, RTK_TIMERINT_8169, 0x800);
1873
1874 /*
1875 * For 8169 gigE NICs, set the max allowed RX packet
1876 * size so we can receive jumbo frames.
1877 */
1878 CSR_WRITE_2(sc, RTK_MAXRXPKTLEN, 16383);
1879 }
1880
1881 if (sc->re_testmode)
1882 return 0;
1883
1884 CSR_WRITE_1(sc, RTK_CFG1, RTK_CFG1_DRVLOAD);
1885
1886 ifp->if_flags |= IFF_RUNNING;
1887 ifp->if_flags &= ~IFF_OACTIVE;
1888
1889 callout_reset(&sc->rtk_tick_ch, hz, re_tick, sc);
1890
1891 out:
1892 if (error) {
1893 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1894 ifp->if_timer = 0;
1895 printf("%s: interface not running\n",
1896 device_xname(sc->sc_dev));
1897 }
1898
1899 return error;
1900 }
1901
1902 static int
1903 re_ioctl(struct ifnet *ifp, u_long command, void *data)
1904 {
1905 struct rtk_softc *sc = ifp->if_softc;
1906 struct ifreq *ifr = data;
1907 int s, error = 0;
1908
1909 s = splnet();
1910
1911 switch (command) {
1912 case SIOCSIFMTU:
1913 /*
1914 * Disable jumbo frames if it's not supported.
1915 */
1916 if ((sc->sc_quirk & RTKQ_NOJUMBO) != 0 &&
1917 ifr->ifr_mtu > ETHERMTU) {
1918 error = EINVAL;
1919 break;
1920 }
1921
1922 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > ETHERMTU_JUMBO)
1923 error = EINVAL;
1924 else if ((error = ifioctl_common(ifp, command, data)) ==
1925 ENETRESET)
1926 error = 0;
1927 break;
1928 default:
1929 if ((error = ether_ioctl(ifp, command, data)) != ENETRESET)
1930 break;
1931
1932 error = 0;
1933
1934 if (command == SIOCSIFCAP)
1935 error = (*ifp->if_init)(ifp);
1936 else if (command != SIOCADDMULTI && command != SIOCDELMULTI)
1937 ;
1938 else if (ifp->if_flags & IFF_RUNNING)
1939 rtk_setmulti(sc);
1940 break;
1941 }
1942
1943 splx(s);
1944
1945 return error;
1946 }
1947
1948 static void
1949 re_watchdog(struct ifnet *ifp)
1950 {
1951 struct rtk_softc *sc;
1952 int s;
1953
1954 sc = ifp->if_softc;
1955 s = splnet();
1956 printf("%s: watchdog timeout\n", device_xname(sc->sc_dev));
1957 ifp->if_oerrors++;
1958
1959 re_txeof(sc);
1960 re_rxeof(sc);
1961
1962 re_init(ifp);
1963
1964 splx(s);
1965 }
1966
1967 /*
1968 * Stop the adapter and free any mbufs allocated to the
1969 * RX and TX lists.
1970 */
1971 static void
1972 re_stop(struct ifnet *ifp, int disable)
1973 {
1974 int i;
1975 struct rtk_softc *sc = ifp->if_softc;
1976
1977 callout_stop(&sc->rtk_tick_ch);
1978
1979 mii_down(&sc->mii);
1980
1981 if ((sc->sc_quirk & RTKQ_CMDSTOP) != 0)
1982 CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_STOPREQ | RTK_CMD_TX_ENB |
1983 RTK_CMD_RX_ENB);
1984 else
1985 CSR_WRITE_1(sc, RTK_COMMAND, 0x00);
1986 DELAY(1000);
1987 CSR_WRITE_2(sc, RTK_IMR, 0x0000);
1988 CSR_WRITE_2(sc, RTK_ISR, 0xFFFF);
1989
1990 if (sc->re_head != NULL) {
1991 m_freem(sc->re_head);
1992 sc->re_head = sc->re_tail = NULL;
1993 }
1994
1995 /* Free the TX list buffers. */
1996 for (i = 0; i < RE_TX_QLEN; i++) {
1997 if (sc->re_ldata.re_txq[i].txq_mbuf != NULL) {
1998 bus_dmamap_unload(sc->sc_dmat,
1999 sc->re_ldata.re_txq[i].txq_dmamap);
2000 m_freem(sc->re_ldata.re_txq[i].txq_mbuf);
2001 sc->re_ldata.re_txq[i].txq_mbuf = NULL;
2002 }
2003 }
2004
2005 /* Free the RX list buffers. */
2006 for (i = 0; i < RE_RX_DESC_CNT; i++) {
2007 if (sc->re_ldata.re_rxsoft[i].rxs_mbuf != NULL) {
2008 bus_dmamap_unload(sc->sc_dmat,
2009 sc->re_ldata.re_rxsoft[i].rxs_dmamap);
2010 m_freem(sc->re_ldata.re_rxsoft[i].rxs_mbuf);
2011 sc->re_ldata.re_rxsoft[i].rxs_mbuf = NULL;
2012 }
2013 }
2014
2015 if (disable)
2016 re_disable(sc);
2017
2018 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
2019 ifp->if_timer = 0;
2020 }
NetBSD on the FriendlyARM MINI2440