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[netbsd-mini2440.git] / sys / dev / ic / rtwreg.h
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1 /* $NetBSD: rtwreg.h,v 1.26 2008/09/08 23:36:54 gmcgarry Exp $ */
2 /*-
3 * Copyright (c) 2004, 2005 David Young. All rights reserved.
4 *
5 * Programmed for NetBSD by David Young.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY David Young ``AS IS'' AND ANY
17 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
18 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
19 * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL David
20 * Young BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
22 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
24 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
25 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
27 * OF SUCH DAMAGE.
28 */
29
30 #include <lib/libkern/libkern.h>
31
32 /* RTL8180L Host Control and Status Registers */
33
34 #define RTW_IDR0 0x00 /* ID Register: MAC addr, 6 bytes.
35 * Auto-loaded from EEPROM. Read by byte,
36 * by word, or by double word, but write
37 * only by double word.
38 */
39 #define RTW_IDR1 0x04
40
41 #define RTW_MAR0 0x08 /* Multicast filter, 64b. */
42 #define RTW_MAR1 0x0c
43
44 #define RTW_TSFTRL 0x18 /* Timing Synchronization Function Timer
45 * Register, low word, 32b, read-only.
46 */
47 #define RTW_TSFTRH 0x1c /* High word, 32b, read-only. */
48 #define RTW_TLPDA 0x20 /* Transmit Low Priority Descriptors Start
49 * Address, 32b, 256-byte alignment.
50 */
51 #define RTW_TNPDA 0x24 /* Transmit Normal Priority Descriptors Start
52 * Address, 32b, 256-byte alignment.
53 */
54 #define RTW_THPDA 0x28 /* Transmit High Priority Descriptors Start
55 * Address, 32b, 256-byte alignment.
56 */
57
58 #define RTW_BRSR 0x2c /* Basic Rate Set Register, 16b */
59 #define RTW_BRSR_BPLCP __BIT(8)/* 1: use short PLCP header for CTS/ACK packet,
60 * 0: use long PLCP header
61 */
62 #define RTW_BRSR_MBR8180_MASK __BITS(1,0) /* Maximum Basic Service Rate */
63 #define RTW_BRSR_MBR8180_1MBPS __SHIFTIN(0, RTW_BRSR_MBR8180_MASK)
64 #define RTW_BRSR_MBR8180_2MBPS __SHIFTIN(1, RTW_BRSR_MBR8180_MASK)
65 #define RTW_BRSR_MBR8180_5MBPS __SHIFTIN(2, RTW_BRSR_MBR8180_MASK)
66 #define RTW_BRSR_MBR8180_11MBPS __SHIFTIN(3, RTW_BRSR_MBR8180_MASK)
67
68 /* 8181 and 8180 docs conflict! */
69 #define RTW_BRSR_MBR8181_1MBPS __BIT(0)
70 #define RTW_BRSR_MBR8181_2MBPS __BIT(1)
71 #define RTW_BRSR_MBR8181_5MBPS __BIT(2)
72 #define RTW_BRSR_MBR8181_11MBPS __BIT(3)
73
74 #define RTW_BSSID 0x2e
75 /* BSSID, 6 bytes */
76 #define RTW_BSSID16 0x2e /* first two bytes */
77 #define RTW_BSSID32 (0x2e + 4) /* remaining four bytes */
78 #define RTW_BSSID0 RTW_BSSID16 /* BSSID[0], 8b */
79 #define RTW_BSSID1 (RTW_BSSID0 + 1) /* BSSID[1], 8b */
80 #define RTW_BSSID2 (RTW_BSSID1 + 1) /* BSSID[2], 8b */
81 #define RTW_BSSID3 (RTW_BSSID2 + 1) /* BSSID[3], 8b */
82 #define RTW_BSSID4 (RTW_BSSID3 + 1) /* BSSID[4], 8b */
83 #define RTW_BSSID5 (RTW_BSSID4 + 1) /* BSSID[5], 8b */
84
85 #define RTW_CR 0x37 /* Command Register, 8b */
86 #define RTW_CR_RST __BIT(4)/* Reset: host sets to 1 to disable
87 * transmitter & receiver, reinitialize FIFO.
88 * RTL8180L sets to 0 to signal completion.
89 */
90 #define RTW_CR_RE __BIT(3)/* Receiver Enable: host enables receiver
91 * by writing 1. RTL8180L indicates receiver
92 * is active with 1. After power-up, host
93 * must wait for reset before writing.
94 */
95 #define RTW_CR_TE __BIT(2)/* Transmitter Enable: host enables transmitter
96 * by writing 1. RTL8180L indicates transmitter
97 * is active with 1. After power-up, host
98 * must wait for reset before writing.
99 */
100 #define RTW_CR_MULRW __BIT(0)/* PCI Multiple Read/Write enable: 1 enables,
101 * 0 disables. XXX RTL8180, only?
102 */
103
104 #define RTW_IMR 0x3c /* Interrupt Mask Register, 16b */
105 #define RTW_ISR 0x3e /* Interrupt status register, 16b */
106
107 #define RTW_INTR_TXFOVW __BIT(15) /* Tx FIFO underflow */
108 #define RTW_INTR_TIMEOUT __BIT(14) /* Time Out: 1 indicates
109 * RTW_TSFTR[0:31] = RTW_TINT
110 */
111 /* Beacon Time Out: time for host to prepare beacon:
112 * RTW_TSFTR % (RTW_BCNITV_BCNITV * TU) =
113 * (RTW_BCNITV_BCNITV * TU - RTW_BINTRITV)
114 */
115 #define RTW_INTR_BCNINT __BIT(13)
116 /* ATIM Time Out: ATIM interval will pass,
117 * RTW_TSFTR % (RTW_BCNITV_BCNITV * TU) =
118 * (RTW_ATIMWND_ATIMWND * TU - RTW_ATIMTRITV)
119 */
120 #define RTW_INTR_ATIMINT __BIT(12)
121 /* Tx Beacon Descriptor Error: beacon transmission aborted because frame Rx'd */
122 #define RTW_INTR_TBDER __BIT(11)
123 #define RTW_INTR_TBDOK __BIT(10) /* Tx Beacon Descriptor OK */
124 #define RTW_INTR_THPDER __BIT(9)/* Tx High Priority Descriptor Error:
125 * reached short/long retry limit
126 */
127 #define RTW_INTR_THPDOK __BIT(8)/* Tx High Priority Descriptor OK */
128 #define RTW_INTR_TNPDER __BIT(7)/* Tx Normal Priority Descriptor Error:
129 * reached short/long retry limit
130 */
131 #define RTW_INTR_TNPDOK __BIT(6)/* Tx Normal Priority Descriptor OK */
132 #define RTW_INTR_RXFOVW __BIT(5)/* Rx FIFO Overflow: either RDU (see below)
133 * or PCI bus too slow/busy
134 */
135 #define RTW_INTR_RDU __BIT(4)/* Rx Descriptor Unavailable */
136 #define RTW_INTR_TLPDER __BIT(3)/* Tx Normal Priority Descriptor Error
137 * reached short/long retry limit
138 */
139 #define RTW_INTR_TLPDOK __BIT(2)/* Tx Normal Priority Descriptor OK */
140 #define RTW_INTR_RER __BIT(1)/* Rx Error: CRC32 or ICV error */
141 #define RTW_INTR_ROK __BIT(0)/* Rx OK */
142
143 /* Convenient interrupt conjunctions. */
144 #define RTW_INTR_RX (RTW_INTR_RER|RTW_INTR_ROK|RTW_INTR_RDU|RTW_INTR_RXFOVW)
145 #define RTW_INTR_TX (RTW_INTR_TLPDER|RTW_INTR_TLPDOK|RTW_INTR_THPDER|\
146 RTW_INTR_THPDOK|RTW_INTR_TNPDER|RTW_INTR_TNPDOK|\
147 RTW_INTR_TBDER|RTW_INTR_TBDOK)
148 #define RTW_INTR_BEACON (RTW_INTR_BCNINT|RTW_INTR_TBDER|RTW_INTR_TBDOK)
149 #define RTW_INTR_IOERROR (RTW_INTR_TXFOVW)
150
151 #define RTW_TCR 0x40 /* Transmit Configuration Register, 32b */
152 #define RTW_TCR_CWMIN __BIT(31)/* 1: CWmin = 8, 0: CWmin = 32. */
153 #define RTW_TCR_SWSEQ __BIT(30)/* 1: host assigns 802.11 sequence number,
154 * 0: hardware assigns sequence number
155 */
156 /* Hardware version ID, read-only */
157 #define RTW_TCR_HWVERID_MASK __BITS(29, 25)
158 #define RTW_TCR_HWVERID_D __SHIFTIN(26, RTW_TCR_HWVERID_MASK)
159 #define RTW_TCR_HWVERID_F __SHIFTIN(27, RTW_TCR_HWVERID_MASK)
160 #define RTW_TCR_HWVERID_RTL8180 RTW_TCR_HWVERID_F
161
162 /* Set ACK/CTS Timeout (EIFS).
163 * 1: ACK rate = max(RTW_BRSR_MBR, Rx rate) (XXX not min? typo in datasheet?)
164 * 0: ACK rate = 1Mbps
165 */
166 #define RTW_TCR_SAT __BIT(24)
167 /* Max DMA Burst Size per Tx DMA Burst */
168 #define RTW_TCR_MXDMA_MASK __BITS(23,21)
169 #define RTW_TCR_MXDMA_16 __SHIFTIN(0, RTW_TCR_MXDMA_MASK)
170 #define RTW_TCR_MXDMA_32 __SHIFTIN(1, RTW_TCR_MXDMA_MASK)
171 #define RTW_TCR_MXDMA_64 __SHIFTIN(2, RTW_TCR_MXDMA_MASK)
172 #define RTW_TCR_MXDMA_128 __SHIFTIN(3, RTW_TCR_MXDMA_MASK)
173 #define RTW_TCR_MXDMA_256 __SHIFTIN(4, RTW_TCR_MXDMA_MASK)
174 #define RTW_TCR_MXDMA_512 __SHIFTIN(5, RTW_TCR_MXDMA_MASK)
175 #define RTW_TCR_MXDMA_1024 __SHIFTIN(6, RTW_TCR_MXDMA_MASK)
176 #define RTW_TCR_MXDMA_2048 __SHIFTIN(7, RTW_TCR_MXDMA_MASK)
177
178 /* disable 802.11 random backoff */
179 #define RTW_TCR_DISCW __BIT(20)
180
181 /* host lets RTL8180 append ICV to WEP packets */
182 #define RTW_TCR_ICV __BIT(19)
183
184 /* Loopback Test: disables TXI/TXQ outputs. */
185 #define RTW_TCR_LBK_MASK __BITS(18,17)
186 #define RTW_TCR_LBK_NORMAL __SHIFTIN(0, RTW_TCR_LBK_MASK) /* normal ops */
187 #define RTW_TCR_LBK_MAC __SHIFTIN(1, RTW_TCR_LBK_MASK) /* MAC loopback */
188 #define RTW_TCR_LBK_BBP __SHIFTIN(2, RTW_TCR_LBK_MASK) /* baseband loop. */
189 #define RTW_TCR_LBK_CONT __SHIFTIN(3, RTW_TCR_LBK_MASK) /* continuous Tx */
190
191 #define RTW_TCR_CRC __BIT(16) /* 0: RTL8180 appends CRC32
192 * 1: host appends CRC32
193 *
194 * (I *think* this is right.
195 * The docs have a mysterious
196 * description in the
197 * passive voice.)
198 */
199 #define RTW_TCR_SRL_MASK __BITS(15,8) /* Short Retry Limit */
200 #define RTW_TCR_LRL_MASK __BITS(7,0) /* Long Retry Limit */
201
202 #define RTW_RCR 0x44 /* Receive Configuration Register, 32b */
203 /* only do Early Rx on packets longer than 1536 bytes */
204 #define RTW_RCR_ONLYERLPKT __BIT(31)
205 /* enable carrier sense method 2 */
206 #define RTW_RCR_ENCS2 __BIT(30)
207 /* enable carrier sense method 1 */
208 #define RTW_RCR_ENCS1 __BIT(29)
209 #define RTW_RCR_ENMARP __BIT(28) /* enable MAC auto-reset PHY */
210 /* Check BSSID/ToDS/FromDS: set "Link On" when received BSSID
211 * matches RTW_BSSID and received ToDS/FromDS are appropriate
212 * according to RTW_MSR_NETYPE.
213 */
214 #define RTW_RCR_CBSSID __BIT(23)
215 /* accept packets w/ PWRMGMT bit set */
216 #define RTW_RCR_APWRMGT __BIT(22)
217 /* when RTW_MSR_NETYPE == RTW_MSR_NETYPE_INFRA_OK, accept
218 * broadcast/multicast packets whose 3rd address matches RTL8180's MAC.
219 */
220 #define RTW_RCR_ADD3 __BIT(21)
221 #define RTW_RCR_AMF __BIT(20) /* accept management frames */
222 #define RTW_RCR_ACF __BIT(19) /* accept control frames */
223 #define RTW_RCR_ADF __BIT(18) /* accept data frames */
224 /* Rx FIFO Threshold: RTL8180 begins PCI transfer when this many data
225 * bytes are received
226 */
227 #define RTW_RCR_RXFTH_MASK __BITS(15,13)
228 #define RTW_RCR_RXFTH_64 __SHIFTIN(2, RTW_RCR_RXFTH_MASK)
229 #define RTW_RCR_RXFTH_128 __SHIFTIN(3, RTW_RCR_RXFTH_MASK)
230 #define RTW_RCR_RXFTH_256 __SHIFTIN(4, RTW_RCR_RXFTH_MASK)
231 #define RTW_RCR_RXFTH_512 __SHIFTIN(5, RTW_RCR_RXFTH_MASK)
232 #define RTW_RCR_RXFTH_1024 __SHIFTIN(6, RTW_RCR_RXFTH_MASK)
233 #define RTW_RCR_RXFTH_WHOLE __SHIFTIN(7, RTW_RCR_RXFTH_MASK)
234
235 #define RTW_RCR_AICV __BIT(12)/* accept frames w/ ICV errors */
236
237 /* Max DMA Burst Size per Rx DMA Burst */
238 #define RTW_RCR_MXDMA_MASK __BITS(10,8)
239 #define RTW_RCR_MXDMA_16 __SHIFTIN(0, RTW_RCR_MXDMA_MASK)
240 #define RTW_RCR_MXDMA_32 __SHIFTIN(1, RTW_RCR_MXDMA_MASK)
241 #define RTW_RCR_MXDMA_64 __SHIFTIN(2, RTW_RCR_MXDMA_MASK)
242 #define RTW_RCR_MXDMA_128 __SHIFTIN(3, RTW_RCR_MXDMA_MASK)
243 #define RTW_RCR_MXDMA_256 __SHIFTIN(4, RTW_RCR_MXDMA_MASK)
244 #define RTW_RCR_MXDMA_512 __SHIFTIN(5, RTW_RCR_MXDMA_MASK)
245 #define RTW_RCR_MXDMA_1024 __SHIFTIN(6, RTW_RCR_MXDMA_MASK)
246 #define RTW_RCR_MXDMA_UNLIMITED __SHIFTIN(7, RTW_RCR_MXDMA_MASK)
247
248 /* EEPROM type, read-only. 1: EEPROM is 93c56, 0: 93c46 */
249 #define RTW_RCR_9356SEL __BIT(6)
250
251 #define RTW_RCR_ACRC32 __BIT(5)/* accept frames w/ CRC32 errors */
252 #define RTW_RCR_AB __BIT(3)/* accept broadcast frames */
253 #define RTW_RCR_AM __BIT(2)/* accept multicast frames */
254 /* accept physical match frames. XXX means PLCP header ok? */
255 #define RTW_RCR_APM __BIT(1)
256 #define RTW_RCR_AAP __BIT(0)/* accept frames w/ destination */
257
258 /* Additional bits to set in monitor mode. */
259 #define RTW_RCR_MONITOR ( \
260 RTW_RCR_AAP | \
261 RTW_RCR_ACF | \
262 RTW_RCR_ACRC32 | \
263 RTW_RCR_AICV | \
264 0)
265
266 /* The packet filter bits. */
267 #define RTW_RCR_PKTFILTER_MASK (\
268 RTW_RCR_AAP | \
269 RTW_RCR_AB | \
270 RTW_RCR_ACF | \
271 RTW_RCR_ACRC32 | \
272 RTW_RCR_ADD3 | \
273 RTW_RCR_ADF | \
274 RTW_RCR_AICV | \
275 RTW_RCR_AM | \
276 RTW_RCR_AMF | \
277 RTW_RCR_APM | \
278 RTW_RCR_APWRMGT | \
279 0)
280
281 /* Receive power-management frames and mgmt/ctrl/data frames. */
282 #define RTW_RCR_PKTFILTER_DEFAULT ( \
283 RTW_RCR_ACF | \
284 RTW_RCR_ADF | \
285 RTW_RCR_AMF | \
286 RTW_RCR_APM | \
287 RTW_RCR_APWRMGT | \
288 0)
289
290 #define RTW_TINT 0x48 /* Timer Interrupt Register, 32b */
291 #define RTW_TBDA 0x4c /* Transmit Beacon Descriptor Start Address,
292 * 32b, 256-byte alignment
293 */
294 #define RTW_9346CR 0x50 /* 93c46/93c56 Command Register, 8b */
295 #define RTW_9346CR_EEM_MASK __BITS(7,6) /* Operating Mode */
296 #define RTW_9346CR_EEM_NORMAL __SHIFTIN(0, RTW_9346CR_EEM_MASK)
297 /* Load the EEPROM. Reset registers to defaults.
298 * Takes ~2ms. RTL8180 indicates completion with RTW_9346CR_EEM_NORMAL.
299 * XXX RTL8180 only?
300 */
301 #define RTW_9346CR_EEM_AUTOLOAD __SHIFTIN(1, RTW_9346CR_EEM_MASK)
302 /* Disable network & bus-master operations and enable
303 * _EECS, _EESK, _EEDI, _EEDO.
304 * XXX RTL8180 only?
305 */
306 #define RTW_9346CR_EEM_PROGRAM __SHIFTIN(2, RTW_9346CR_EEM_MASK)
307 /* Enable RTW_CONFIG[0123] registers. */
308 #define RTW_9346CR_EEM_CONFIG __SHIFTIN(3, RTW_9346CR_EEM_MASK)
309 /* EEPROM pin status/control in _EEM_CONFIG, _EEM_AUTOLOAD modes.
310 * XXX RTL8180 only?
311 */
312 #define RTW_9346CR_EECS __BIT(3)
313 #define RTW_9346CR_EESK __BIT(2)
314 #define RTW_9346CR_EEDI __BIT(1)
315 #define RTW_9346CR_EEDO __BIT(0) /* read-only */
316
317 #define RTW_CONFIG0 0x51 /* Configuration Register 0, 8b */
318 #define RTW_CONFIG0_WEP40 __BIT(7)/* implements 40-bit WEP,
319 * XXX RTL8180 only?
320 */
321 #define RTW_CONFIG0_WEP104 __BIT(6)/* implements 104-bit WEP,
322 * from EEPROM, read-only
323 * XXX RTL8180 only?
324 */
325 #define RTW_CONFIG0_LEDGPOEN __BIT(4)/* 1: RTW_PSR_LEDGPO[01] control
326 * LED[01] pins.
327 * 0: LED behavior defined by
328 * RTW_CONFIG1_LEDS10_MASK
329 * XXX RTL8180 only?
330 */
331 /* auxiliary power is present, read-only */
332 #define RTW_CONFIG0_AUXPWR __BIT(3)
333 /* Geographic Location, read-only */
334 #define RTW_CONFIG0_GL_MASK __BITS(1,0)
335 /* _RTW_CONFIG0_GL_* is what the datasheet says, but RTW_CONFIG0_GL_*
336 * work.
337 */
338 #define _RTW_CONFIG0_GL_USA __SHIFTIN(3, RTW_CONFIG0_GL_MASK)
339 #define RTW_CONFIG0_GL_EUROPE __SHIFTIN(2, RTW_CONFIG0_GL_MASK)
340 #define RTW_CONFIG0_GL_JAPAN __SHIFTIN(1, RTW_CONFIG0_GL_MASK)
341 #define RTW_CONFIG0_GL_USA __SHIFTIN(0, RTW_CONFIG0_GL_MASK)
342 /* RTL8181 datasheet says RTW_CONFIG0_GL_JAPAN = 0. */
343
344 #define RTW_CONFIG1 0x52 /* Configuration Register 1, 8b */
345
346 /* LED configuration. From EEPROM. Read/write.
347 *
348 * Setting LED0 LED1
349 * ------- ---- ----
350 * RTW_CONFIG1_LEDS_ACT_INFRA Activity Infrastructure
351 * RTW_CONFIG1_LEDS_ACT_LINK Activity Link
352 * RTW_CONFIG1_LEDS_TX_RX Tx Rx
353 * RTW_CONFIG1_LEDS_LINKACT_INFRA Link/Activity Infrastructure
354 */
355 #define RTW_CONFIG1_LEDS_MASK __BITS(7,6)
356 #define RTW_CONFIG1_LEDS_ACT_INFRA __SHIFTIN(0, RTW_CONFIG1_LEDS_MASK)
357 #define RTW_CONFIG1_LEDS_ACT_LINK __SHIFTIN(1, RTW_CONFIG1_LEDS_MASK)
358 #define RTW_CONFIG1_LEDS_TX_RX __SHIFTIN(2, RTW_CONFIG1_LEDS_MASK)
359 #define RTW_CONFIG1_LEDS_LINKACT_INFRA __SHIFTIN(3, RTW_CONFIG1_LEDS_MASK)
360
361 /* LWAKE Output Signal. Only applicable to Cardbus. Pulse width is 150ms.
362 *
363 * RTW_CONFIG1_LWACT
364 * 0 1
365 * RTW_CONFIG4_LWPTN 0 active high active low
366 * 1 positive pulse negative pulse
367 */
368 #define RTW_CONFIG1_LWACT __BIT(4)
369
370 #define RTW_CONFIG1_MEMMAP __BIT(3)/* using PCI memory space, read-only */
371 #define RTW_CONFIG1_IOMAP __BIT(2)/* using PCI I/O space, read-only */
372 #define RTW_CONFIG1_VPD __BIT(1)/* if set, VPD from offsets
373 * 0x40-0x7f in EEPROM are at
374 * registers 0x60-0x67 of PCI
375 * Configuration Space (XXX huh?)
376 */
377 #define RTW_CONFIG1_PMEN __BIT(0)/* Power Management Enable: TBD */
378
379 #define RTW_CONFIG2 0x53 /* Configuration Register 2, 8b */
380 #define RTW_CONFIG2_LCK __BIT(7)/* clocks are locked, read-only:
381 * Tx frequency & symbol clocks
382 * are derived from the same OSC
383 */
384 #define RTW_CONFIG2_ANT __BIT(6) /* diversity enabled, read-only */
385 #define RTW_CONFIG2_DPS __BIT(3) /* Descriptor Polling State: enable
386 * test mode.
387 */
388 #define RTW_CONFIG2_PAPESIGN __BIT(2) /* TBD, from EEPROM */
389 #define RTW_CONFIG2_PAPETIME_MASK __BITS(1,0) /* TBD, from EEPROM */
390
391 #define RTW_ANAPARM 0x54 /* Analog parameter, 32b */
392 #define RTW_ANAPARM_RFPOW0_MASK __BITS(30,28) /* undocumented bits
393 * which appear to
394 * control the power
395 * state of the RF
396 * components
397 */
398 #define RTW_ANAPARM_RFPOW_MASK \
399 (RTW_ANAPARM_RFPOW0_MASK|RTW_ANAPARM_RFPOW1_MASK)
400
401 #define RTW_ANAPARM_TXDACOFF __BIT(27) /* 1: disable Tx DAC,
402 * 0: enable
403 */
404 #define RTW_ANAPARM_RFPOW1_MASK __BITS(26,20) /* undocumented bits
405 * which appear to
406 * control the power
407 * state of the RF
408 * components
409 */
410
411 /*
412 * Maxim On/Sleep/Off control
413 */
414 #define RTW_ANAPARM_RFPOW_MAXIM_ON __SHIFTIN(0x8, RTW_ANAPARM_RFPOW1_MASK)
415
416 /* reg[RTW_ANAPARM] |= RTW_ANAPARM_TXDACOFF; */
417 #define RTW_ANAPARM_RFPOW_MAXIM_SLEEP __SHIFTIN(0x378, RTW_ANAPARM_RFPOW1_MASK)
418
419 /* reg[RTW_ANAPARM] |= RTW_ANAPARM_TXDACOFF; */
420 #define RTW_ANAPARM_RFPOW_MAXIM_OFF __SHIFTIN(0x379, RTW_ANAPARM_RFPOW1_MASK)
421
422 /*
423 * RFMD On/Sleep/Off control
424 */
425 #define RTW_ANAPARM_RFPOW_RFMD_ON __SHIFTIN(0x408, RTW_ANAPARM_RFPOW1_MASK)
426
427 /* reg[RTW_ANAPARM] |= RTW_ANAPARM_TXDACOFF; */
428 #define RTW_ANAPARM_RFPOW_RFMD_SLEEP __SHIFTIN(0x378, RTW_ANAPARM_RFPOW1_MASK)
429
430 /* reg[RTW_ANAPARM] |= RTW_ANAPARM_TXDACOFF; */
431 #define RTW_ANAPARM_RFPOW_RFMD_OFF __SHIFTIN(0x379, RTW_ANAPARM_RFPOW1_MASK)
432
433 /*
434 * Philips On/Sleep/Off control
435 */
436 #define RTW_ANAPARM_RFPOW_ANA_PHILIPS_ON \
437 __SHIFTIN(0x328, RTW_ANAPARM_RFPOW1_MASK)
438 #define RTW_ANAPARM_RFPOW_DIG_PHILIPS_ON \
439 __SHIFTIN(0x008, RTW_ANAPARM_RFPOW1_MASK)
440
441 /* reg[RTW_ANAPARM] |= RTW_ANAPARM_TXDACOFF; */
442 #define RTW_ANAPARM_RFPOW_PHILIPS_SLEEP\
443 __SHIFTIN(0x378, RTW_ANAPARM_RFPOW1_MASK)
444
445 /* reg[RTW_ANAPARM] |= RTW_ANAPARM_TXDACOFF; */
446 #define RTW_ANAPARM_RFPOW_PHILIPS_OFF\
447 __SHIFTIN(0x379, RTW_ANAPARM_RFPOW1_MASK)
448
449 #define RTW_ANAPARM_RFPOW_PHILIPS_ON __SHIFTIN(0x328, RTW_ANAPARM_RFPOW1_MASK)
450
451 #define RTW_ANAPARM_CARDSP_MASK __BITS(19,0) /* undocumented
452 * card-specific
453 * bits from the
454 * EEPROM.
455 */
456
457 #define RTW_MSR 0x58 /* Media Status Register, 8b */
458 /* Network Type and Link Status */
459 #define RTW_MSR_NETYPE_MASK __BITS(3,2)
460 /* AP, XXX RTL8181 only? */
461 #define RTW_MSR_NETYPE_AP_OK __SHIFTIN(3, RTW_MSR_NETYPE_MASK)
462 /* infrastructure link ok */
463 #define RTW_MSR_NETYPE_INFRA_OK __SHIFTIN(2, RTW_MSR_NETYPE_MASK)
464 /* ad-hoc link ok */
465 #define RTW_MSR_NETYPE_ADHOC_OK __SHIFTIN(1, RTW_MSR_NETYPE_MASK)
466 /* no link */
467 #define RTW_MSR_NETYPE_NOLINK __SHIFTIN(0, RTW_MSR_NETYPE_MASK)
468
469 #define RTW_CONFIG3 0x59 /* Configuration Register 3, 8b */
470 #define RTW_CONFIG3_GNTSEL __BIT(7) /* Grant Select, read-only */
471 #define RTW_CONFIG3_PARMEN __BIT(6) /* Set RTW_CONFIG3_PARMEN and
472 * RTW_9346CR_EEM_CONFIG to
473 * allow RTW_ANAPARM writes.
474 */
475 #define RTW_CONFIG3_MAGIC __BIT(5)/* Valid when RTW_CONFIG1_PMEN is
476 * set. If set, RTL8180 wakes up
477 * OS when Magic Packet is Rx'd.
478 */
479 #define RTW_CONFIG3_CARDBEN __BIT(3)/* Cardbus-related registers
480 * and functions are enabled,
481 * read-only. XXX RTL8180 only.
482 */
483 #define RTW_CONFIG3_CLKRUNEN __BIT(2)/* CLKRUN enabled, read-only.
484 * XXX RTL8180 only.
485 */
486 #define RTW_CONFIG3_FUNCREGEN __BIT(1)/* Function Registers Enabled,
487 * read-only. XXX RTL8180 only.
488 */
489 #define RTW_CONFIG3_FBTBEN __BIT(0)/* Fast back-to-back enabled,
490 * read-only.
491 */
492 #define RTW_CONFIG4 0x5A /* Configuration Register 4, 8b */
493 #define RTW_CONFIG4_VCOPDN __BIT(7)/* VCO Power Down
494 * 0: normal operation
495 * (power-on default)
496 * 1: power-down VCO, RF front-end,
497 * and most RTL8180 components.
498 */
499 #define RTW_CONFIG4_PWROFF __BIT(6)/* Power Off
500 * 0: normal operation
501 * (power-on default)
502 * 1: power-down RF front-end,
503 * and most RTL8180 components,
504 * but leave VCO on.
505 *
506 * XXX RFMD front-end only?
507 */
508 #define RTW_CONFIG4_PWRMGT __BIT(5)/* Power Management
509 * 0: normal operation
510 * (power-on default)
511 * 1: set Tx packet's PWRMGMT bit.
512 */
513 #define RTW_CONFIG4_LWPME __BIT(4)/* LANWAKE vs. PMEB: Cardbus-only
514 * 0: LWAKE & PMEB asserted
515 * simultaneously
516 * 1: LWAKE asserted only if
517 * both PMEB is asserted and
518 * ISOLATEB is low.
519 * XXX RTL8180 only.
520 */
521 #define RTW_CONFIG4_LWPTN __BIT(2)/* see RTW_CONFIG1_LWACT
522 * XXX RTL8180 only.
523 */
524 /* Radio Front-End Programming Method */
525 #define RTW_CONFIG4_RFTYPE_MASK __BITS(1,0)
526 #define RTW_CONFIG4_RFTYPE_INTERSIL __SHIFTIN(1, RTW_CONFIG4_RFTYPE_MASK)
527 #define RTW_CONFIG4_RFTYPE_RFMD __SHIFTIN(2, RTW_CONFIG4_RFTYPE_MASK)
528 #define RTW_CONFIG4_RFTYPE_PHILIPS __SHIFTIN(3, RTW_CONFIG4_RFTYPE_MASK)
529
530 #define RTW_TESTR 0x5B /* TEST mode register, 8b */
531
532 #define RTW_PSR 0x5e /* Page Select Register, 8b */
533 #define RTW_PSR_GPO __BIT(7)/* Control/status of pin 52. */
534 #define RTW_PSR_GPI __BIT(6)/* Status of pin 64. */
535 #define RTW_PSR_LEDGPO1 __BIT(5)/* Status/control of LED1 pin if
536 * RTW_CONFIG0_LEDGPOEN is set.
537 */
538 #define RTW_PSR_LEDGPO0 __BIT(4)/* Status/control of LED0 pin if
539 * RTW_CONFIG0_LEDGPOEN is set.
540 */
541 #define RTW_PSR_UWF __BIT(1)/* Enable Unicast Wakeup Frame */
542 #define RTW_PSR_PSEN __BIT(0)/* 1: page 1, 0: page 0 */
543
544 #define RTW_SCR 0x5f /* Security Configuration Register, 8b */
545 #define RTW_SCR_KM_MASK __BITS(5,4) /* Key Mode */
546 #define RTW_SCR_KM_WEP104 __SHIFTIN(1, RTW_SCR_KM_MASK)
547 #define RTW_SCR_KM_WEP40 __SHIFTIN(0, RTW_SCR_KM_MASK)
548 #define RTW_SCR_TXSECON __BIT(1)/* Enable Tx WEP. Invalid if
549 * neither RTW_CONFIG0_WEP40 nor
550 * RTW_CONFIG0_WEP104 is set.
551 */
552 #define RTW_SCR_RXSECON __BIT(0)/* Enable Rx WEP. Invalid if
553 * neither RTW_CONFIG0_WEP40 nor
554 * RTW_CONFIG0_WEP104 is set.
555 */
556
557 #define RTW_BCNITV 0x70 /* Beacon Interval Register, 16b */
558 #define RTW_BCNITV_BCNITV_MASK __BITS(9,0) /* TU between TBTT, written
559 * by host.
560 */
561 #define RTW_ATIMWND 0x72 /* ATIM Window Register, 16b */
562 #define RTW_ATIMWND_ATIMWND __BITS(9,0) /* ATIM Window length in TU,
563 * written by host.
564 */
565
566 #define RTW_BINTRITV 0x74 /* Beacon Interrupt Interval Register, 16b */
567 #define RTW_BINTRITV_BINTRITV __BITS(9,0) /* RTL8180 wakes host with
568 * RTW_INTR_BCNINT at BINTRITV
569 * microseconds before TBTT
570 */
571 #define RTW_ATIMTRITV 0x76 /* ATIM Interrupt Interval Register, 16b */
572 #define RTW_ATIMTRITV_ATIMTRITV __BITS(9,0) /* RTL8180 wakes host with
573 * RTW_INTR_ATIMINT at ATIMTRITV
574 * microseconds before end of
575 * ATIM Window
576 */
577
578 #define RTW_PHYDELAY 0x78 /* PHY Delay Register, 8b */
579 #define RTW_PHYDELAY_REVC_MAGIC __BIT(3) /* Rev. C magic from reference
580 * driver
581 */
582 #define RTW_PHYDELAY_PHYDELAY __BITS(2,0) /* microsecond Tx delay between
583 * MAC and RF front-end
584 */
585 #define RTW_CRCOUNT 0x79 /* Carrier Sense Counter, 8b */
586 #define RTW_CRCOUNT_MAGIC 0x4c
587
588 #define RTW_CRC16ERR 0x7a /* CRC16 error count, 16b, XXX RTL8181 only? */
589
590 #define RTW_BB 0x7c /* Baseband interface, 32b */
591 /* used for writing RTL8180's integrated baseband processor */
592 #define RTW_BB_RD_MASK __BITS(23,16) /* data to read */
593 #define RTW_BB_WR_MASK __BITS(15,8) /* data to write */
594 #define RTW_BB_WREN __BIT(7) /* write enable */
595 #define RTW_BB_ADDR_MASK __BITS(6,0) /* address */
596
597 #define RTW_PHYADDR 0x7c /* Address register for PHY interface, 8b */
598 #define RTW_PHYDATAW 0x7d /* Write data to PHY, 8b, write-only */
599 #define RTW_PHYDATAR 0x7e /* Read data from PHY, 8b (?), read-only */
600
601 #define RTW_PHYCFG 0x80 /* PHY Configuration Register, 32b */
602 #define RTW_PHYCFG_MAC_POLL __BIT(31) /* if !RTW_PHYCFG_HST,
603 * host sets. MAC clears
604 * after banging bits.
605 */
606 #define RTW_PHYCFG_HST __BIT(30) /* 1: host bangs bits
607 * 0: MAC bangs bits
608 */
609 #define RTW_PHYCFG_MAC_RFTYPE_MASK __BITS(29,28)
610 #define RTW_PHYCFG_MAC_RFTYPE_INTERSIL __SHIFTIN(0, RTW_PHYCFG_MAC_RFTYPE_MASK)
611 #define RTW_PHYCFG_MAC_RFTYPE_RFMD __SHIFTIN(1, RTW_PHYCFG_MAC_RFTYPE_MASK)
612 #define RTW_PHYCFG_MAC_RFTYPE_GCT RTW_PHYCFG_MAC_RFTYPE_RFMD
613 #define RTW_PHYCFG_MAC_RFTYPE_PHILIPS __SHIFTIN(3, RTW_PHYCFG_MAC_RFTYPE_MASK)
614 #define RTW_PHYCFG_MAC_PHILIPS_ADDR_MASK __BITS(27,24)
615 #define RTW_PHYCFG_MAC_PHILIPS_DATA_MASK __BITS(23,0)
616 #define RTW_PHYCFG_MAC_MAXIM_LODATA_MASK __BITS(27,24)
617 #define RTW_PHYCFG_MAC_MAXIM_ADDR_MASK __BITS(11,8)
618 #define RTW_PHYCFG_MAC_MAXIM_HIDATA_MASK __BITS(7,0)
619 #define RTW_PHYCFG_HST_EN __BIT(2)
620 #define RTW_PHYCFG_HST_CLK __BIT(1)
621 #define RTW_PHYCFG_HST_DATA __BIT(0)
622
623 #define RTW_MAXIM_HIDATA_MASK __BITS(11,4)
624 #define RTW_MAXIM_LODATA_MASK __BITS(3,0)
625
626 /**
627 ** 0x84 - 0xD3, page 1, selected when RTW_PSR[PSEN] == 1.
628 **/
629
630 #define RTW_WAKEUP0L 0x84 /* Power Management Wakeup Frame */
631 #define RTW_WAKEUP0H 0x88 /* 32b */
632
633 #define RTW_WAKEUP1L 0x8c
634 #define RTW_WAKEUP1H 0x90
635
636 #define RTW_WAKEUP2LL 0x94
637 #define RTW_WAKEUP2LH 0x98
638
639 #define RTW_WAKEUP2HL 0x9c
640 #define RTW_WAKEUP2HH 0xa0
641
642 #define RTW_WAKEUP3LL 0xa4
643 #define RTW_WAKEUP3LH 0xa8
644
645 #define RTW_WAKEUP3HL 0xac
646 #define RTW_WAKEUP3HH 0xb0
647
648 #define RTW_WAKEUP4LL 0xb4
649 #define RTW_WAKEUP4LH 0xb8
650
651 #define RTW_WAKEUP4HL 0xbc
652 #define RTW_WAKEUP4HH 0xc0
653
654 #define RTW_CRC0 0xc4 /* CRC of wakeup frame 0, 16b */
655 #define RTW_CRC1 0xc6 /* CRC of wakeup frame 1, 16b */
656 #define RTW_CRC2 0xc8 /* CRC of wakeup frame 2, 16b */
657 #define RTW_CRC3 0xca /* CRC of wakeup frame 3, 16b */
658 #define RTW_CRC4 0xcc /* CRC of wakeup frame 4, 16b */
659
660 /**
661 ** 0x84 - 0xD3, page 0, selected when RTW_PSR[PSEN] == 0.
662 **/
663
664 /* Default Key Registers, each 128b
665 *
666 * If RTW_SCR_KM_WEP104, 104 lsb are the key.
667 * If RTW_SCR_KM_WEP40, 40 lsb are the key.
668 */
669 #define RTW_DK0 0x90 /* Default Key 0 Register, 128b */
670 #define RTW_DK1 0xa0 /* Default Key 1 Register, 128b */
671 #define RTW_DK2 0xb0 /* Default Key 2 Register, 128b */
672 #define RTW_DK3 0xc0 /* Default Key 3 Register, 128b */
673
674 #define RTW_CONFIG5 0xd8 /* Configuration Register 5, 8b */
675 #define RTW_CONFIG5_TXFIFOOK __BIT(7)/* Tx FIFO self-test pass, read-only */
676 #define RTW_CONFIG5_RXFIFOOK __BIT(6)/* Rx FIFO self-test pass, read-only */
677 #define RTW_CONFIG5_CALON __BIT(5)/* 1: start calibration cycle
678 * and raise AGCRESET pin.
679 * 0: lower AGCRESET pin
680 */
681 #define RTW_CONFIG5_EACPI __BIT(2)/* Enable ACPI Wake up, default 0 */
682 #define RTW_CONFIG5_LANWAKE __BIT(1)/* Enable LAN Wake signal,
683 * from EEPROM
684 */
685 #define RTW_CONFIG5_PMESTS __BIT(0)/* 1: both software & PCI Reset
686 * reset PME_Status
687 * 0: only software resets PME_Status
688 *
689 * From EEPROM.
690 */
691
692 #define RTW_TPPOLL 0xd9 /* Transmit Priority Polling Register, 8b,
693 * write-only.
694 */
695 #define RTW_TPPOLL_BQ __BIT(7)/* RTL8180 clears to notify host of a beacon
696 * Tx. Host writes have no effect.
697 */
698 #define RTW_TPPOLL_HPQ __BIT(6)/* Host writes 1 to notify RTL8180 of
699 * high-priority Tx packets, RTL8180 clears
700 * to after high-priority Tx is complete.
701 */
702 #define RTW_TPPOLL_NPQ __BIT(5)/* If RTW_CONFIG2_DPS is set,
703 * host writes 1 to notify RTL8180 of
704 * normal-priority Tx packets, RTL8180 clears
705 * after normal-priority Tx is complete.
706 *
707 * If RTW_CONFIG2_DPS is clear, host writes
708 * have no effect. RTL8180 clears after
709 * normal-priority Tx is complete.
710 */
711 #define RTW_TPPOLL_LPQ __BIT(4)/* Host writes 1 to notify RTL8180 of
712 * low-priority Tx packets, RTL8180 clears
713 * after low-priority Tx is complete.
714 */
715 #define RTW_TPPOLL_SBQ __BIT(3)/* Host writes 1 to tell RTL8180 to
716 * stop beacon DMA. This bit is invalid
717 * when RTW_CONFIG2_DPS is set.
718 */
719 #define RTW_TPPOLL_SHPQ __BIT(2)/* Host writes 1 to tell RTL8180 to
720 * stop high-priority DMA.
721 */
722 #define RTW_TPPOLL_SNPQ __BIT(1)/* Host writes 1 to tell RTL8180 to
723 * stop normal-priority DMA. This bit is invalid
724 * when RTW_CONFIG2_DPS is set.
725 */
726 #define RTW_TPPOLL_SLPQ __BIT(0)/* Host writes 1 to tell RTL8180 to
727 * stop low-priority DMA.
728 */
729
730 /* Start all queues. */
731 #define RTW_TPPOLL_ALL (RTW_TPPOLL_BQ | RTW_TPPOLL_HPQ | \
732 RTW_TPPOLL_NPQ | RTW_TPPOLL_LPQ)
733 /* Check all queues' activity. */
734 #define RTW_TPPOLL_ACTIVE RTW_TPPOLL_ALL
735 /* Stop all queues. */
736 #define RTW_TPPOLL_SALL (RTW_TPPOLL_SBQ | RTW_TPPOLL_SHPQ | \
737 RTW_TPPOLL_SNPQ | RTW_TPPOLL_SLPQ)
738
739 #define RTW_CWR 0xdc /* Contention Window Register, 16b, read-only */
740 /* Contention Window: indicates number of contention windows before Tx
741 */
742 #define RTW_CWR_CW __BITS(9,0)
743
744 /* Retry Count Register, 16b, read-only */
745 #define RTW_RETRYCTR 0xde
746 /* Retry Count: indicates number of retries after Tx */
747 #define RTW_RETRYCTR_RETRYCT __BITS(7,0)
748
749 #define RTW_RDSAR 0xe4 /* Receive descriptor Start Address Register,
750 * 32b, 256-byte alignment.
751 */
752 /* Function Event Register, 32b, Cardbus only. Only valid when
753 * both RTW_CONFIG3_CARDBEN and RTW_CONFIG3_FUNCREGEN are set.
754 */
755 #define RTW_FER 0xf0
756 #define RTW_FER_INTR __BIT(15) /* set when RTW_FFER_INTR is set */
757 #define RTW_FER_GWAKE __BIT(4) /* General Wakeup */
758 /* Function Event Mask Register, 32b, Cardbus only. Only valid when
759 * both RTW_CONFIG3_CARDBEN and RTW_CONFIG3_FUNCREGEN are set.
760 */
761 #define RTW_FEMR 0xf4
762 #define RTW_FEMR_INTR __BIT(15) /* set when RTW_FFER_INTR is set */
763 #define RTW_FEMR_WKUP __BIT(14) /* Wakeup Mask */
764 #define RTW_FEMR_GWAKE __BIT(4) /* General Wakeup */
765 /* Function Present State Register, 32b, read-only, Cardbus only.
766 * Only valid when both RTW_CONFIG3_CARDBEN and RTW_CONFIG3_FUNCREGEN
767 * are set.
768 */
769 #define RTW_FPSR 0xf8
770 #define RTW_FPSR_INTR __BIT(15) /* TBD */
771 #define RTW_FPSR_GWAKE __BIT(4) /* General Wakeup: TBD */
772 /* Function Force Event Register, 32b, write-only, Cardbus only.
773 * Only valid when both RTW_CONFIG3_CARDBEN and RTW_CONFIG3_FUNCREGEN
774 * are set.
775 */
776 #define RTW_FFER 0xfc
777 #define RTW_FFER_INTR __BIT(15) /* TBD */
778 #define RTW_FFER_GWAKE __BIT(4) /* General Wakeup: TBD */
779
780 /* Serial EEPROM offsets */
781 #define RTW_SR_ID 0x00 /* 16b */
782 #define RTW_SR_VID 0x02 /* 16b */
783 #define RTW_SR_DID 0x04 /* 16b */
784 #define RTW_SR_SVID 0x06 /* 16b */
785 #define RTW_SR_SMID 0x08 /* 16b */
786 #define RTW_SR_MNGNT 0x0a
787 #define RTW_SR_MXLAT 0x0b
788 #define RTW_SR_RFCHIPID 0x0c
789 #define RTW_SR_CONFIG3 0x0d
790 #define RTW_SR_MAC 0x0e /* 6 bytes */
791 #define RTW_SR_CONFIG0 0x14
792 #define RTW_SR_CONFIG1 0x15
793 #define RTW_SR_PMC 0x16 /* Power Management Capabilities, 16b */
794 #define RTW_SR_CONFIG2 0x18
795 #define RTW_SR_CONFIG4 0x19
796 #define RTW_SR_ANAPARM 0x1a /* Analog Parameters, 32b */
797 #define RTW_SR_TESTR 0x1e
798 #define RTW_SR_CONFIG5 0x1f
799 #define RTW_SR_TXPOWER1 0x20
800 #define RTW_SR_TXPOWER2 0x21
801 #define RTW_SR_TXPOWER3 0x22
802 #define RTW_SR_TXPOWER4 0x23
803 #define RTW_SR_TXPOWER5 0x24
804 #define RTW_SR_TXPOWER6 0x25
805 #define RTW_SR_TXPOWER7 0x26
806 #define RTW_SR_TXPOWER8 0x27
807 #define RTW_SR_TXPOWER9 0x28
808 #define RTW_SR_TXPOWER10 0x29
809 #define RTW_SR_TXPOWER11 0x2a
810 #define RTW_SR_TXPOWER12 0x2b
811 #define RTW_SR_TXPOWER13 0x2c
812 #define RTW_SR_TXPOWER14 0x2d
813 #define RTW_SR_CHANNELPLAN 0x2e /* bitmap of channels to scan */
814 #define RTW_SR_ENERGYDETTHR 0x2f /* energy-detect threshold */
815 #define RTW_SR_ENERGYDETTHR_DEFAULT 0x0c /* use this if old SROM */
816 #define RTW_SR_CISPOINTER 0x30 /* 16b */
817 #define RTW_SR_RFPARM 0x32 /* RF-specific parameter */
818 #define RTW_SR_RFPARM_DIGPHY __BIT(0) /* 1: digital PHY */
819 #define RTW_SR_RFPARM_DFLANTB __BIT(1) /* 1: antenna B is default */
820 #define RTW_SR_RFPARM_CS_MASK __BITS(2,3) /* carrier-sense type */
821 #define RTW_SR_VERSION 0x3c /* EEPROM content version, 16b */
822 #define RTW_SR_CRC 0x3e /* EEPROM content CRC, 16b */
823 #define RTW_SR_VPD 0x40 /* Vital Product Data, 64 bytes */
824 #define RTW_SR_CIS 0x80 /* CIS Data, 93c56 only, 128 bytes*/
825
826 /*
827 * RTL8180 Transmit/Receive Descriptors
828 */
829
830 /* the first descriptor in each ring must be on a 256-byte boundary */
831 #define RTW_DESC_ALIGNMENT 256
832
833 /* Tx descriptor */
834 struct rtw_txdesc {
835 volatile uint32_t td_ctl0;
836 volatile uint32_t td_ctl1;
837 volatile uint32_t td_buf;
838 volatile uint32_t td_len;
839 volatile uint32_t td_next;
840 volatile uint32_t td_rsvd[3];
841 } __packed __aligned(4);
842
843 #define td_stat td_ctl0
844
845 #define RTW_TXCTL0_OWN __BIT(31) /* 1: ready to Tx */
846 #define RTW_TXCTL0_RSVD0 __BIT(30) /* reserved */
847 #define RTW_TXCTL0_FS __BIT(29) /* first segment */
848 #define RTW_TXCTL0_LS __BIT(28) /* last segment */
849
850 #define RTW_TXCTL0_RATE_MASK __BITS(27,24) /* Tx rate */
851 #define RTW_TXCTL0_RATE_1MBPS __SHIFTIN(0, RTW_TXCTL0_RATE_MASK)
852 #define RTW_TXCTL0_RATE_2MBPS __SHIFTIN(1, RTW_TXCTL0_RATE_MASK)
853 #define RTW_TXCTL0_RATE_5MBPS __SHIFTIN(2, RTW_TXCTL0_RATE_MASK)
854 #define RTW_TXCTL0_RATE_11MBPS __SHIFTIN(3, RTW_TXCTL0_RATE_MASK)
855
856 #define RTW_TXCTL0_RTSEN __BIT(23) /* RTS Enable */
857
858 #define RTW_TXCTL0_RTSRATE_MASK __BITS(22,19) /* Tx rate */
859 #define RTW_TXCTL0_RTSRATE_1MBPS __SHIFTIN(0, RTW_TXCTL0_RTSRATE_MASK)
860 #define RTW_TXCTL0_RTSRATE_2MBPS __SHIFTIN(1, RTW_TXCTL0_RTSRATE_MASK)
861 #define RTW_TXCTL0_RTSRATE_5MBPS __SHIFTIN(2, RTW_TXCTL0_RTSRATE_MASK)
862 #define RTW_TXCTL0_RTSRATE_11MBPS __SHIFTIN(3, RTW_TXCTL0_RTSRATE_MASK)
863
864 #define RTW_TXCTL0_BEACON __BIT(18) /* packet is a beacon */
865 #define RTW_TXCTL0_MOREFRAG __BIT(17) /* another fragment
866 * follows
867 */
868 /* add short PLCP preamble and header */
869 #define RTW_TXCTL0_SPLCP __BIT(16)
870 #define RTW_TXCTL0_KEYID_MASK __BITS(15,14) /* default key id */
871 #define RTW_TXCTL0_RSVD1_MASK __BITS(13,12) /* reserved */
872 #define RTW_TXCTL0_TPKTSIZE_MASK __BITS(11,0) /* Tx packet size
873 * in bytes
874 */
875
876 #define RTW_TXSTAT_OWN RTW_TXCTL0_OWN
877 #define RTW_TXSTAT_RSVD0 RTW_TXCTL0_RSVD0
878 #define RTW_TXSTAT_FS RTW_TXCTL0_FS
879 #define RTW_TXSTAT_LS RTW_TXCTL0_LS
880 #define RTW_TXSTAT_RSVD1_MASK __BITS(27,16)
881 #define RTW_TXSTAT_TOK __BIT(15)
882 #define RTW_TXSTAT_RTSRETRY_MASK __BITS(14,8) /* RTS retry count */
883 #define RTW_TXSTAT_DRC_MASK __BITS(7,0) /* Data retry count */
884
885 #define RTW_TXCTL1_LENGEXT __BIT(31) /* supplements _LENGTH
886 * in packets sent 5.5Mb/s or
887 * faster
888 */
889 #define RTW_TXCTL1_LENGTH_MASK __BITS(30,16) /* PLCP length (microseconds) */
890 #define RTW_TXCTL1_RTSDUR_MASK __BITS(15,0) /* RTS Duration
891 * (microseconds)
892 */
893
894 #define RTW_TXLEN_LENGTH_MASK __BITS(11,0) /* Tx buffer length in bytes */
895
896 /* Rx descriptor */
897 struct rtw_rxdesc {
898 volatile uint32_t rd_ctl;
899 volatile uint32_t rd_rsvd0;
900 volatile uint32_t rd_buf;
901 volatile uint32_t rd_rsvd1;
902 } __packed __aligned(4);
903
904 #define rd_stat rd_ctl
905 #define rd_rssi rd_rsvd0
906 #define rd_tsftl rd_buf /* valid only when RTW_RXSTAT_LS is set */
907 #define rd_tsfth rd_rsvd1 /* valid only when RTW_RXSTAT_LS is set */
908
909 #define RTW_RXCTL_OWN __BIT(31) /* 1: owned by NIC */
910 #define RTW_RXCTL_EOR __BIT(30) /* end of ring */
911 #define RTW_RXCTL_FS __BIT(29) /* first segment */
912 #define RTW_RXCTL_LS __BIT(28) /* last segment */
913 #define RTW_RXCTL_RSVD0_MASK __BITS(29,12) /* reserved */
914 #define RTW_RXCTL_LENGTH_MASK __BITS(11,0) /* Rx buffer length */
915
916 #define RTW_RXSTAT_OWN RTW_RXCTL_OWN
917 #define RTW_RXSTAT_EOR RTW_RXCTL_EOR
918 #define RTW_RXSTAT_FS RTW_RXCTL_FS /* first segment */
919 #define RTW_RXSTAT_LS RTW_RXCTL_LS /* last segment */
920 #define RTW_RXSTAT_DMAFAIL __BIT(27) /* DMA failure on this pkt */
921 #define RTW_RXSTAT_BOVF __BIT(26) /* buffer overflow XXX means
922 * FIFO exhausted?
923 */
924 #define RTW_RXSTAT_SPLCP __BIT(25) /* Rx'd with short preamble
925 * and PLCP header
926 */
927 #define RTW_RXSTAT_RSVD1 __BIT(24) /* reserved */
928 #define RTW_RXSTAT_RATE_MASK __BITS(23,20) /* Rx rate */
929 #define RTW_RXSTAT_RATE_1MBPS __SHIFTIN(0, RTW_RXSTAT_RATE_MASK)
930 #define RTW_RXSTAT_RATE_2MBPS __SHIFTIN(1, RTW_RXSTAT_RATE_MASK)
931 #define RTW_RXSTAT_RATE_5MBPS __SHIFTIN(2, RTW_RXSTAT_RATE_MASK)
932 #define RTW_RXSTAT_RATE_11MBPS __SHIFTIN(3, RTW_RXSTAT_RATE_MASK)
933 #define RTW_RXSTAT_MIC __BIT(19) /* XXX from reference driver */
934 #define RTW_RXSTAT_MAR __BIT(18) /* is multicast */
935 #define RTW_RXSTAT_PAR __BIT(17) /* matches RTL8180's MAC */
936 #define RTW_RXSTAT_BAR __BIT(16) /* is broadcast */
937 #define RTW_RXSTAT_RES __BIT(15) /* error summary. valid when
938 * RTW_RXSTAT_LS set. indicates
939 * that either RTW_RXSTAT_CRC32
940 * or RTW_RXSTAT_ICV is set.
941 */
942 #define RTW_RXSTAT_PWRMGT __BIT(14) /* 802.11 PWRMGMT bit is set */
943 #define RTW_RXSTAT_CRC16 __BIT(14) /* XXX CRC16 error, from
944 * reference driver
945 */
946 #define RTW_RXSTAT_CRC32 __BIT(13) /* CRC32 error */
947 #define RTW_RXSTAT_ICV __BIT(12) /* ICV error */
948 #define RTW_RXSTAT_LENGTH_MASK __BITS(11,0) /* frame length, including
949 * CRC32
950 */
951
952 /* Convenient status conjunction. */
953 #define RTW_RXSTAT_ONESEG (RTW_RXSTAT_FS|RTW_RXSTAT_LS)
954 /* Convenient status disjunctions. */
955 #define RTW_RXSTAT_IOERROR (RTW_RXSTAT_DMAFAIL|RTW_RXSTAT_BOVF)
956 #define RTW_RXSTAT_DEBUG (RTW_RXSTAT_SPLCP|RTW_RXSTAT_MAR|\
957 RTW_RXSTAT_PAR|RTW_RXSTAT_BAR|\
958 RTW_RXSTAT_PWRMGT|RTW_RXSTAT_CRC32|\
959 RTW_RXSTAT_ICV)
960
961
962 #define RTW_RXRSSI_VLAN __BITS(31,16) /* XXX from reference driver */
963 /* for Philips RF front-ends */
964 #define RTW_RXRSSI_RSSI __BITS(15,8) /* RF energy at the PHY */
965 /* for RF front-ends by Intersil, Maxim, RFMD */
966 #define RTW_RXRSSI_IMR_RSSI __BITS(15,9) /* RF energy at the PHY */
967 #define RTW_RXRSSI_IMR_LNA __BIT(8) /* 1: LNA activated */
968 #define RTW_RXRSSI_SQ __BITS(7,0) /* Barker code-lock quality */
969
970 #define RTW_READ8(regs, ofs) \
971 bus_space_read_1((regs)->r_bt, (regs)->r_bh, (ofs))
972
973 #define RTW_READ16(regs, ofs) \
974 bus_space_read_2((regs)->r_bt, (regs)->r_bh, (ofs))
975
976 #define RTW_READ(regs, ofs) \
977 bus_space_read_4((regs)->r_bt, (regs)->r_bh, (ofs))
978
979 #define RTW_WRITE8(regs, ofs, val) \
980 bus_space_write_1((regs)->r_bt, (regs)->r_bh, (ofs), (val))
981
982 #define RTW_WRITE16(regs, ofs, val) \
983 bus_space_write_2((regs)->r_bt, (regs)->r_bh, (ofs), (val))
984
985 #define RTW_WRITE(regs, ofs, val) \
986 bus_space_write_4((regs)->r_bt, (regs)->r_bh, (ofs), (val))
987
988 #define RTW_ISSET(regs, reg, mask) \
989 (RTW_READ((regs), (reg)) & (mask))
990
991 #define RTW_CLR(regs, reg, mask) \
992 RTW_WRITE((regs), (reg), RTW_READ((regs), (reg)) & ~(mask))
993
994 /* bus_space(9) lied? */
995 #ifndef BUS_SPACE_BARRIER_SYNC
996 #define BUS_SPACE_BARRIER_SYNC (BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE)
997 #endif
998
999 #ifndef BUS_SPACE_BARRIER_READ_BEFORE_READ
1000 #define BUS_SPACE_BARRIER_READ_BEFORE_READ BUS_SPACE_BARRIER_READ
1001 #endif
1002
1003 #ifndef BUS_SPACE_BARRIER_READ_BEFORE_WRITE
1004 #define BUS_SPACE_BARRIER_READ_BEFORE_WRITE BUS_SPACE_BARRIER_READ
1005 #endif
1006
1007 #ifndef BUS_SPACE_BARRIER_WRITE_BEFORE_READ
1008 #define BUS_SPACE_BARRIER_WRITE_BEFORE_READ BUS_SPACE_BARRIER_WRITE
1009 #endif
1010
1011 #ifndef BUS_SPACE_BARRIER_WRITE_BEFORE_WRITE
1012 #define BUS_SPACE_BARRIER_WRITE_BEFORE_WRITE BUS_SPACE_BARRIER_WRITE
1013 #endif
1014
1015 /*
1016 * Bus barrier
1017 *
1018 * Complete outstanding read and/or write ops on [reg0, reg1]
1019 * ([reg1, reg0]) before starting new ops on the same region. See
1020 * acceptable bus_space_barrier(9) for the flag definitions.
1021 */
1022 #define RTW_BARRIER(regs, reg0, reg1, flags) \
1023 bus_space_barrier((regs)->r_bh, (regs)->r_bt, \
1024 MIN(reg0, reg1), MAX(reg0, reg1) - MIN(reg0, reg1) + 4, flags)
1025
1026 /*
1027 * Barrier convenience macros.
1028 */
1029 /* sync */
1030 #define RTW_SYNC(regs, reg0, reg1) \
1031 RTW_BARRIER(regs, reg0, reg1, BUS_SPACE_BARRIER_SYNC)
1032
1033 /* write-before-write */
1034 #define RTW_WBW(regs, reg0, reg1) \
1035 RTW_BARRIER(regs, reg0, reg1, BUS_SPACE_BARRIER_WRITE_BEFORE_WRITE)
1036
1037 /* write-before-read */
1038 #define RTW_WBR(regs, reg0, reg1) \
1039 RTW_BARRIER(regs, reg0, reg1, BUS_SPACE_BARRIER_WRITE_BEFORE_READ)
1040
1041 /* read-before-read */
1042 #define RTW_RBR(regs, reg0, reg1) \
1043 RTW_BARRIER(regs, reg0, reg1, BUS_SPACE_BARRIER_READ_BEFORE_READ)
1044
1045 /* read-before-write */
1046 #define RTW_RBW(regs, reg0, reg1) \
1047 RTW_BARRIER(regs, reg0, reg1, BUS_SPACE_BARRIER_READ_BEFORE_WRITE)
1048
1049 #define RTW_WBRW(regs, reg0, reg1) \
1050 RTW_BARRIER(regs, reg0, reg1, \
1051 BUS_SPACE_BARRIER_WRITE_BEFORE_READ | \
1052 BUS_SPACE_BARRIER_WRITE_BEFORE_WRITE)
1053
1054 /*
1055 * Registers for RTL8180L's built-in baseband modem.
1056 */
1057 #define RTW_BBP_SYS1 0x00
1058 #define RTW_BBP_TXAGC 0x03 /* guess: transmit auto gain control */
1059 #define RTW_BBP_LNADET 0x04 /* guess: low-noise amplifier activation
1060 * threshold
1061 */
1062 #define RTW_BBP_IFAGCINI 0x05 /* guess: intermediate frequency (IF)
1063 * auto-gain control (AGC) initial value
1064 */
1065 #define RTW_BBP_IFAGCLIMIT 0x06 /* guess: IF AGC maximum value */
1066 #define RTW_BBP_IFAGCDET 0x07 /* guess: activation threshold for
1067 * IF AGC loop
1068 */
1069
1070 #define RTW_BBP_ANTATTEN 0x10 /* guess: antenna & attenuation */
1071 #define RTW_BBP_ANTATTEN_GCT_MAGIC 0xa3
1072 #define RTW_BBP_ANTATTEN_PHILIPS_MAGIC 0x91
1073 #define RTW_BBP_ANTATTEN_INTERSIL_MAGIC 0x92
1074 #define RTW_BBP_ANTATTEN_RFMD_MAGIC 0x93
1075 #define RTW_BBP_ANTATTEN_MAXIM_MAGIC 0xb3
1076 #define RTW_BBP_ANTATTEN_DFLANTB 0x40
1077 #define RTW_BBP_ANTATTEN_CHAN14 0x0c
1078
1079 #define RTW_BBP_TRL 0x11 /* guess: transmit/receive
1080 * switch latency
1081 */
1082 #define RTW_BBP_SYS2 0x12
1083 #define RTW_BBP_SYS2_ANTDIV 0x80 /* enable antenna diversity */
1084 #define RTW_BBP_SYS2_RATE_MASK __BITS(5,4) /* loopback rate?
1085 * 0: 1Mbps
1086 * 1: 2Mbps
1087 * 2: 5.5Mbps
1088 * 3: 11Mbps
1089 */
1090 #define RTW_BBP_SYS3 0x13
1091 /* carrier-sense threshold */
1092 #define RTW_BBP_SYS3_CSTHRESH_MASK __BITS(0,3)
1093 #define RTW_BBP_CHESTLIM 0x19 /* guess: channel energy-detect
1094 * threshold
1095 */
1096 #define RTW_BBP_CHSQLIM 0x1a /* guess: channel signal-quality
1097 * threshold
1098 */
NetBSD on the FriendlyARM MINI2440