1 /* $NetBSD: seeq8003reg.h,v 1.2 2001/06/06 22:11:42 soren Exp $ */
4 * Copyright (c) 2000 Soren S. Jorvang. All rights reserved.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions, and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * Register definitions for the Seeq 8003 and 80C03 ethernet controllers
31 * Based on documentation available at
32 * http://www.lsilogic.com/techlib/techdocs/networking/eol/80c03.pdf .
35 #define SEEQ_ADDR0 0 /* Station Address Byte 0 */
36 #define SEEQ_ADDR1 1 /* Station Address Byte 1 */
37 #define SEEQ_ADDR2 2 /* Station Address Byte 2 */
38 #define SEEQ_ADDR3 3 /* Station Address Byte 3 */
39 #define SEEQ_ADDR4 4 /* Station Address Byte 4 */
40 #define SEEQ_ADDR5 5 /* Station Address Byte 5 */
42 #define SEEQ_TXCOLLS0 0 /* Transmit Collision Counter LSB */
43 #define SEEQ_TXCOLLS1 1 /* Transmit Collision Counter MSB */
44 #define SEEQ_ALLCOLL0 2 /* Total Collision Counter LSB */
45 #define SEEQ_ALLCOLL1 3 /* Total Collision Counter MSB */
47 #define SEEQ_TEST 4 /* "For Test Only" - Do Not Use */
49 #define SEEQ_SQE 5 /* SQE / No Carrier */
50 #define SQE_FLAG 0x01 /* SQE Flag */
51 #define SQE_NOCARR 0x02 /* No Carrier Flag */
53 #define SEEQ_RXCMD 6 /* Rx Command */
54 #define RXCMD_IE_OFLOW 0x01 /* Interrupt on Overflow Error */
55 #define RXCMD_IE_CRC 0x02 /* Interrupt on CRC Error */
56 #define RXCMD_IE_DRIB 0x04 /* Interrupt on Dribble Error */
57 #define RXCMD_IE_SHORT 0x08 /* Interrupt on Short Frame */
58 #define RXCMD_IE_END 0x10 /* Interrupt on End of Frame */
59 #define RXCMD_IE_GOOD 0x20 /* Interrupt on Good Frame */
60 #define RXCMD_REC_MASK 0xc0 /* Receiver Match Mode Mask */
61 #define RXCMD_REC_NONE 0x00 /* Receiver Disabled */
62 #define RXCMD_REC_ALL 0x40 /* Receive All Frames */
63 #define RXCMD_REC_BROAD 0x80 /* Receive Station/Broadcast Frames */
64 #define RXCMD_REC_MULTI 0xc0 /* Station/Broadcast/Multicast */
66 #define SEEQ_RXSTAT 6 /* Rx Status */
67 #define RXSTAT_OFLOW 0x01 /* Frame Overflow Error */
68 #define RXSTAT_CRC 0x02 /* Frame CRC Error */
69 #define RXSTAT_DRIB 0x04 /* Frame Dribble Error */
70 #define RXSTAT_SHORT 0x08 /* Received Short Frame */
71 #define RXSTAT_END 0x10 /* Received End of Frame */
72 #define RXSTAT_GOOD 0x20 /* Received Good Frame */
73 #define RXSTAT_OLDNEW 0x80 /* Old/New Status */
75 #define SEEQ_TXCMD 7 /* Tx Command */
76 #define TXCMD_IE_UFLOW 0x01 /* Interrupt on Transmit Underflow */
77 #define TXCMD_IE_COLL 0x02 /* Interrupt on Transmit Collision */
78 #define TXCMD_IE_16COLL 0x04 /* Interrupt on 16 Collisions */
79 #define TXCMD_IE_GOOD 0x08 /* Interrupt on Transmit Succes */
80 #define TXCMD_ENABLE_C 0xf0 /* (80C03) Enable 80C03 Mode */
81 #define TXCMD_BANK_MASK 0x60 /* (80C03) Register Bank Mask */
82 #define TXCMD_BANK0 0x00 /* (80C03) Register Bank 0 (8003) */
83 #define TXCMD_BANK1 0x20 /* (80C03) Register Bank 1 (Writes) */
84 #define TXCMD_BANK2 0x40 /* (80C03) Register Bank 2 (Writes) */
86 #define SEEQ_TXSTAT 7 /* Tx Status */
87 #define TXSTAT_UFLOW 0x01 /* Transmit Underflow */
88 #define TXSTAT_COLL 0x02 /* Transmit Collision */
89 #define TXSTAT_16COLL 0x04 /* 16 Collisions */
90 #define TXSTAT_GOOD 0x08 /* Transmit Success */
91 #define TXSTAT_OLDNEW 0x80 /* Old/New Status */
94 * 80C03 Mode Register Bank 1
97 #define SEEQ_MC_HASH0 0 /* Multicast Filter Byte 0 (LSB) */
98 #define SEEQ_MC_HASH1 1 /* Multicast Filter Byte 1 */
99 #define SEEQ_MC_HASH2 2 /* Multicast Filter Byte 2 */
100 #define SEEQ_MC_HASH3 3 /* Multicast Filter Byte 3 */
101 #define SEEQ_MC_HASH4 4 /* Multicast Filter Byte 4 */
102 #define SEEQ_MC_HASH5 5 /* Multicast Filter Byte 5 */
105 * 80C03 Mode Register Bank 2
108 #define SEEQ_MC_HASH6 0 /* Multicast Filter Byte 6 */
109 #define SEEQ_MC_HASH7 1 /* Multicast Filter Byte 7 (MSB) */
111 #define SEEQ_RESERVED0 2 /* Reserved (Set to All Zeroes) */
113 #define SEEQ_TXCTRL 3 /* Tx Control */
114 #define TXCTRL_TXCOLL 0x01 /* Clear/Enable Tx Collision Counter */
115 #define TXCTRL_COLL 0x02 /* Clear/Enable Collision Counter */
116 #define TXCTRL_SQE 0x04 /* Clear/Enable SQE Flag */
117 #define TXCTRL_HASH 0x08 /* Enable Multicast Hash Filter */
118 #define TXCTRL_SHORT 0x10 /* Receive Short (<13 Bytes) Frames */
119 #define TXCTRL_NOCARR 0x20 /* Clear/Enable No Carrier Flag */
121 #define SEEQ_CFG 4 /* Transmit/Receive Configuration */
122 #define CFG_RX_GRPADDR 0x01 /* Ignore Last 4 Bits of Address */
123 #define CFG_TX_AUTOPAD 0x02 /* Automatically Pad to 60 Bytes */
124 #define CFG_TX_NOPRE 0x04 /* Do Not Add Preamble Pattern */
125 #define CFG_RX_NOOWN 0x08 /* Do Not Receive Own Packets */
126 #define CFG_TX_NOCRC 0x10 /* No Not Append CRC */
127 #define CFG_TX_DUPLEX 0x20 /* AutoDUPLEX - Ignore Carrier */
128 #define CFG_RX_CRCFIFO 0x40 /* Write CRC to FIFO */
129 #define CFG_RX_FASTDISC 0x80 /* Fast Receive Discard Mode */
131 #define SEEQ_RESERVED1 5 /* Reserved */
132 #define SEEQ_RESERVED2 6 /* Reserved */
133 #define SEEQ_RESERVED3 7 /* Reserved */
