?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
No empty .Rs/.Re
[netbsd-mini2440.git] / sys / dev / ic / tcic2reg.h
blob4bb7648ce4957cc290d9fb38aa2977a833f93f7d
1 /* $NetBSD: tcic2reg.h,v 1.4 2005/12/11 12:21:28 christos Exp $ */
2
3 /*-
4 * Copyright (c) 1998, 1999 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Christoph Badura.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32 /*
33 * All information is from the Databook DB86082 TCIC PC Card Controller for
34 * Notebook PCs -- Hardware Design Guide, March 22, 1994.
35 */
36
37 #ifndef _TCIC2REG_H
38 #define _TCIC2REG_H
39 #define TCIC_IOSIZE 16
40
41 /* TCIC primary registers */
42 #define TCIC_R_DATA 0 /* Data register, 16 bit */
43 #define TCIC_R_ADDR 2 /* Address register, 32 bit */
44 #define TCIC_R_ADDR2 (TCIC_R_ADDR+2) /* high word of addr. reg. */
45 #define TCIC_R_SCTRL 6 /* Socket control reg., 8 bit */
46 #define TCIC_R_SSTAT 7 /* Socket status reg., 8 bit */
47 #define TCIC_R_MODE 8 /* Mode register, 8 bit */
48 #define TCIC_R_PWR 9 /* Power control reg., 8 bit */
49 #define TCIC_R_EDC 0xA /* Error detect code, 16 bit */
50 #define TCIC_R_ICSR 0xC /* Interrupt ctrl/status, 8 bit */
51 #define TCIC_R_IENA 0xD /* Interrupt enable, 8 bit */
52 #define TCIC_R_AUX 0xE /* Auxiliary Register, 16 bit */
53
54 /*
55 * TCIC auxiliary registers.
56 * These are all 16 bit registers.
57 * They are accessed by selecting the appropriate index in
58 * bits 7:5 of the mode register.
59 */
60 #define TCIC_AR_MASK 0xe0 /* for masking the mode reg. */
61 #define TCIC_AR_TCTL 0x00 /* timing control register */
62 #define TCIC_AR_PCTL 0x20 /* programming pulse ctrl. */
63 #define TCIC_AR_WCTL 0x40 /* wait state control */
64 #define TCIC_AR_EXTERN 0x60 /* external access */
65 #define TCIC_AR_PDATA 0x80 /* programming data */
66 #define TCIC_AR_SYSCFG 0xA0 /* system configuration */
67 #define TCIC_AR_ILOCK 0xC0 /* interlock control/status */
68 #define TCIC_AR_TEST 0xE0 /* test */
69
70 /*
71 * TCIC indirect registers.
72 * These are all 16 bit.
73 * They are accessed by selecting the appropriate address in
74 * bits 9:0 of the address register with indirect register access mode
75 * enabled.
76 */
77 #define TCIC_WR_MEM_BASE 0x100 /* base address */
78 #define TCIC_WR_MEM_SHFT 3 /* log2 size of one reg set */
79 #define TCIC_WR_MEXT_N(n) ((TCIC_WR_MEM_BASE+((n)<<TCIC_WR_MEM_SHFT))+0)
80 #define TCIC_WR_MBASE_N(n) ((TCIC_WR_MEM_BASE+((n)<<TCIC_WR_MEM_SHFT))+2)
81 #define TCIC_WR_MMAP_N(n) ((TCIC_WR_MEM_BASE+((n)<<TCIC_WR_MEM_SHFT))+4)
82 #define TCIC_WR_MCTL_N(n) ((TCIC_WR_MEM_BASE+((n)<<TCIC_WR_MEM_SHFT))+6)
83
84 #define TCIC_WR_IO_BASE 0x200 /* base address */
85 #define TCIC_WR_IO_SHFT 2 /* log2 size of one reg set */
86 #define TCIC_WR_IBASE_N(n) ((TCIC_WR_IO_BASE+((n)<<TCIC_WR_IO_SHFT))+0)
87 #define TCIC_WR_ICTL_N(n) ((TCIC_WR_IO_BASE+((n)<<TCIC_WR_IO_SHFT))+2)
88
89 #define TCIC_IR_SCF_BASE 0 /* base address */
90 #define TCIC_IR_SCF_SHFT 3 /* log2 size of one reg set */
91 #define TCIC_IR_SCF1_N(n) ((TCIC_IR_SCF_BASE+((n)<<TCIC_IR_SCF_SHFT))+0)
92 #define TCIC_IR_SCF2_N(n) ((TCIC_IR_SCF_BASE+((n)<<TCIC_IR_SCF_SHFT))+2)
93
94
95 /* Bits in the ADDR2 register */
96 #define TCIC_SS_SHIFT 12 /* location of socket select bits */
97 #define TCIC_SS_MASK (7<<(TCIC_SS_SHIFT)) /* socket select mask */
98
99 #define TCIC_ADDR2_REG (1 << 15) /* select REG space */
100 #define TCIC_ADDR2_SS_SHFT TCIC_SS_SHIFT /* select sockets the usual way */
101 #define TCIC_ADDR2_SS_MASK TCIC_SS_MASK /* ditto */
102 #define TCIC_ADDR2_INDREG (1 << 11) /* access indirect registers
103 * (not card data)
104 */
105 #define TCIC_ADDR2_IO (1 << 10) /* select I/O cycles, readback
106 * card /IORD, /IOWR in diag-
107 * nostic mode.
108 */
109
110 /* Bits in address register */
111 #define TCIC_ADDR_REG (u_int32_t) TCIC_ADDR2_REG << 16) /* OR with this for REG space */
112 #define TCIC_ADDR_SS_SHFT ((u_int32_t) TCIC_ADDR2_SS_SHFT + 16)
113 /* shift count, cast so that
114 * you'll get the right type
115 * if you use it but forget
116 * to cast the left arg.
117 */
118 #define TCIC_ADDR_SS_MASK ((u_int32_t) TCIC_ADDR2_SS_MASK << 16)
119 #define TCIC_ADDR_INDREG ((u_int32_t) TCIC_ADDR2_INDREG << 16)
120 #define TCIC_ADDR_IO ((u_int32_t) TCIC_ADDR2_IO << 16)
121
122 #define TCIC_ADDR_SPACE_SIZE ((u_int32_t) 1 << 26)
123 #define TCIC_ADDR_MASK (ADDR_SPACE_SIZE - 1)
124
125 /* The following bits are defined in diagnostic mode */
126 #define TCIC_ADDR_DIAG_NREG ((u_int32_t) 1 << 31) /* inverted! */
127 #define TCIC_ADDR_DIAG_NCEH ((u_int32_t) 1 << 30)
128 #define TCIC_ADDR_DIAG_NCEL ((u_int32_t) 1 << 29)
129 #define TCIC_ADDR_DIAG_NCWR ((u_int32_t) 1 << 28)
130 #define TCIC_ADDR_DIAG_NCRD ((u_int32_t) 1 << 27)
131 #define TCIC_ADDR_DIAG_CRESET ((u_int32_t) 1 << 26)
132
133 /* Bits in socket control register */
134 #define TCIC_SCTRL_ENA (1 << 0) /* enable access to card */
135 #define TCIC_SCTRL_INCMODE (3 << 3) /* mask for increment mode: */
136 #define TCIC_SCTRL_INCMODE_AUTO (3 << 3) /* auto-increment mode */
137 #define TCIC_SCTRL_INCMODE_HOLD (0 << 3) /* byte hold mode */
138 #define TCIC_SCTRL_INCMODE_WORD (1 << 3) /* word hold mode */
139 #define TCIC_SCTRL_INCMODE_REG (2 << 3) /* reg-space increment mode */
140 #define TCIC_SCTRL_EDCSUM (1 << 5) /* if set, use checksum (not CRC) */
141 #define TCIC_SCTRL_RESET (1 << 7) /* internal software reset */
142 #define TCIC_SCTRL_RSVD 0x46 /* reserved bits, MBZ */
143
144 /* Bits in the socket status register */
145 #define TCIC_SSTAT_6US (1<<0) /* 6 usec have elapsed */
146 #define TCIC_SSTAT_10US (1<<1) /* 10 usec have elapsed */
147 #define TCIC_SSTAT_PROGTIME (1<<2) /* programming pulse timeout */
148 #define TCIC_SSTAT_LBAT1 (1<<3) /* low battery 1 */
149 #define TCIC_SSTAT_LBAT2 (1<<4) /* low battery 2 */
150 #define TCIC_SSTAT_BATOK (0<<3) /* battery is OK */
151 #define TCIC_SSTAT_BATBAD1 (1<<3) /* battery is low */
152 #define TCIC_SSTAT_BATLO (2<<3) /* battery is getting low */
153 #define TCIC_SSTAT_BATBAD2 (3<<3) /* battery is low */
154 #define TCIC_SSTAT_RDY (1<<5) /* card is ready (not busy) */
155 #define TCIC_SSTAT_WP (1<<6) /* card is write-protected */
156 #define TCIC_SSTAT_CD (1<<7) /* card present */
157 #define TCIC_SSTAT_STAT_MASK 0xf8
158
159 /* Mode register contents (R_MODE) */
160 #define TCIC_MODE_PGMMASK (0x1F) /* the programming mode bits */
161 #define TCIC_MODE_NORMAL (0) /* normal mode */
162 #define TCIC_MODE_PGMWR (1 << 0) /* assert /WR */
163 #define TCIC_MODE_PGMRD (1 << 1) /* assert /RD */
164 #define TCIC_MODE_PGMCE (1 << 2) /* assert /CEx */
165 #define TCIC_MODE_PGMDBW (1 << 3) /* databus in write mode */
166 #define TCIC_MODE_PGMWORD (1 << 4) /* word programming mode */
167
168 /* Power control register contents (R_PWR) */
169 #define TCIC_PWR_VCC_SHFT (0) /* the VCC ctl shift */
170 #define TCIC_PWR_VCC_MASK (3 << TCIC_PWR_VCC_SHFT)
171
172 #define TCIC_PWR_VPP_SHFT (3) /* the VPP ctl shift */
173 #define TCIC_PWR_VPP_MASK (3 << TCIC_PWR_VPP_SHFT)
174 #define TCIC_PWR_ENA (1 << 5) /* on 084, successors, this
175 * must be set to turn on
176 * power.
177 */
178 #define TCIC_PWR_VCC5V (1 << 2) /* enable +5 (not +3) */
179 #if 0
180 #define TCIC_PWR_VOFF_POFF (0) /* turn off VCC, VPP */
181 #define TCIC_PWR_VON_PVCC (1) /* turn on VCC, VPP=VCC */
182 #define TCIC_PWR_VON_PVPP (2) /* turn on VCC, VPP=12V */
183 #define TCIC_PWR_VON_POFF (3) /* turn on VCC, VPP=0V */
184 #endif
185 #define TCIC_PWR_VCC_N(n) (1<<((n))) /* VCCSEL for socket n */
186 #define TCIC_PWR_VPP_N(n) (1<<(3+(n))) /* VPPSEL for socket n */
187
188 #define TCIC_PWR_CLIMENA (1 << 6) /* the current-limit enable */
189 #define TCIC_PWR_CLIMSTAT (1 << 7) /* current limit sense (r/o) */
190
191 /* Bits in the icsr register. */
192 #define TCIC_ICSR_IOCHK (1<<7) /* I/O check */
193 #define TCIC_ICSR_CDCHG (1<<6) /* card status change, see SSTAT */
194 #define TCIC_ICSR_ERR (1<<5) /* error condition */
195 #define TCIC_ICSR_PROGTIME (1<<4) /* program timer ding */
196 #define TCIC_ICSR_ILOCK (1<<3) /* interlock change */
197 #define TCIC_ICSR_STOPCPU (1<<2) /* Stop CPU was asserted */
198 #define TCIC_ICSR_SET (1<<1) /* (w/o) enable writes that set bits */
199 #define TCIC_ICSR_CLEAR (1<<0) /* (w/o) enable writes that clear */
200 #define TCIC_ICSR_JAM (TCIC_ICSR_SET|TCIC_ICSR_CLEAR)
201 /* jam value into ICSR */
202
203 /* bits in the interrupt enable register */
204 #define TCIC_IENA_CDCHG (1 << 6) /* enable INT when ICSR_CDCHG is set */
205 #define TCIC_IENA_ERR (1 << 5) /* enable INT when ICSR_ERR is set */
206 #define TCIC_IENA_PROGTIME (1 << 4) /* enable INT when ICSR_PROGTIME " */
207 #define TCIC_IENA_ILOCK (1 << 3) /* enable INT when ICSR_ILOCK is set */
208 #define TCIC_IENA_CFG_MASK (3 << 0) /* select the bits for IRQ config: */
209 #define TCIC_IENA_CFG_OFF (0 << 0) /* IRQ is high-impedance */
210 #define TCIC_IENA_CFG_OD (1 << 0) /* IRQ is active low, open drain. */
211 #define TCIC_IENA_CFG_LOW (2 << 0) /* IRQ is active low, totem pole */
212 #define TCIC_IENA_CFG_HIGH (3 << 0) /* IRQ is active high, totem pole */
213 #define TCIC_IENA_RSVD 0x84 /* reserved bits, MBZ */
214
215
216 /*
217 * Bits in the auxiliary registers
218 */
219
220 /* Bits in the timing control register (AR_TCTL) */
221 #define TCIC_TCTL_6US_SHFT (0) /* the shift count for the 6 us ctr */
222 #define TCIC_TCTL_10US_SHFT (8) /* the shift count for the 10 us ctr */
223 #define TCIC_TCTL_6US_MASK (0xFF << TCIC_TCTL_6US_SHFT)
224 #define TCIC_TCTL_10US_MASK (0xFF << TCIC_TCTL_10US_SHFT)
225
226 #define TCIC_R_TCTL_6US (TCIC_R_AUX + 0) /* the byte access handle */
227 #define TCIC_R_TCTL_10US (TCIC_R_AUX + 1) /* the byte access handle */
228
229 /* Bits in the programming pulse register (AR_PCTL) */
230 #define TCIC_R_PULSE_LO (TCIC_R_AUX + 0)
231 #define TCIC_R_PULSE_HI (TCIC_R_AUX + 1)
232
233 /* Bits in the wait state control register (AR_WCTL) */
234 #define TCIC_WAIT_COUNT_MASK (0x1F) /* the count of 1/2 wait states */
235 #define TCIC_WAIT_COUNT_SHFT (0) /* the wait-count shift */
236 #define TCIC_WAIT_SYNC (1 << 5) /* set for synch, clear for asynch cycles */
237 #define TCIC_WAIT_ASYNC (0)
238
239 #define TCIC_WAIT_SENSE (1 << 6) /* select rising (1) or falling (0)
240 * edge of wait clock as reference
241 * edge.
242 */
243 #define TCIC_WAIT_SRC (1 << 7) /* select constant clock (0) or bus
244 * clock (1) as the timing source
245 */
246
247 /* Some derived constants */
248 #define TCIC_WAIT_BCLK (1 * TCIC_WAIT_SRC)
249 #define TCIC_WAIT_CCLK (0 * TCIC_WAIT_SRC)
250 #define TCIC_WAIT_RISING (1 * TCIC_WAIT_SENSE)
251 #define TCIC_WAIT_FALLING (0 * TCIC_WAIT_SENSE)
252
253 /* high byte */
254 #define TCIC_WCTL_WR (1 << 8) /* control: pulse write */
255 #define TCIC_WCTL_RD (1 << 9) /* control: pulse read */
256 #define TCIC_WCTL_CE (1 << 10) /* control: pulse chip ena */
257 #define TCIC_WCTL_LLBAT1 (1 << 11) /* status: latched LBAT1 */
258 #define TCIC_WCTL_LLBAT2 (1 << 12) /* status: latched LBAT2 */
259 #define TCIC_WCTL_LRDY (1 << 13) /* status: latched RDY */
260 #define TCIC_WCTL_LWP (1 << 14) /* status: latched WP */
261 #define TCIC_WCTL_LCD (1 << 15) /* status: latched CD */
262
263 /* The same thing, from a byte perspective */
264 #define TCIC_R_WCTL_WAIT (TCIC_R_AUX + 0) /* the wait state control byte */
265 #define TCIC_R_WCTL_XCSR (TCIC_R_AUX + 1) /* extended control/status */
266
267 #define TCIC_XCSR_WR (1 << 0) /* control: pulse write */
268 #define TCIC_XCSR_RD (1 << 1) /* control: pulse read */
269 #define TCIC_XCSR_CE (1 << 2) /* control: pulse chip ena */
270 #define TCIC_XCSR_LLBAT1 (1 << 3) /* status: latched LBAT1 */
271 #define TCIC_XCSR_LLBAT2 (1 << 4) /* status: latched LBAT2 */
272 #define TCIC_XCSR_LRDY (1 << 5) /* status: latched RDY */
273 #define TCIC_XCSR_LWP (1 << 6) /* status: latched WP */
274 #define TCIC_XCSR_LCD (1 << 7) /* status: latched CD */
275 #define TCIC_XCSR_STAT_MASK 0xf8
276
277 /* Bits in the programming data register (AR_PDATA) */
278 #define TCIC_R_PDATA_LO (TCIC_R_AUX + 0)
279 #define TCIC_R_PDATA_HI (TCIC_R_AUX + 1)
280
281 /* Bits in the system configuration register (AR_SYSCFG) */
282 /*
283 * The bottom four bits specify the steering of the socket IRQ. On
284 * the 2N, the socket IRQ is (by default) pointed at the dedicated
285 * pin.
286 */
287 #define TCIC_SYSCFG_IRQ_MASK (0xF) /* mask for this bit field. */
288 #define TCIC_SYSCFG_SSIRQDFLT (0) /* default: use SKTIRQ (2/N)
289 * disable (2/P)
290 */
291 #define TCIC_SYSCFG_SSIRQ (0x1) /* use SKTIRQ (explicit) (2/N)
292 * do not use (2/P)
293 */
294 #define TCIC_SYSCFG_SIRQ3 (0x3) /* use IRQ3 */
295 #define TCIC_SYSCFG_SIRQ4 (0x4) /* use IRQ4 */
296 #define TCIC_SYSCFG_SIRQ5 (0x5) /* use IRQ5 (2/N) */
297 #define TCIC_SYSCFG_SIRQ6 (0x6) /* use IRQ6 (2/N) */
298 #define TCIC_SYSCFG_SIRQ7 (0x7) /* use IRQ7 (2/N) */
299 #define TCIC_SYSCFG_SIRQ10 (0xA) /* use IRQ10 */
300 #define TCIC_SYSCFG_SIRQ14 (0xE) /* use IRQ14 */
301
302 #define TCIC_SYSCFG_MCSFULL (1 << 4)
303 /*
304 * If set, use full address (a[12:23]) for MCS16 generation.
305 * If clear, run in ISA-compatible mode (only using a[17:23]).
306 * With many chip sets, the TCIC-2/N's timing will will allow full
307 * address decoding to be used rather than limiting us to LA[17:23];
308 * thus we can get around the ISA spec which limits the granularity
309 * of bus sizing to 128K blocks.
310 */
311 #define TCIC_SYSCFG_IO1723 (1 << 5)
312 /*
313 * Flag indicating that LA[17:23] can be trusted to be zero during a
314 * true I/O cycle. Setting this bit will allow us to reduce power
315 * consumption further by eliminating I/O address broadcasts for
316 * memory cycles.
317 *
318 * Unfortunately, you cannot trust LA[17:23] to be zero on all systems,
319 * because the ISA specs do not require that LA[17:23] be zero when an
320 * alternate bus master runs an I/O cycle. However, on a palmtop or
321 * notebook, it is a good guess.
322 */
323
324 #define TCIC_SYSCFG_MCSXB (1 << 6)
325 /*
326 * If set, assume presence of an external buffer for MCS16: operate
327 * the driver as a totem-pole output.
328 *
329 * If clear, run in pseudo-ISA mode; output is open drain. But note
330 * that on the 082 the output buffers cannot drive a 300-ohm
331 * load.
332 */
333 #define TCIC_SYSCFG_ICSXB (1 << 7)
334 /*
335 * If set, assume presence of an external buffer for IOCS16*; operate
336 * the buffer as a totem-pole output.
337 *
338 * If clear, run in pseudo-ISA mode; output is open drain. But note
339 * that on the 082 the output buffers cannot drive a 300-ohm
340 * load.
341 */
342 #define TCIC_SYSCFG_NOPDN (1 << 8)
343 /*
344 * If set, disable the auto power-down sequencing. The chip will
345 * run card cycles somewhat more quickly (though perhaps not
346 * significantly so); but it will dissipate significantly more power.
347 *
348 * If clear, the low-power operating modes are enabled. This
349 * causes the part to go into low-power mode automatically at
350 * system reset.
351 */
352 #define TCIC_SYSCFG_MPSEL_SHFT (9)
353 #define TCIC_SYSCFG_MPSEL_MASK (7 << 9)
354 /*
355 * This field controls the operation of the multipurpose pin on the
356 * 86082. It has the following codes:
357 */
358 #define TCIC_SYSCFG_MPSEL_OFF (0 << TCIC_SYSCFG_MPSEL_SHFT)
359 /*
360 * This is the reset state; it indicates that the Multi-purpose
361 * pin is not used. The pin will be held in a high-impedance
362 * state. It can be read by monitoring SYSCFG_MPSENSE.
363 */
364 #define TCIC_SYSCFG_MPSEL_NEEDCLK (1 << TCIC_SYSCFG_MPSEL_SHFT)
365 /*
366 * NMULTI is an output.
367 * External indication that CCLK or BCLK are needed in order
368 * to complete an internal operation. External logic can use
369 * this to control the clocks coming to the chip.
370 */
371 #define TCIC_SYSCFG_MPSEL_MIO (2 << TCIC_SYSCFG_MPSEL_SHFT)
372 /*
373 * NMULTI is an input; it is an unambiguous M/IO signal, issued
374 * with timing similar to the LA[] lines.
375 */
376 #define TCIC_SYSCFG_MPSEL_EXTSEL (3 << TCIC_SYSCFG_MPSEL_SHFT)
377 /*
378 * NMULTI is an output; it is the external register select
379 * pulse, generated whenever software attempts to access
380 * aux register AR_EXTRN. Of course, the 86082 will ignore
381 * writes to AR_EXTRN, and will float the data bus if
382 * the CPU reads from AR_EXTRN.
383 */
384
385 /* (4 << TCIC_SYSCFG_MPSEL_SHFT) is reserved */
386
387 #define TCIC_SYSCFG_MPSEL_RI (5 << TCIC_SYSCFG_MPSEL_SHFT)
388 /*
389 * NMULTI is an output; it indicates a RI (active-going)
390 * transition has occurred lately on a an appropriately-
391 * configured socket. The output is active low.
392 */
393 /*
394 * Codes 4, 6 and 7 are reserved, and must NOT be output. It is
395 * indeed possibly hazardous to your system to encode values in
396 * this field that do not match your hardware!
397 */
398
399 /* 1 << 12 reserved */
400
401 #define TCIC_SYSCFG_MPSENSE (1 << 13)
402 /*
403 * This bit, when read, returns the sense of the multi-purpose pin.
404 */
405
406 #define TCIC_SYSCFG_AUTOBUSY (1 << 14)
407 /*
408 * This bit, when set, causes the busy led to be gated with the
409 * SYSCFG_ACC bit. When clear, the busy led reflects whether the
410 * socket is actually enabled. If AUTOBUSY is set and ACC is clear,
411 * then the busy light will be off, even if a socket is enabled.
412 * If AUTOBUSY is clear, then the busy light will be on if either
413 * socket is enabled.
414 *
415 * Note, that when in a programming mode, you should either clear this
416 * bit (causing the busy light to be on whenever the socket is enabled)
417 * or set both this bit and the ACC bit (causing the light to be on
418 * all the time).
419 *
420 * On the '084 and '184, this bit is per-socket.
421 */
422
423 #define TCIC_SYSCFG_ACC (1<<15)
424 /*
425 * This bit will be set automatically by the hardware whenever the CPU
426 * accesses data on a card. It can be cleared under software control.
427 *
428 * In AUTOBUSY mode, it has the additional effect of turning on the
429 * busy light.
430 *
431 * Since we'll tristate the command lines as the card is going out of
432 * the socket, and since the shared lines idle low, there's no real
433 * danger if the busy light is off even though the socket is enabled.
434 *
435 * On the '084 and '184, this bit is per-socket.
436 */
437
438
439 /* Bits in the ilock aux. register. */
440 #define TCIC_ILOCK_OUT (1 << 0) /* interlock output
441 * per-socket on x84
442 */
443 #define TCIC_ILOCK_SENSE (1 << 1) /* (r/o) interlock sense
444 * 0 -> /cilock not asserted;
445 * 1 -> /cilock is asserted.
446 * per-socket on x84.
447 */
448 #define TCIC_ILOCK_CRESET (1 << 2) /* card reset output level(S) */
449 #define TCIC_ILOCK_CRESENA (1 << 3) /* enable card reset output (S) */
450 #define TCIC_ILOCK_CWAIT (1 << 4) /* enable card wait (S) */
451 #define TCIC_ILOCK_CWAITSNS (1 << 5) /* (r/o) sense current state of wait
452 * 0 -> /cwait not asserted;
453 * 1 -> /cwait is asserted
454 * (S)
455 */
456 /* The shift count & mask for the hold-time control */
457 #define TCIC_ILOCK_HOLD_SHIFT 6 /* shift count for the hold-time ctl (G) */
458 #define TCIC_ILOCK_HOLD_MASK (3 << TCIC_ILOCK_HOLD_SHIFT)
459
460 /*
461 * Quick hold mode waits until we observe that the strobe is high,
462 * guaranteeing 10ns or so of hold time.
463 */
464 #define TCIC_ILOCK_HOLD_QUICK (0 << TCIC_ILOCK_HOLD_SHIFT)
465
466 /*
467 * CCLK hold mode waits (asynchronously) for an edge on CCLK. Minimum is 1
468 * CCLK + epsilon; maximum is 2 CCLKs + epsilon.
469 *
470 * for the 86081 & '82, this mode enables the multi-step
471 * sequencer that generates setup and hold times based on CCLK. This
472 * is the recommended mode of operation for the '81 and '82.
473 *
474 */
475 #define TCIC_ILOCK_HOLD_CCLK (3 << TCIC_ILOCK_HOLD_SHIFT)
476
477 /* The following bits are only present on the x84 and later parts */
478 #define TCIC_ILOCK_INPACK (1 << 11) /* (r/o, S) this bit is a diagnostic
479 * read-back for card input
480 * acknowledge.
481 * The sense is inverted from
482 * the level at the pin.
483 */
484 #define TCIC_ILOCK_CP0 (1 << 12) /* (r/o, S) this bit is a diagnostic
485 * monitor for card present pin 0.
486 * The sense is inverted from the
487 * level at the pin.
488 */
489 #define TCIC_ILOCK_CP1 (1 << 13) /* (r/o, S) this bit is a diagnostic
490 * monitor for card present pin 1.
491 * The sense is inverted from the
492 * level at the pin.
493 */
494 #define TCIC_ILOCK_VS1 (1 << 14) /* (r/o, S) this bit is the primary
495 * monitor for Card Voltage Sense
496 * pin 1.
497 * The sense is inverted from the
498 * level at the pin.
499 */
500 #define TCIC_ILOCK_VS2 (1 << 15) /* (r/o, S) this bit is the primary
501 * monitor for Card Voltage Sense
502 * pin 2.
503 * The sense is inverted from the
504 * level at the pin.
505 */
506 /*
507 * Silicon Version Register
508 *
509 * In diagnostic mode, the high byte of the interlock register is defined
510 * as the silicon identity byte.
511 *
512 * In order to read this byte, the chip must be placed in diagnostic
513 * mode by setting bit 15 of the TESTDIAG register. (This may or may
514 * not be enforced by the silicon.)
515 *
516 * The layout is:
517 *
518 * 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
519 * m <-------ID-------> <----ILOCK---->
520 *
521 * The fields are:
522 *
523 * m Always reset.
524 *
525 * ID This field is one of the following:
526 *
527 * 0x02 the db86082
528 * 0x03 the db86082a
529 * 0x04 the db86084
530 * 0x05 the DB86072ES, (Engineering Sample)
531 * 0x07 the db86082bES, (Engineering Sample)
532 * 0x08 the db86084a
533 * 0x14 the DB86184
534 * 0x15 the DB86072, (Production)
535 * 0x17 the db86082b, (Production)
536 */
537
538 /*
539 * Defines for Chip IDs described above.
540 *
541 * Use the following convention for defining TCIC_CHIPID_DBxxxxxY:
542 *
543 * TCIC_CHIPID_DBxxxxx_1 The First step of chip.
544 * TCIC_CHIPID_DBxxxxxA The Second step of chip.
545 * TCIC_CHIPID_DBxxxxxB The Third step of chip.
546 * TCIC_CHIPID_DBxxxxx... The ... step of chip.
547 *
548 * TCIC_CHIPID_DBxxxxx"step of chip"_ES An Engineering Sample of chip.
549 *
550 */
551 #define TCIC_CHIPID_DB86082_1 (0x02)
552 #define TCIC_CHIPID_DB86082A (0x03)
553 #define TCIC_CHIPID_DB86082B_ES (0x07)
554 #define TCIC_CHIPID_DB86082B (0x17)
555
556 #define TCIC_CHIPID_DB86084_1 (0x04)
557 #define TCIC_CHIPID_DB86084A (0x08)
558
559 #define TCIC_CHIPID_DB86184_1 (0x14)
560
561 #define TCIC_CHIPID_DB86072_1_ES (0x05)
562 #define TCIC_CHIPID_DB86072_1 (0x15)
563
564
565 /* the high order bits (in diag mode) give the chip version */
566 #define TCIC_R_ILOCK_ID (TCIC_R_AUX + 1)
567
568 #define TCIC_ILOCKTEST_ID_SHFT 8 /* the shift count */
569 #define TCIC_ILOCKTEST_ID_MASK (0x7F << TCIC_ILOCKTEST_ID_SHFT)
570 /* the mask for the field */
571 /*
572 * Use the following convention for defining TCIC_ILOCKTEST_DBxxxxxY:
573 *
574 * TCIC_ILOCKTEST_DBxxxxx_1 The First step of chip.
575 * TCIC_ILOCKTEST_DBxxxxxA The Second step of chip.
576 * TCIC_ILOCKTEST_DBxxxxxB The Third step of chip.
577 * TCIC_ILOCKTEST_DBxxxxx... The ... step of chip.
578 *
579 * TCIC_ILOCKTEST_DBxxxxx"step of chip"_ES An Engineering Sample of chip.
580 *
581 */
582 #define TCIC_ILOCKTEST_TCIC2N_1 ((TCIC_CHIPID_DB86082_1) << TCIC_ILOCKTEST_ID_SHFT)
583 #define TCIC_ILOCKTEST_DB86082_1 TCIC_ILOCKTEST_TCIC2N_1
584 #define TCIC_ILOCKTEST_TCIC2N_2 ((TCIC_CHIPID_DB86082A) << TCIC_ILOCKTEST_ID_SHFT)
585 #define TCIC_ILOCKTEST_DB86082A TCIC_ILOCKTEST_TCIC2N_2
586 #define TCIC_ILOCKTEST_TCIC2N_3 ((TCIC_CHIPID_DB86082B_ES) << TCIC_ILOCKTEST_ID_SHFT)
587 #define TCIC_ILOCKTEST_DB86082B_ES TCIC_ILOCKTEST_TCIC2N_3
588
589 #define TCIC_ILOCKTEST_DB86082B ((TCIC_CHIPID_DB86082B) << TCIC_ILOCKTEST_ID_SHFT)
590
591 #define TCIC_ILOCKTEST_DB86084_1 ((TCIC_CHIPID_DB86084_1) << TCIC_ILOCKTEST_ID_SHFT)
592 #define TCIC_ILOCKTEST_DB86084A ((TCIC_CHIPID_DB86084A) << TCIC_ILOCKTEST_ID_SHFT)
593
594 #define TCIC_ILOCKTEST_DB86184_1 ((TCIC_CHIPID_DB86184_1) << TCIC_ILOCKTEST_ID_SHFT)
595
596 #define TCIC_ILOCKTEST_DB86072_1 ((TCIC_CHIPID_DB86072_1) << TCIC_ILOCKTEST_ID_SHFT)
597 #define TCIC_ILOCKTEST_DB86072_1_ES ((TCIC_CHIPID_DB86072_1_ES) << TCIC_ILOCKTEST_ID_SHFT)
598
599
600 /* Bits in the test control register (AR_TEST) */
601 #define TCIC_R_TEST (TCIC_R_AUX + 0)
602 #define TCIC_TEST_AEN (1 << 0) /* force card AEN */
603 #define TCIC_TEST_CEN (1 << 1) /* force card CEN */
604 #define TCIC_TEST_CTR (1 << 2) /* test programming pulse, address ctrs */
605 #define TCIC_TEST_ENA (1 << 3) /* force card-present (for test), and
606 * special VPP test mode
607 */
608 #define TCIC_TEST_IO (1 << 4) /* feed back some I/O signals
609 * internally.
610 */
611 #define TCIC_TEST_OUT1 (1 << 5) /* force special address output mode */
612 #define TCIC_TEST_ZPB (1 << 6) /* enter ZPB test mode */
613 #define TCIC_TEST_WAIT (1 << 7) /* force-enable WAIT pin */
614 #define TCIC_TEST_PCTR (1 << 8) /* program counter in read-test mode */
615 #define TCIC_TEST_VCTL (1 << 9) /* force-enable power-supply controls */
616 #define TCIC_TEST_EXTA (1 << 10) /* external access doesn't override
617 || internal decoding.
618 */
619 #define TCIC_TEST_DRIVECDB (1 << 11) /* drive the card data bus all the time */
620 #define TCIC_TEST_ISTP (1 << 12) /* turn off CCLK to the interrupt CSR */
621 #define TCIC_TEST_BSTP (1 << 13) /* turn off BCLK internal to the chip */
622 #define TCIC_TEST_CSTP (1 << 14) /* turn off CCLK except to int CSR */
623 #define TCIC_TEST_DIAG (1 << 15) /* enable diagnostic read-back mode */
624
625 /* Bits in the SCF1 register */
626 #define TCIC_SCF1_IRQ_MASK (0xF) /* mask for this bit field */
627 #define TCIC_SCF1_IRQOFF (0) /* disable */
628 #define TCIC_SCF1_SIRQ (0x1) /* use SKTIRQ (2/N) */
629 #define TCIC_SCF1_IRQ3 (0x3) /* use IRQ3 */
630 #define TCIC_SCF1_IRQ4 (0x4) /* use IRQ4 */
631 #define TCIC_SCF1_IRQ5 (0x5) /* use IRQ5 */
632 #define TCIC_SCF1_IRQ6 (0x6) /* use IRQ6 */
633 #define TCIC_SCF1_IRQ7 (0x7) /* use IRQ7 */
634 #define TCIC_SCF1_IRQ9 (0x9) /* use IRQ9 */
635 #define TCIC_SCF1_IRQ10 (0xA) /* use IRQ10 */
636 #define TCIC_SCF1_IRQ11 (0xB) /* use IRQ11 */
637 #define TCIC_SCF1_IRQ12 (0xC) /* use IRQ12 */
638 #define TCIC_SCF1_IRQ14 (0xE) /* use IRQ14 */
639 #define TCIC_SCF1_IRQ15 (0xF) /* use IRQ15 */
640
641 /* XXX doc bug? -chb */
642 #define TCIC_SCF1_IRQOD (1 << 4)
643 #define TCIC_SCF1_IRQOC (0) /* selected IRQ is
644 * open-collector, and active
645 * low; otherwise it's totem-
646 * pole and active hi.
647 */
648 #define TCIC_SCF1_PCVT (1 << 5) /* convert level-mode IRQ
649 * to pulse mode, or stretch
650 * pulses from card.
651 */
652 #define TCIC_SCF1_IRDY (1 << 6) /* interrupt from RDY (not
653 * from /IREQ). Used with
654 * ATA drives.
655 */
656 #define TCIC_SCF1_ATA (1 << 7) /* Special ATA drive mode.
657 * CEL/H become CE1/2 in
658 * the IDE sense; CEL is
659 * activated for even window
660 * matches, and CEH for
661 * odd window matches.
662 */
663 #define TCIC_SCF1_DMA_SHIFT 8 /* offset to DMA selects; */
664 #define TCIC_SCF1_DMA_MASK (0x7 << IRSCFG_DMA_SHIFT)
665
666 #define TCIC_SCF1_DMAOFF (0 << IRSCFG_DMA_SHIFT) /* disable DMA */
667 #define TCIC_SCF1_DREQ2 (2 << IRSCFG_DMA_SHIFT) /* enable DMA on DRQ2 */
668
669 #define TCIC_SCF1_IOSTS (1 << 11) /* enable I/O status mode;
670 * allows CIORD/CIOWR to
671 * become low-Z.
672 */
673 #define TCIC_SCF1_SPKR (1 << 12) /* enable SPKR output from
674 * this card
675 */
676 #define TCIC_SCF1_FINPACK (1 << 13) /* force card input
677 * acknowledge during I/O
678 * cycles. Has no effect
679 * if no windows map to card
680 */
681 #define TCIC_SCF1_DELWR (1 << 14) /* force -all- data to
682 * meet 60ns setup time
683 * ("DELay WRite")
684 */
685 #define TCIC_SCF1_HD7IDE (1 << 15) /* Enable special IDE
686 * data register mode: odd
687 * byte addresses in odd
688 * I/O windows will not
689 * drive HD7.
690 */
691
692 /* Bits in the scrf2 register */
693 #define TCIC_SCF2_RI (1 << 0) /* enable RI pin from STSCHG
694 * (2/N)
695 `*/
696 #define TCIC_SCF2_IDBR (1 << 1) /* force I/O data bus routing
697 * for this socket, regardless
698 * of cycle type. (2/N)
699 `*/
700 #define TCIC_SCF2_MDBR (1 << 2) /* force memory window data
701 * bus routing for this
702 * socket, regardless of cycle
703 * type. (2/N)
704 */
705 #define TCIC_SCF2_MLBAT1 (1 << 3) /* disable status change
706 * ints from LBAT1 (or
707 * "STSCHG"
708 */
709 #define TCIC_SCF2_MLBAT2 (1 << 4) /* disable status change
710 * ints from LBAT2 (or "SPKR")
711 */
712 #define TCIC_SCF2_MRDY (1 << 5) /* disable status change ints
713 * from RDY/BSY (or /IREQ).
714 * note that you get ints on
715 * both high- and low-going
716 * edges if this is enabled.
717 */
718 #define TCIC_SCF2_MWP (1 << 6) /* disable status-change ints
719 * from WP (or /IOIS16).
720 * If you're using status
721 * change ints, you better set
722 * this once an I/O window is
723 * enabled, before accessing
724 * it.
725 */
726 #define TCIC_SCF2_MCD (1 << 7) /* disable status-change ints
727 * from Card Detect.
728 */
729
730 /*
731 * note that these bits match the top 5 bits of the socket status register
732 * in order and sense.
733 */
734 #define TCIC_SCF2_DMASRC_MASK (0x3 << 8) /* mask for this bit field */
735 /*-- DMA Source --*/
736 #define TCIC_SCF2_DRQ_BVD2 (0x0 << 8) /* BVD2 */
737 #define TCIC_SCF2_DRQ_IOIS16 (0x1 << 8) /* IOIS16 */
738 #define TCIC_SCF2_DRQ_INPACK (0x2 << 8) /* INPACK */
739 #define TCIC_SCF2_DRQ_FORCE (0x3 << 8) /* Force it */
740
741 #define TCIC_SCFS2_RSVD (0xFC00) /* top 6 bits are RFU */
742
743 /* Bits in the MBASE window registers */
744 #define TCIC_MBASE_4K (1 << 14) /* window size is 4K */
745 #define TCIC_MBASE_ADDR_MASK 0x0fff /* bits holding the address */
746
747 /* Bits in the MMAP window registers */
748 #define TCIC_MMAP_ATTR (1 << 15) /* map attr or common space */
749 #define TCIC_MMAP_ADDR_MASK 0x3fff /* bits holding the address */
750
751 /* Bits in the MCTL window registers */
752 #define TCIC_MCTL_ENA (1 << 15) /* enable this window */
753 #define TCIC_MCTL_SS_SHIFT 12
754 #define TCIC_MCTL_SS_MASK (7 << TCIC_MCTL_SS_SHIFT) /* which socket does this window map to */
755 #define TCIC_MCTL_B8 (1 << 11) /* 8/16 bit access select */
756 #define TCIC_MCTL_EDC (1 << 10) /* do EDC calc. on access */
757 #define TCIC_MCTL_KE (1 << 9) /* accesses are cacheable */
758 #define TCIC_MCTL_ACC (1 << 8) /* window has been accessed */
759 #define TCIC_MCTL_WP (1 << 7) /* window is write protected */
760 #define TCIC_MCTL_QUIET (1 << 6) /* enable quiet socket mode */
761 #define TCIC_MCTL_WSCNT_MASK 0x0f /* wait state counter */
762
763 /* Bits in the ICTL window registers */
764 #define TCIC_ICTL_ENA (1 << 15) /* enable this windo */
765 #define TCIC_ICTL_SS_SHIFT 12
766 #define TCIC_ICTL_SS_MASK (7 << TCIC_ICTL_SS_SHIFT) /* which socket does this window map to */
767 #define TCIC_ICTL_AUTOSZ 0 /* auto size 8/16 bit acc. */
768 #define TCIC_ICTL_B8 (1 << 11) /* all accesses 8 bit */
769 #define TCIC_ICTL_B16 (1 << 10) /* all accesses 16 bit */
770 #define TCIC_ICTL_ATA (3 << 10) /* special ATA mode */
771 #define TCIC_ICTL_TINY (1 << 9) /* window size 1 byte */
772 #define TCIC_ICTL_ACC (1 << 8) /* window has been accessed */
773 #define TCIC_ICTL_1K (1 << 7) /* only 10 bits io decoding */
774 #define TCIC_ICTL_QUIET (1 << 6) /* enable quiet socket mode */
775 #define TCIC_ICTL_PASS16 (1 << 5) /* pass all 16 bits to card */
776 #define TCIC_ICTL_WSCNT_MASK 0x0f /* wait state counter */
777
778 /* Various validity tests */
779 /*
780 * From Databook sample source:
781 * MODE_AR_SYSCFG must have, with j = ***read*** (***, R_AUX)
782 * and k = (j>>9)&7:
783 * if (k&4) k == 5
784 * And also:
785 * j&0x0f is none of 2, 8, 9, b, c, d, f
786 * if (j&8) must have (j&3 == 2)
787 * Can't have j==2
788 */
789 #if 0
790 /* this is from the Databook sample code and apparently is wrong */
791 #define INVALID_AR_SYSCFG(x) ((((x)&0x1000) && (((x)&0x0c00) != 0x0200)) \
792 || (((((x)&0x08) == 0) || (((x)&0x03) == 2)) \
793 && ((x) != 0x02)))
794 #else
795 #define INVALID_AR_SYSCFG(x) ((((x)&0x0800) && (((x)&0x0600) != 0x0100)) \
796 || ((((((x)&0x08) == 0) && (((x)&0x03) == 2)) \
797 || (((x)&0x03) == 2)) \
798 && ((x) != 0x02)))
799 #endif
800 /* AR_ILOCK must have bits 6 and 7 the same: */
801 #define INVALID_AR_ILOCK(x) (((x)&0xc0)==0 || (((x)&0xc0)==0xc0))
802
803 /* AR_TEST has some reserved bits: */
804 #define INVALID_AR_TEST(x) (((x)&0154) != 0)
805
806
807 #define TCIC_IO_WINS 2
808 #define TCIC_MAX_MEM_WINS 5
809
810 /*
811 * Memory window addresses refer to bits A23-A12 of the ISA system memory
812 * address. This is a shift of 12 bits. The LSB contains A19-A12, and the
813 * MSB contains A23-A20, plus some other bits.
814 */
815
816 #define TCIC_MEM_SHIFT 12
817 #define TCIC_MEM_PAGESIZE (1<<TCIC_MEM_SHIFT)
818
819 #endif /* _TCIC2REG_H */
NetBSD on the FriendlyARM MINI2440