sys/dev/ic/wereg.h

   1 /*      $NetBSD: wereg.h,v 1.1 2001/03/23 17:34:41 jdolecek Exp $       */
   2
   3 /*
   4  * National Semiconductor DS8390 NIC register definitions.
   5  *
   6  * Copyright (C) 1993, David Greenman.  This software may be used, modified,
   7  * copied, distributed, and sold, in both source and binary form provided that
   8  * the above copyright and these terms are retained.  Under no circumstances is
   9  * the author responsible for the proper functioning of this software, nor does
  10  * the author assume any responsibility for damages incurred with its use.
  11  */
  12
  13 /*
  14  *              Definitions for Western digital/SMC WD80x3 series ASIC
  15  */
  16
  17 /*
  18  * Memory Select Register (MSR)
  19  */
  20 #define WE_MSR  0
  21
  22 /* next three definitions for Toshiba */
  23 #define WE_MSR_POW      0x02    /* 0 = power save, 1 = normal (R/W) */
  24 #define WE_MSR_BSY      0x04    /* gate array busy (R) */
  25 #define WE_MSR_LEN      0x20    /* 0 = 16-bit, 1 = 8-bit (R/W) */
  26
  27 #define WE_MSR_ADDR     0x3f    /* Memory decode bits 18-13 */
  28 #define WE_MSR_MENB     0x40    /* Memory enable */
  29 #define WE_MSR_RST      0x80    /* Reset board */
  30
  31 /*
  32  * Interface Configuration Register (ICR)
  33  */
  34 #define WE_ICR  1
  35
  36 #define WE_ICR_16BIT    0x01    /* 16-bit interface */
  37 #define WE_ICR_OAR      0x02    /* select register (0=BIO 1=EAR) */
  38 #define WE_ICR_IR2      0x04    /* high order bit of encoded IRQ */
  39 #define WE_ICR_MSZ      0x08    /* memory size (0=8k 1=32k) */
  40 #define WE_ICR_RLA      0x10    /* recall LAN address */
  41 #define WE_ICR_RX7      0x20    /* recall all but i/o and LAN address */
  42 #define WE_ICR_RIO      0x40    /* recall i/o address */
  43 #define WE_ICR_STO      0x80    /* store to non-volatile memory */
  44 #ifdef TOSH_ETHER
  45 #define WE_ICR_MEM      0xe0    /* shared mem address A15-A13 (R/W) */
  46 #define WE_ICR_MSZ1     0x0f    /* memory size, 0x08 = 64K, 0x04 = 32K,
  47                                    0x02 = 16K, 0x01 = 8K */
  48                                 /* 64K can only be used if mem address
  49                                    above 1MB */
  50                                 /* IAR holds address A23-A16 (R/W) */
  51 #endif
  52
  53 /*
  54  * IO Address Register (IAR)
  55  */
  56 #define WE_IAR  2
  57
  58 /*
  59  * EEROM Address Register
  60  */
  61 #define WE_EAR  3
  62
  63 /*
  64  * Interrupt Request Register (IRR)
  65  */
  66 #define WE_IRR  4
  67
  68 #define WE_IRR_0WS      0x01    /* use 0 wait-states on 8 bit bus */
  69 #define WE_IRR_OUT1     0x02    /* WD83C584 pin 1 output */
  70 #define WE_IRR_OUT2     0x04    /* WD83C584 pin 2 output */
  71 #define WE_IRR_OUT3     0x08    /* WD83C584 pin 3 output */
  72 #define WE_IRR_FLASH    0x10    /* Flash RAM is in the ROM socket */
  73
  74 /*
  75  * The three bits of the encoded IRQ are decoded as follows:
  76  *
  77  * IR2 IR1 IR0  IRQ
  78  *  0   0   0   2/9
  79  *  0   0   1   3
  80  *  0   1   0   5
  81  *  0   1   1   7
  82  *  1   0   0   10
  83  *  1   0   1   11
  84  *  1   1   0   15
  85  *  1   1   1   4
  86  */
  87 #define WE_IRR_IR0      0x20    /* bit 0 of encoded IRQ */
  88 #define WE_IRR_IR1      0x40    /* bit 1 of encoded IRQ */
  89 #define WE_IRR_IEN      0x80    /* Interrupt enable */
  90
  91 /*
  92  * LA Address Register (LAAR)
  93  */
  94 #define WE_LAAR 5
  95
  96 #define WE_LAAR_ADDRHI  0x1f    /* bits 23-19 of RAM address */
  97 #define WE_LAAR_0WS16   0x20    /* enable 0 wait-states on 16 bit bus */
  98 #define WE_LAAR_L16EN   0x40    /* enable 16-bit operation */
  99 #define WE_LAAR_M16EN   0x80    /* enable 16-bit memory access */
 100
 101 /* i/o base offset to station address/card-ID PROM */
 102 #define WE_PROM 8
 103
 104 /*
 105  *      83C790 specific registers
 106  */
 107 /*
 108  * Hardware Support Register (HWR) ('790)
 109  */
 110 #define WE790_HWR       4
 111
 112 #define WE790_HWR_RST   0x10    /* hardware reset */
 113 #define WE790_HWR_LPRM  0x40    /* LAN PROM select */
 114 #define WE790_HWR_SWH   0x80    /* switch register set */
 115
 116 /*
 117  * ICR790 Interrupt Control Register for the 83C790
 118  */
 119 #define WE790_ICR       6
 120
 121 #define WE790_ICR_EIL   0x01    /* enable interrupts */
 122
 123 /*
 124  * REV/IOPA Revision / I/O Pipe register for the 83C79X
 125  */
 126 #define WE790_REV       7
 127
 128 #define WE790_REV_790   0x20
 129 #define WE790_REV_795   0x40
 130
 131 /*
 132  * 79X RAM Address Register (RAR)
 133  *      Enabled with SWH bit=1 in HWR register
 134  */
 135
 136 #define WE790_RAR       0x0b
 137
 138 #define WE790_RAR_SZ8   0x00    /* 8k memory buffer */
 139 #define WE790_RAR_SZ16  0x10    /* 16k memory buffer */
 140 #define WE790_RAR_SZ32  0x20    /* 32k memory buffer */
 141 #define WE790_RAR_SZ64  0x30    /* 64k memory buffer */
 142
 143 /*
 144  * General Control Register (GCR)
 145  * Enabled with SWH bit == 1 in HWR register
 146  */
 147 #define WE790_GCR       0x0d
 148
 149 #define WE790_GCR_LIT   0x01    /* on for UTP */
 150 #define WE790_GCR_GPOUT 0x02    /* if BNC is enabled */
 151 #define WE790_GCR_IR0   0x04    /* bit 0 of encoded IRQ */
 152 #define WE790_GCR_IR1   0x08    /* bit 1 of encoded IRQ */
 153 #define WE790_GCR_ZWSEN 0x20    /* zero wait state enable */
 154 #define WE790_GCR_IR2   0x40    /* bit 2 of encoded IRQ */
 155 /*
 156  * The three bits of the encoded IRQ are decoded as follows:
 157  *
 158  * IR2 IR1 IR0  IRQ
 159  *  0   0   0   none
 160  *  0   0   1   9
 161  *  0   1   0   3
 162  *  0   1   1   5
 163  *  1   0   0   7
 164  *  1   0   1   10
 165  *  1   1   0   11
 166  *  1   1   1   15
 167  */
 168
 169 /* i/o base offset to CARD ID */
 170 #define WE_CARD_ID      WE_PROM+6
 171
 172 /* Board type codes in card ID */
 173 #define WE_TYPE_WD8003S         0x02
 174 #define WE_TYPE_WD8003E         0x03
 175 #define WE_TYPE_WD8013EBT       0x05
 176 #define WE_TYPE_TOSHIBA1        0x11    /* named PCETA1 */
 177 #define WE_TYPE_TOSHIBA2        0x12    /* named PCETA2 */
 178 #define WE_TYPE_TOSHIBA3        0x13    /* named PCETB */
 179 #define WE_TYPE_TOSHIBA4        0x14    /* named PCETC */
 180 #define WE_TYPE_WD8003W         0x24
 181 #define WE_TYPE_WD8003EB        0x25
 182 #define WE_TYPE_WD8013W         0x26
 183 #define WE_TYPE_WD8013EP        0x27
 184 #define WE_TYPE_WD8013WC        0x28
 185 #define WE_TYPE_WD8013EPC       0x29
 186 #define WE_TYPE_SMC8216T        0x2a
 187 #define WE_TYPE_SMC8216C        0x2b
 188 #define WE_TYPE_WD8013EBP       0x2c
 189
 190 /* Bit definitions in card ID */
 191 #define WE_REV_MASK             0x1f    /* Revision mask */
 192 #define WE_SOFTCONFIG           0x20    /* Soft config */
 193 #define WE_LARGERAM             0x40    /* Large RAM */
 194 #define WE_MICROCHANEL          0x80    /* Microchannel bus (vs. isa) */
 195
 196 /*
 197  * Checksum total.  All 8 bytes in station address PROM will add up to this.
 198  */
 199 #ifdef TOSH_ETHER
 200 #define WE_ROM_CHECKSUM_TOTAL   0xA5
 201 #else
 202 #define WE_ROM_CHECKSUM_TOTAL   0xFF
 203 #endif
 204
 205 #define WE_NIC_OFFSET           0x10    /* I/O base offset to NIC */
 206 #define WE_ASIC_OFFSET          0       /* I/O base offset to ASIC */
 207 #define WE_NIC_NPORTS           16
 208 #define WE_ASIC_NPORTS          16
 209 #define WE_NPORTS               (WE_NIC_NPORTS + WE_ASIC_NPORTS)
 210
 211 #define WE_PAGE_OFFSET  0       /* page offset for NIC access to mem */