4 * Copyright (c) 1994, Matthew E. Kimmel. Permission is hereby granted
5 * to use, copy, modify and distribute this software provided that both
6 * the copyright notice and this permission notice appear in all copies
7 * of the software, derivative works or modified versions, and any
12 * 3COM Etherlink 3C501 Register Definitions
18 #define EL_RXS 0x6 /* Receive status register */
19 #define EL_RXC 0x6 /* Receive command register */
20 #define EL_TXS 0x7 /* Transmit status register */
21 #define EL_TXC 0x7 /* Transmit command register */
22 #define EL_GPBL 0x8 /* GP buffer ptr low byte */
23 #define EL_GPBH 0x9 /* GP buffer ptr high byte */
24 #define EL_RBL 0xa /* Receive buffer ptr low byte */
25 #define EL_RBC 0xa /* Receive buffer clear */
26 #define EL_RBH 0xb /* Receive buffer ptr high byte */
27 #define EL_EAW 0xc /* Ethernet address window */
28 #define EL_AS 0xe /* Auxillary status register */
29 #define EL_AC 0xe /* Auxillary command register */
30 #define EL_BUF 0xf /* Data buffer */
32 /* Receive status register bits */
33 #define EL_RXS_OFLOW 0x01 /* Overflow error */
34 #define EL_RXS_FCS 0x02 /* FCS error */
35 #define EL_RXS_DRIB 0x04 /* Dribble error */
36 #define EL_RXS_SHORT 0x08 /* Short frame */
37 #define EL_RXS_NOFLOW 0x10 /* No overflow */
38 #define EL_RXS_GOOD 0x20 /* Received good frame */
39 #define EL_RXS_STALE 0x80 /* Stale receive status */
41 /* Receive command register bits */
42 #define EL_RXC_DISABLE 0x00 /* Receiver disabled */
43 #define EL_RXC_DOFLOW 0x01 /* Detect overflow */
44 #define EL_RXC_DFCS 0x02 /* Detect FCS errs */
45 #define EL_RXC_DDRIB 0x04 /* Detect dribble errors */
46 #define EL_RXC_DSHORT 0x08 /* Detect short frames */
47 #define EL_RXC_DNOFLOW 0x10 /* Detect frames w/o overflow ??? */
48 #define EL_RXC_AGF 0x20 /* Accept Good Frames */
49 #define EL_RXC_PROMISC 0x40 /* Promiscuous mode */
50 #define EL_RXC_ABROAD 0x80 /* Accept address, broadcast */
51 #define EL_RXC_AMULTI 0xc0 /* Accept address, multicast */
53 /* Transmit status register bits */
54 #define EL_TXS_UFLOW 0x01 /* Underflow */
55 #define EL_TXS_COLL 0x02 /* Collision */
56 #define EL_TXS_COLL16 0x04 /* Collision 16 */
57 #define EL_TXS_READY 0x08 /* Ready for new frame */
59 /* Transmit command register bits */
60 #define EL_TXC_DUFLOW 0x01 /* Detect underflow */
61 #define EL_TXC_DCOLL 0x02 /* Detect collisions */
62 #define EL_TXC_DCOLL16 0x04 /* Detect collision 16 */
63 #define EL_TXC_DSUCCESS 0x08 /* Detect success */
65 /* Auxillary status register bits */
66 #define EL_AS_RXBUSY 0x01 /* Receive busy */
67 #define EL_AS_DMADONE 0x10 /* DMA finished */
68 #define EL_AS_TXBUSY 0x80 /* Transmit busy */
70 /* Auxillary command register bits */
71 #define EL_AC_HOST 0x00 /* System bus can access buffer */
72 #define EL_AC_IRQE 0x01 /* IRQ enable */
73 #define EL_AC_TXBAD 0x02 /* Transmit frames with bad FCS */
74 #define EL_AC_TXFRX 0x04 /* Transmit followed by receive */
75 #define EL_AC_RX 0x08 /* Receive */
76 #define EL_AC_LB 0x0c /* Loopback */
77 #define EL_AC_DRQ 0x20 /* DMA request */
78 #define EL_AC_RIDE 0x40 /* DRQ and IRQ enabled */
79 #define EL_AC_RESET 0x80 /* Reset */
81 /* Packet buffer size */
82 #define EL_BUFSIZ 2048