sys/dev/isa/sbreg.h

   1 /*      $NetBSD: sbreg.h,v 1.29.30.1 2005/01/17 19:31:11 skrll Exp $    */
   2
   3 /*
   4  * Copyright (c) 1991-1993 Regents of the University of California.
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  * 3. All advertising materials mentioning features or use of this software
  16  *    must display the following acknowledgement:
  17  *      This product includes software developed by the Computer Systems
  18  *      Engineering Group at Lawrence Berkeley Laboratory.
  19  * 4. Neither the name of the University nor of the Laboratory may be used
  20  *    to endorse or promote products derived from this software without
  21  *    specific prior written permission.
  22  *
  23  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
  24  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  25  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  26  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
  27  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  28  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  29  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  30  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  31  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  32  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  33  * SUCH DAMAGE.
  34  *
  35  *      From: Header: sbreg.h,v 1.3 93/07/18 14:07:28 mccanne Exp (LBL)
  36  */
  37
  38 /*
  39  * SoundBlaster register definitions.
  40  * See "The Developer Kit for Sound Blaster Series, User's Guide" for more
  41  * complete information (avialable from Creative Labs, Inc.).  We refer
  42  * to this documentation as "SBK".
  43  *
  44  * We handle two types of cards: the basic SB version 2.0+, and
  45  * the SB PRO.  There are several distinct pieces of the hardware:
  46  *
  47  *   joystick port      (independent of I/O base address)
  48  *   FM synth           (stereo on PRO)
  49  *   mixer              (PRO only)
  50  *   DSP (sic)
  51  *   CD-ROM             (PRO only)
  52  *
  53  * The MIDI capabilities are handled by the DSP unit.
  54  */
  55
  56 /*
  57  * Address map.  The SoundBlaster can be configured (via jumpers) for
  58  * either base I/O address 0x220 or 0x240.  The encodings below give
  59  * the offsets to specific SB ports.  SBP stands for SB port offset.
  60  */
  61 #define SBP_LFM_STATUS          0       /* R left FM status port */
  62 #define SBP_LFM_ADDR            0       /* W left FM address register */
  63 #define SBP_LFM_DATA            1       /* RW left FM data port */
  64 #define SBP_RFM_STATUS          2       /* R right FM status port */
  65 #define SBP_RFM_ADDR            2       /* W right FM address register */
  66 #define SBP_RFM_DATA            3       /* RW right FM data port */
  67
  68 #define SBP_FM_STATUS           8       /* R FM status port */
  69 #define SBP_FM_ADDR             8       /* W FM address register */
  70 #define SBP_FM_DATA             9       /* RW FM data port */
  71 #define SBP_MIXER_ADDR          4       /* W mixer address register */
  72 #define SBP_MIXER_DATA          5       /* RW mixer data port */
  73
  74 #define SBP_MIX_RESET           0x00    /* mixer reset port, value */
  75 #define SBP_1335_MASTER_VOL     0x02
  76 #define SBP_1335_MIDI_VOL       0x06
  77 #define SBP_1335_CD_VOL         0x08
  78 #define SBP_1335_VOICE_VOL      0x0A
  79
  80 #define SBP_VOICE_VOL           0x04
  81 #define SBP_MIC_VOL             0x0A    /* warning: only one channel of volume... */
  82 #define SBP_MASTER_VOL          0x22
  83 #define SBP_MIDI_VOL            0x26
  84 #define SBP_CD_VOL              0x28
  85 #define SBP_LINE_VOL            0x2E
  86
  87 #define SBP_RECORD_SOURCE       0x0C
  88 #define SBP_STEREO              0x0E
  89 #define         SBP_PLAYMODE_STEREO     0x2
  90 #define         SBP_PLAYMODE_MONO       0x0
  91 #define         SBP_PLAYMODE_MASK       0x2
  92 #define SBP_OUTFILTER           0x0E
  93 #define SBP_INFILTER            0x0C
  94
  95 #define SBP_RECORD_FROM(src, filteron, high) ((src) | (filteron) | (high))
  96 #define         SBP_FILTER_ON           0x0
  97 #define         SBP_FILTER_OFF          0x20
  98 #define         SBP_IFILTER_MASK        0x28
  99 #define         SBP_OFILTER_MASK        0x20
 100 #define         SBP_IFILTER_LOW         0
 101 #define         SBP_IFILTER_HIGH        0x08
 102 #define         SBP_FROM_MIC            0x00
 103 #define         SBP_FROM_CD             0x02
 104 #define         SBP_FROM_LINE           0x06
 105
 106 #define SBP_SET_IRQ             0x80    /* Soft-configured irq (SB16-) */
 107 #define SBP_SET_DRQ             0x81    /* Soft-configured drq (SB16-) */
 108 #define SBP_IRQ_STATUS          0x82    /* Pending IRQ status (SB16-) */
 109 #define         SBP_IRQ_MPU401  0x04
 110 #define         SBP_IRQ_DMA16   0x02
 111 #define         SBP_IRQ_DMA8    0x01
 112 #define SBP_MPU_ADDR            0x84    /* Vibra16 register */
 113
 114 #define SB16P_MASTER_L          0x30
 115 #define SB16P_VOICE_L           0x32
 116 #define SB16P_MIDI_L            0x34
 117 #define SB16P_CD_L              0x36
 118 #define SB16P_LINE_L            0x38
 119 #define SB16P_MIC_L             0x3a
 120 #define SB16P_PCSPEAKER         0x3b
 121 #define SB16P_OSWITCH           0x3c
 122 #define SB16P_ISWITCH_L         0x3d
 123 #define SB16P_ISWITCH_R         0x3e
 124 #define         SB16P_SW_MIC    0x01
 125 #define         SB16P_SW_CD_R   0x02
 126 #define         SB16P_SW_CD_L   0x04
 127 #define         SB16P_SW_CD     (SB16P_SW_CD_L|SB16P_SW_CD_R)
 128 #define         SB16P_SW_LINE_R 0x08
 129 #define         SB16P_SW_LINE_L 0x10
 130 #define         SB16P_SW_LINE   (SB16P_SW_LINE_L|SB16P_SW_LINE_R)
 131 #define         SB16P_SW_MIDI_R 0x20
 132 #define         SB16P_SW_MIDI_L 0x40
 133 #define         SB16P_SW_MIDI   (SB16P_SW_MIDI_L|SB16P_SW_MIDI_R)
 134 #define SB16P_INPUT_GAIN_L      0x3f
 135 #define SB16P_OUTPUT_GAIN_L     0x41
 136 #define SB16P_TREBLE_L          0x44
 137 #define SB16P_BASS_L            0x46
 138 #define SB16P_L_TO_R(l) ((l)+1)
 139
 140 #define SB16P_AGC               0x43
 141
 142 #define SBP_RECORD_SOURCE_L     0x3d
 143 #define SBP_RECORD_SOURCE_R     0x3e
 144 #define         SBP_MIDI_SRC_R  0x20
 145 #define         SBP_LINE_SRC_R  0x08
 146 #define         SBP_CD_SRC_R    0x02
 147 #define         SBP_MIC_SRC     0x01
 148 #define SB_SRC_R_TO_L(x) ((x) << 1)
 149
 150 #define SB_STEREO_GAIN(left, right) ((left) | ((right) >> 4))
 151 #define SB_MIC_GAIN(v) ((v) >> 5)
 152
 153 #define SB_ADJUST_MIC_GAIN(sc, x) sbdsp_adjust((x), ISSB16CLASS(sc) ? 0xf8 : 0xc0)
 154 #define SB_ADJUST_GAIN(sc, x)     sbdsp_adjust((x), ISSB16CLASS(sc) ? 0xf8 : 0xe0)
 155 #define SB_ADJUST_2_GAIN(sc, x)   sbdsp_adjust((x), 0xc0)
 156
 157 #define SB_1335_GAIN(x) ((x) >> 4)
 158 #define SB_1335_MASTER_GAIN(x) ((x) >> 5)
 159
 160 #define SBP_DSP_RESET           6       /* W reset port */
 161 #define         SB_MAGIC        0xaa    /* card outputs on successful reset */
 162 #define SBP_DSP_READ            10      /* R read port */
 163 #define SBP_DSP_WRITE           12      /* W write port */
 164 #define SBP_DSP_WSTAT           12      /* R write status */
 165 #define SBP_DSP_RSTAT           14      /* R read status */
 166 #define         SB_DSP_BUSY     0x80
 167 #define         SB_DSP_READY    0x80
 168 #define SBP_DSP_IRQACK8         14      /* R acknowledge DSP IRQ, 8-bit */
 169 #define SBP_DSP_IRQACK16        15      /* R acknowledge DSP IRQ, 16-bit */
 170 #define SBP_CDROM_DATA          16      /* RW send cmds/recv data */
 171 #define SBP_CDROM_STATUS        17      /* R status port */
 172 #define SBP_CDROM_RESET         18      /* W reset register */
 173 #define SBP_CDROM_ENABLE        19      /* W enable register */
 174
 175 #define SBP_NPORT       24
 176 #define SB_NPORT        16
 177 #define SB_NMPUPORT     2
 178
 179 /*
 180  * DSP commands.  This unit handles MIDI and audio capabilities.
 181  * The DSP can be reset, data/commands can be read or written to it,
 182  * and it can generate interrupts.  Interrupts are generated for MIDI
 183  * input or DMA completion.  They seem to have neglected the fact
 184  * that it would be nice to have a MIDI transmission complete interrupt.
 185  * Worse, the DMA engine is half-duplex.  This means you need to do
 186  * (timed) programmed I/O to be able to record and play simulataneously.
 187  */
 188 #define SB_DSP_DACWRITE         0x10    /* programmed I/O write to DAC */
 189 #define SB_DSP_WDMA             0x14    /* begin 8-bit linear DMA output */
 190 #define SB_DSP_WDMA_2           0x16    /* begin 2-bit ADPCM DMA output */
 191 #define SB_DSP_WDMA_LOOP        0x1C    /* begin 8-bit linear DMA output loop */
 192 #define SB_DSP_ADCREAD          0x20    /* programmed I/O read from ADC */
 193 #define SB_DSP_RDMA             0x24    /* begin 8-bit linear DMA input */
 194 #define SB_DSP_RDMA_LOOP        0x2C    /* begin 8-bit linear DMA input loop */
 195 #define SB_MIDI_POLL            0x30    /* initiate a polling read for MIDI */
 196 #define SB_MIDI_READ            0x31    /* read a MIDI byte on recv intr */
 197 #define SB_MIDI_UART_POLL       0x34    /* enter UART mode w/ read polling */
 198 #define SB_MIDI_UART_INTR       0x35    /* enter UART mode w/ read intrs */
 199 #define SB_MIDI_WRITE           0x38    /* write a MIDI byte (non-UART mode) */
 200 #define SB_DSP_TIMECONST        0x40    /* set ADAC time constant */
 201 #define SB_DSP16_OUTPUTRATE     0x41    /* set ADAC output rate */
 202 #define SB_DSP16_INPUTRATE      0x42    /* set ADAC input rate */
 203 #define SB_DSP_BLOCKSIZE        0x48    /* set blk size for high speed xfer */
 204 #define SB_DSP_WDMA_4           0x74    /* begin 4-bit ADPCM DMA output */
 205 #define SB_DSP_WDMA_2_6         0x76    /* begin 2.6-bit ADPCM DMA output */
 206 #define SB_DSP_SILENCE          0x80    /* send a block of silence */
 207 #define SB_DSP_HS_OUTPUT        0x90    /* set high speed mode for wdma */
 208 #define SB_DSP_HS_INPUT         0x98    /* set high speed mode for rdma */
 209 #define SB_DSP_RECORD_MONO      0xA0    /* set mono recording */
 210 #define SB_DSP_RECORD_STEREO    0xA8    /* set stereo recording */
 211 #define SB_DSP16_WDMA_16        0xB6    /* begin 16-bit linear output */
 212 #define SB_DSP16_RDMA_16        0xBE    /* begin 16-bit linear input */
 213 #define SB_DSP16_WDMA_8         0xC6    /* begin 8-bit linear output */
 214 #define SB_DSP16_RDMA_8         0xCE    /* begin 8-bit linear input */
 215 #define SB_DSP_HALT             0xd0    /* suspend 8-bit DMA */
 216 #define SB_DSP_SPKR_ON          0xd1    /* turn speaker on */
 217 #define SB_DSP_SPKR_OFF         0xd3    /* turn speaker off */
 218 #define SB_DSP_CONT             0xd4    /* continue 8-bit DMA */
 219 #define SB_DSP16_HALT           0xd5    /* suspend 16-bit DMA */
 220 #define SB_DSP16_CONT           0xd6    /* continue 16-bit DMA */
 221 #define SB_DSP_RD_SPKR          0xd8    /* get speaker status */
 222 #define         SB_SPKR_OFF     0x00
 223 #define         SB_SPKR_ON      0xff
 224 #define SB_DSP_VERSION          0xe1    /* get version number */
 225
 226 #define SB_BMODE_UNSIGNED       0x00
 227 #define SB_BMODE_SIGNED         0x10
 228 #define SB_BMODE_STEREO         0x20
 229
 230 /* Some of these come from linux driver (It serves as convenient unencumbered
 231    documentation) */
 232 #define JAZZ16_READ_VER         0xFA    /* 0x12 means ProSonic/Jazz16? */
 233 #define         JAZZ16_VER_JAZZ 0x12
 234 #define JAZZ16_SET_DMAINTR      0xFB
 235
 236 #define JAZZ16_CONFIG_PORT      0x201
 237 #define JAZZ16_WAKEUP           0xAF
 238 #define JAZZ16_SETBASE          0x50
 239
 240 #define JAZZ16_RECORD_STEREO    0xAC    /* 16-bit record */
 241 #define JAZZ16_RECORD_MONO      0xA4    /* 16-bit record */
 242
 243 /*
 244  * These come from Jazz16 chipset documentation, which doesn't include
 245  * full register details, alas.  Their source code CD-ROM probably includes
 246  * details, but it has an NDA attached.
 247  */
 248 #define JAZZ16_DIR_PB           0x10
 249 #define JAZZ16_SINGLE_PB        0x14
 250 #define JAZZ16_SINGLE_ALAW_PB   0x17
 251 #define JAZZ16_CONT_PB          0x1C
 252 #define JAZZ16_CONT_ALAW_PB     0x1F
 253 #define JAZZ16_DIR_PCM_REC      0x20
 254 #define JAZZ16_SINGLE_REC       0x24
 255 #define JAZZ16_SINGLE_ALAW_REC  0x27
 256 #define JAZZ16_CONT_REC         0x2C
 257 #define JAZZ16_CONT_ALAW_REC    0x2F
 258 #define JAZZ16_SINGLE_ADPCM_PB  0x74
 259 #define JAZZ16_SINGLE_MULAW_PB  0x77
 260 #define JAZZ16_CONT_ADPCM_PB    0x7C
 261 #define JAZZ16_SINGLE_ADPCM_REC 0x84
 262 #define JAZZ16_SINGLE_MULAW_REC 0x87
 263 #define JAZZ16_CONT_ADPCM_REC   0x8C
 264 #define JAZZ16_CONT_MULAW_REC   0x8F
 265 #define JAZZ16_CONT_PB_XX       0x90
 266 #define JAZZ16_SINGLE_PB_XX     0x91
 267 #define JAZZ16_SINGLE_REC_XX    0x98
 268 #define JAZZ16_CONT_REC_XX      0x99
 269
 270
 271 /*
 272  * The ADPCM encodings are differential, meaning each sample represents
 273  * a difference to add to a running sum.  The inital value is called the
 274  * reference, or reference byte.  Any of the ADPCM DMA transfers can specify
 275  * that the given transfer begins with a reference byte by or'ing
 276  * in the bit below.
 277  */
 278 #define SB_DSP_REFERENCE        1
 279
 280 /*
 281  * Macros to detect valid hardware configuration data.
 282  */
 283 #define SBP_IRQ_VALID(irq)  ((irq) == 5 || (irq) == 7 || (irq) == 9 || (irq) == 10 || (irq) == 15)
 284 #define SB_IRQ_VALID(irq)   ((irq) == 3 || (irq) == 5 || (irq) == 7 || (irq) == 9)
 285
 286 #define SB16_DRQ_VALID(chan) ((chan) == 0 || (chan) == 1 || (chan) == 3 || \
 287                               (chan) == 5 || (chan) == 6 || (chan) == 7)
 288 #define SBP_DRQ_VALID(chan) ((chan) == 0 || (chan) == 1 || (chan) == 3)
 289 #define SB_DRQ_VALID(chan)  ((chan) == 1)
 290
 291 #define SB_BASE_VALID(base) ((base) == 0x220 || (base) == 0x240 || (base) == 0x260)
 292
 293 #define SB_INPUT_RATE   0
 294 #define SB_OUTPUT_RATE  1
 295