sys/dev/marvell/gtintrreg.h

   1 /*      $NetBSD: gtintrreg.h,v 1.1.2.4 2005/03/04 16:43:40 skrll Exp $  */
   2
   3 /*
   4  * Copyright (c) 2002 Allegro Networks, Inc., Wasabi Systems, Inc.
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  * 3. All advertising materials mentioning features or use of this software
  16  *    must display the following acknowledgement:
  17  *      This product includes software developed for the NetBSD Project by
  18  *      Allegro Networks, Inc., and Wasabi Systems, Inc.
  19  * 4. The name of Allegro Networks, Inc. may not be used to endorse
  20  *    or promote products derived from this software without specific prior
  21  *    written permission.
  22  * 5. The name of Wasabi Systems, Inc. may not be used to endorse
  23  *    or promote products derived from this software without specific prior
  24  *    written permission.
  25  *
  26  * THIS SOFTWARE IS PROVIDED BY ALLEGRO NETWORKS, INC. AND
  27  * WASABI SYSTEMS, INC. ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
  28  * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
  29  * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  30  * IN NO EVENT SHALL EITHER ALLEGRO NETWORKS, INC. OR WASABI SYSTEMS, INC.
  31  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  32  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  33  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  34  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  35  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  36  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  37  * POSSIBILITY OF SUCH DAMAGE.
  38  */
  39
  40 /*
  41  * gt64260intr.h: defines for GT-64260 system controller interrupts
  42  *
  43  * creation     Sun Jan  7 18:05:59 PST 2001    cliff
  44  *
  45  * NOTE:
  46  *      Galileo GT-64260 manual bit defines assume Little Endian
  47  *      ordering of bits within bytes, i.e.
  48  *              bit #0 --> 0x01
  49  *      vs. Motorola Big Endian bit numbering where
  50  *              bit #0 --> 0x80
  51  *      Consequently we define bits in Little Endian format and plan
  52  *      to swizzle bytes during programmed I/O by using lwbrx/swbrx
  53  *      to load/store GT-64260 registers.
  54  */
  55
  56
  57 #ifndef _DISCOVERY_GT64260INTR_H
  58 #define _DISCOVERY_GT64260INTR_H
  59
  60 #define BIT(n)  (1<<(n))
  61
  62
  63 /*
  64  * GT-64260 Interrupt Controller Register Map
  65  */
  66 #define ICR_MIC_LO      0xc18   /* main interrupt cause low */
  67 #define ICR_MIC_HI      0xc68   /* main interrupt cause high */
  68 #define ICR_CIM_LO      0xc1c   /* CPU interrupt mask low */
  69 #define ICR_CIM_HI      0xc6c   /* CPU interrupt mask high */
  70 #define ICR_CSC         0xc70   /* CPU select cause */
  71 #define ICR_P0IM_LO     0xc24   /* PCI_0 interrupt mask low */
  72 #define ICR_P0IM_HI     0xc64   /* PCI_0 interrupt mask high */
  73 #define ICR_P0SC        0xc74   /* PCI_0 select cause */
  74 #define ICR_P1IM_LO     0xca4   /* PCI_1 interrupt mask low */
  75 #define ICR_P1IM_HI     0xce4   /* PCI_1 interrupt mask high */
  76 #define ICR_P1SC        0xcf4   /* PCI_1 select cause */
  77 #define ICR_CI0M        0xe60   /* CPU int[0] mask */
  78 #define ICR_CI1M        0xe64   /* CPU int[1] mask */
  79 #define ICR_CI2M        0xe68   /* CPU int[2] mask */
  80 #define ICR_CI3M        0xe6c   /* CPU int[3] mask */
  81
  82 /*
  83  * IRQs:
  84  * we define IRQs based on bit number in the
  85  * ICU_LEN dimensioned hardware portion of the imask_t bit vector
  86  * which consists of 64 bits of Main Cause and Mask register pairs
  87  * (ICR_MIC_LO, ICR_MIC_HI and ICR_CIM_LO, ICR_CIM_HI)
  88  * as well as 32 bits in GPP registers (see intr.h):
  89  *
  90  *      IRQs:
  91  *      31.............................0  63.............................32
  92  *                                     |   |                             |
  93  *      imask_t index:                 |   |                             |
  94  *      |                              |   |                             |
  95  *      ^--------- IM_PIC_LO ----------^   ^------ IM_PIC_HI ------------^
  96  *                                     |   |                             |
  97  *      Bitmasks:                      |   |                             |
  98  *      |                              |   |                             |
  99  *      ^--------- IML_* --------------^   ^------ IMH_* ----------------^
 100  *                                     |   |                             |
 101  *      Registers:                     |   |                             |
 102  *      |                              |   |                             |
 103  *      ^--------- ICR_MIC_LO ---------^   ^------ ICR_MIC_HI -----------^
 104  *      ^--------- ICR_CIM_LO ---------^   ^------ ICR_CIM_HI -----------^
 105  *
 106  *      IRQs:
 107  *      95............................64  127............................96
 108  *                                     |   |                             |
 109  *      imask_t index:                 |   |                             |
 110  *      |                              |   |                             |
 111  *      ^-------- IMASK_GPP  ----------^   ^-----  IMASK_SOFTINT --------^
 112  *                                     |   |                             |
 113  *      Bitmasks:                      |   |                             |
 114  *      |                              |   |                             |
 115  *      ^--------- GPP_* --------------^   ^------ SIBIT(irq) -----------^
 116  *                                     |   |                             |
 117  *      Registers:                     |   |                             |
 118  *      |                              |   |                             |
 119  *      ^--- GT_GPP_Interrupt_Cause ---^   ^-------  (none)   -----------^
 120  *      ^--- GT_GPP_Interrupt_Mask  ---^
 121  *
 122  *
 123  * Note that GPP interrupts are summarized in the Main Cause Register.
 124  *
 125  * Some IRQs are "resvered" undefined due to gaps in HW register utilization.
 126  */
 127 #define IRQ_DEV         1       /* device interface interrupt */
 128 #define IRQ_DMA         2       /* DMA addres error interrupt */
 129 #define IRQ_CPU         3       /* CPU interface interrupt */
 130 #define IRQ_IDMA0_1     4       /* IDMA ch. 0..1 complete interrupt */
 131 #define IRQ_IDMA2_3     5       /* IDMA ch. 2..3 complete interrupt */
 132 #define IRQ_IDMA4_5     6       /* IDMA ch. 4..5 complete interrupt */
 133 #define IRQ_IDMA6_7     7       /* IDMA ch. 6..7 complete interrupt */
 134 #define IRQ_TIME0_1     8       /* Timer 0..1 interrupt */
 135 #define IRQ_TIME2_3     9       /* Timer 2..3 interrupt */
 136 #define IRQ_TIME4_5     10      /* Timer 4..5 interrupt */
 137 #define IRQ_TIME6_7     11      /* Timer 6..7 interrupt */
 138 #define IRQ_PCI0_0      12      /* PCI 0 interrupt 0 summary */
 139 #define IRQ_PCI0_1      13      /* PCI 0 interrupt 1 summary */
 140 #define IRQ_PCI0_2      14      /* PCI 0 interrupt 2 summary */
 141 #define IRQ_PCI0_3      15      /* PCI 0 interrupt 3 summary */
 142 #define IRQ_PCI1_0      16      /* PCI 1 interrupt 0 summary */
 143 #define IRQ_ECC         17      /* ECC error interrupt */
 144 #define IRQ_PCI1_1      18      /* PCI 1 interrupt 1 summary */
 145 #define IRQ_PCI1_2      19      /* PCI 1 interrupt 2 summary */
 146 #define IRQ_PCI1_3      20      /* PCI 1 interrupt 3 summary */
 147 #define IRQ_PCI0OUT_LO  21      /* PCI 0 outbound interrupt summary */
 148 #define IRQ_PCI0OUT_HI  22      /* PCI 0 outbound interrupt summary */
 149 #define IRQ_PCI1OUT_LO  23      /* PCI 1 outbound interrupt summary */
 150 #define IRQ_PCI1OUT_HI  24      /* PCI 1 outbound interrupt summary */
 151 #define IRQ_PCI0IN_LO   26      /* PCI 0 inbound interrupt summary */
 152 #define IRQ_PCI0IN_HI   27      /* PCI 0 inbound interrupt summary */
 153 #define IRQ_PCI1IN_LO   28      /* PCI 1 inbound interrupt summary */
 154 #define IRQ_PCI1IN_HI   29      /* PCI 1 inbound interrupt summary */
 155 #define IRQ_ETH0        (32+0)  /* Ethernet controller 0 interrupt */
 156 #define IRQ_ETH1        (32+1)  /* Ethernet controller 1 interrupt */
 157 #define IRQ_ETH2        (32+2)  /* Ethernet controller 2 interrupt */
 158 #define IRQ_SDMA        (32+4)  /* SDMA interrupt */
 159 #define IRQ_I2C         (32+5)  /* I2C interrupt */
 160 #define IRQ_BRG         (32+7)  /* Baud Rate Generator interrupt */
 161 #define IRQ_MPSC0       (32+8)  /* MPSC 0 interrupt */
 162 #define IRQ_MPSC1       (32+10) /* MPSC 1 interrupt */
 163 #define IRQ_COMM        (32+11) /* Comm unit interrupt */
 164 #define IRQ_GPP7_0      (32+24) /* GPP[7..0] interrupt */
 165 #define IRQ_GPP15_8     (32+25) /* GPP[15..8] interrupt */
 166 #define IRQ_GPP23_16    (32+26) /* GPP[23..16] interrupt */
 167 #define IRQ_GPP31_24    (32+27) /* GPP[31..24] interrupt */
 168
 169 /*
 170  * low word interrupt mask register bits
 171  */
 172 #define IML_SUM         BIT(0)
 173 #define IML_DEV         BIT(IRQ_DEV)
 174 #define IML_DMA         BIT(IRQ_DMA)
 175 #define IML_CPU         BIT(IRQ_CPU)
 176 #define IML_IDMA0_1     BIT(IRQ_IDMA0_1)
 177 #define IML_IDMA2_3     BIT(IRQ_IDMA2_3)
 178 #define IML_IDMA4_5     BIT(IRQ_IDMA4_5)
 179 #define IML_IDMA6_7     BIT(IRQ_IDMA6_7)
 180 #define IML_TIME0_1     BIT(IRQ_TIME0_1)
 181 #define IML_TIME2_3     BIT(IRQ_TIME2_3)
 182 #define IML_TIME4_5     BIT(IRQ_TIME4_5)
 183 #define IML_TIME6_7     BIT(IRQ_TIME6_7)
 184 #define IML_PCI0_0      BIT(IRQ_PCI0_0)
 185 #define IML_PCI0_1      BIT(IRQ_PCI0_1)
 186 #define IML_PCI0_2      BIT(IRQ_PCI0_2)
 187 #define IML_PCI0_3      BIT(IRQ_PCI0_3)
 188 #define IML_PCI1_0      BIT(IRQ_PCI1_0)
 189 #define IML_ECC         BIT(IRQ_ECC)
 190 #define IML_PCI1_1      BIT(IRQ_PCI1_1)
 191 #define IML_PCI1_2      BIT(IRQ_PCI1_2)
 192 #define IML_PCI1_3      BIT(IRQ_PCI1_3)
 193 #define IML_PCI0OUT_LO  BIT(IRQ_PCI0OUT_LO)
 194 #define IML_PCI0OUT_HI  BIT(IRQ_PCI0OUT_HI)
 195 #define IML_PCI1OUT_LO  BIT(IRQ_PCI1OUT_LO)
 196 #define IML_PCI1OUT_HI  BIT(IRQ_PCI1OUT_HI)
 197 #define IML_PCI0IN_LO   BIT(IRQ_PCI0IN_LO)
 198 #define IML_PCI0IN_HI   BIT(IRQ_PCI0IN_HI)
 199 #define IML_PCI1IN_LO   BIT(IRQ_PCI1IN_LO)
 200 #define IML_PCI1IN_HI   BIT(IRQ_PCI1IN_HI)
 201 #define IML_RES         (BIT(25)|BIT(30)|BIT(31))
 202
 203 /*
 204  * high word interrupt mask register bits
 205  */
 206 #define IMH_ETH0        BIT(IRQ_ETH0-32)
 207 #define IMH_ETH1        BIT(IRQ_ETH1-32)
 208 #define IMH_ETH2        BIT(IRQ_ETH2-32)
 209 #define IMH_SDMA        BIT(IRQ_SDMA-32)
 210 #define IMH_I2C         BIT(IRQ_I2C-32)
 211 #define IMH_BRG         BIT(IRQ_BRG-32)
 212 #define IMH_MPSC0       BIT(IRQ_MPSC0-32)
 213 #define IMH_MPSC1       BIT(IRQ_MPSC1-32)
 214 #define IMH_COMM        BIT(IRQ_COMM-32)
 215 #define IMH_GPP7_0      BIT(IRQ_GPP7_0-32)
 216 #define IMH_GPP15_8     BIT(IRQ_GPP15_8-32)
 217 #define IMH_GPP23_16    BIT(IRQ_GPP23_16-32)
 218 #define IMH_GPP31_24    BIT(IRQ_GPP31_24-32)
 219 #define IMH_GPP_SUM     (IMH_GPP7_0|IMH_GPP15_8|IMH_GPP23_16|IMH_GPP31_24)
 220 #define IMH_RES         (BIT(3) |BIT(6) |BIT(9) |BIT(12)|BIT(13)|BIT(14) \
 221                         |BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20) \
 222                         |BIT(21)|BIT(22)|BIT(23)|BIT(28)|BIT(29)|BIT(30) \
 223                         |BIT(31))
 224
 225 /*
 226  * ICR_CSC "Select Cause" register bits
 227  */
 228 #define CSC_SEL         BIT(30)         /* HI/LO select */
 229 #define CSC_STAT        BIT(31)         /* ? "irq active" : "irq none"  */
 230 #define CSC_CAUSE       ~(CSC_SEL|CSC_STAT)
 231
 232
 233 /*
 234  * CPU Int[n] Mask bit(s)
 235  */
 236 #define CPUINT_SEL      0x80000000      /* HI/LO select */
 237
 238 #endif  /*  _DISCOVERY_GT64260INTR_H */