sys/dev/marvell/gtmpscreg.h

   1 /*      $NetBSD: gtmpscreg.h,v 1.1.2.1 2005/03/04 16:43:40 skrll Exp $  */
   2
   3 /*
   4  * Copyright (c) 2002 Allegro Networks, Inc., Wasabi Systems, Inc.
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  * 3. All advertising materials mentioning features or use of this software
  16  *    must display the following acknowledgement:
  17  *      This product includes software developed for the NetBSD Project by
  18  *      Allegro Networks, Inc., and Wasabi Systems, Inc.
  19  * 4. The name of Allegro Networks, Inc. may not be used to endorse
  20  *    or promote products derived from this software without specific prior
  21  *    written permission.
  22  * 5. The name of Wasabi Systems, Inc. may not be used to endorse
  23  *    or promote products derived from this software without specific prior
  24  *    written permission.
  25  *
  26  * THIS SOFTWARE IS PROVIDED BY ALLEGRO NETWORKS, INC. AND
  27  * WASABI SYSTEMS, INC. ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
  28  * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
  29  * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  30  * IN NO EVENT SHALL EITHER ALLEGRO NETWORKS, INC. OR WASABI SYSTEMS, INC.
  31  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  32  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  33  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  34  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  35  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  36  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  37  * POSSIBILITY OF SUCH DAMAGE.
  38  */
  39
  40 /*
  41  * gtmpscreg.h - register defines for GT-64260 MPSC
  42  *
  43  * creation     Sun Apr  8 11:49:57 PDT 2001    cliff
  44  */
  45
  46 #ifndef _GTMPSCREG_H
  47 #define _GTMPSCREG_H
  48
  49 #ifndef BIT
  50 #define BIT(bitno)          (1U << (bitno))
  51 #endif
  52 #ifndef BITS
  53 #define BITS(hi, lo)        ((~((~0) << ((hi) + 1))) & ((~0) << (lo)))
  54 #endif
  55
  56 #define GTMPSC_NCHAN      2               /* Number of MPSC channels */
  57
  58 /*******************************************************************************
  59  *
  60  * MPSC register address offsets relative to the base mapping
  61  */
  62 #define GTMPSC_MRR      0xb400          /* MPSC Routing Register */
  63 #define GTMPSC_RCRR     0xb404          /* MPSC RX Clock Routing Register */
  64 #define GTMPSC_TCRR     0xb408          /* MPSC TX Clock Routing Register */
  65 #define GTMPSC_MMCR0_LO 0x8000          /* MPSC0 Main Config Register Lo */
  66 #define GTMPSC_MMCR0_HI 0x8004          /* MPSC0 Main Config Register Hi */
  67 #define GTMPSC_MPCR0    0x8008          /* MPSC0 Protocol Config Register */
  68 #define GTMPSC_CH0_BASE 0x8008          /* MPSC0 Channel Register base */
  69 #define GTMPSC_CHR0(n)  (MPSC_CH0_BASE + ((n) << 2))
  70 #define GTMPSC_MMCR1_LO 0x9000          /* MPSC1 Main Config Register Lo */
  71 #define GTMPSC_MMCR1_HI 0x9004          /* MPSC1 Main Config Register Hi */
  72 #define GTMPSC_MPCR1    0x9008          /* MPSC1 Protocol Config Register */
  73 #define GTMPSC_CH1R_BASE 0x9008         /* MPSC1 Channel Register base */
  74 #define GTMPSC_CHR1(n)  (GTMPSC_CH1_BASE + ((n) << 2))
  75
  76 #define GTMPSC_U_MMCR_LO(u)     (GTMPSC_MMCR0_LO + (((u) & 1) << 12))
  77 #define GTMPSC_U_MMCR_HI(u)     (GTMPSC_MMCR0_HI + (((u) & 1) << 12))
  78 #define GTMPSC_U_MPCR(u)        (GTMPSC_MPCR0 + (((u) & 1) << 12))
  79 #define GTMPSC_U_CHRN(u, n)     (GTMPSC_CH0_BASE + (((u) & 1) << 12) + ((n) << 2))
  80
  81 /*******************************************************************************
  82  *
  83  * MPSC register values & bit defines
  84  *
  85  *      values are provided for UART mode only
  86  */
  87 /*
  88  * MPSC Routing Register bits
  89  */
  90 #define GTMPSC_MRR_PORT0        0               /* serial port #0 */
  91 #define GTMPSC_MRR_NONE         7               /* unconnected */
  92                                                 /* all other "routes" resvd. */
  93 #define GTMPSC_MRR_MR0_MASK     BITS(2,0)       /* routing mask for MPSC0 */
  94 #define GTMPSC_MRR_RESa         BITS(5,3)
  95 #define GTMPSC_MRR_MR1_MASK     BITS(8,6)       /* routing mask for MPSC1 */
  96 #define GTMPSC_MRR_RESb         BITS(30,9)
  97 #define GTMPSC_MRRE_DSC         BIT(31)         /* "Don't Stop Clock" */
  98 #define GTMPSC_MRR_RES (GTMPSC_MRR_RESa|GTMPSC_MRR_RESb)
  99 /*
 100  * MPSC Clock Routing Register bits
 101  * the bitfields and route definitions are common for RCRR and TCRR
 102  * except for MPSC_TCRR_TSCLK0
 103  */
 104 #define GTMPSC_CRR_BRG0         0x0             /* Baud Rate Generator #0 */
 105 #define GTMPSC_CRR_BRG1         0x1             /* Baud Rate Generator #1 */
 106 #define GTMPSC_CRR_BRG2         0x2             /* Baud Rate Generator #2 */
 107 #define GTMPSC_CRR_SCLK0        0x8             /* SCLK0 */
 108 #define GTMPSC_TCRR_TSCLK0      0x9             /* TSCLK0 (for TCRR only) */
 109                                                 /* all other values resvd. */
 110 #define GTMPSC_CRR0_SHIFT       0
 111 #define GTMPSC_CRR0_MASK        BITS(3,0)       /* MPSC0 Clock Routing */
 112 #define GTMPSC_CRR_RESa         BITS(7,4)
 113 #define GTMPSC_CRR1_SHIFT       8
 114 #define GTMPSC_CRR1_MASK        BITS(11,8)      /* MPSC1 Clock Routing */
 115 #define GTMPSC_CRR_RESb         BITS(31,12)
 116 #define GTMPSC_CRR_RES (GTMPSC_CRR_RESa|GTMPSC_CRR_RESb)
 117 /*
 118  * MPSC Main Configuration Register LO bits
 119  */
 120 #define GTMPSC_MMCR_LO_MODE_MASK BITS(2,0)
 121 #define GTMPSC_MMCR_LO_MODE_UART (0x4 << 0)     /* UART mode */
 122 #define GTMPSC_MMCR_LO_TTX       BIT(3)         /* Transparent TX */
 123 #define GTMPSC_MMCR_LO_TRX       BIT(4)         /* Transparent RX */
 124 #define GTMPSC_MMCR_LO_RESa      BIT(5)
 125 #define GTMPSC_MMCR_LO_ET        BIT(6)         /* Enable TX */
 126 #define GTMPSC_MMCR_LO_ER        BIT(7)         /* Enable RX */
 127 #define GTMPSC_MMCR_LO_LPBK_MASK BITS(9,8)      /* Loop Back */
 128 #define GTMPSC_MMCR_LO_LPBK_NONE (0 << 8)       /* Normal (non-loop) */
 129 #define GTMPSC_MMCR_LO_LPBK_LOOP (1 << 8)       /* Loop Back */
 130 #define GTMPSC_MMCR_LO_LPBK_ECHO (2 << 8)       /* Echo */
 131 #define GTMPSC_MMCR_LO_LPBK_LBE (3 << 8)        /* Loop Back and Echo */
 132 #define GTMPSC_MMCR_LO_NLM      BIT(10)         /* Null Modem */
 133 #define GTMPSC_MMCR_LO_RESb     BIT(11)
 134 #define GTMPSC_MMCR_LO_TSYN     BIT(12)         /* Transmitter sync to Rcvr. */
 135 #define GTMPSC_MMCR_LO_RESc     BIT(13)
 136 #define GTMPSC_MMCR_LO_TSNS_MASK BITS(15,14)    /* Transmit Sense */
 137 #define GTMPSC_MMCR_LO_TSNS_INF (0 << 14)       /* Infinite */
 138 #define GTMPSC_MMCR_LO_TIDL     BIT(16)         /* TX Idles */
 139 #define GTMPSC_MMCR_LO_RTSM     BIT(17)         /* RTS Mode */
 140 #define GTMPSC_MMCR_LO_RESd     BIT(18)
 141 #define GTMPSC_MMCR_LO_CTSS     BIT(19)         /* CTS Sampling mode */
 142 #define GTMPSC_MMCR_LO_CDS      BIT(20)         /* CD Sampling mode */
 143 #define GTMPSC_MMCR_LO_CTSM     BIT(21)         /* CTS operating Mode */
 144 #define GTMPSC_MMCR_LO_CDM      BIT(22)         /* CD operating Mode */
 145 #define GTMPSC_MMCR_LO_CRCM_MASK BITS(25,23)    /* CRC Mode */
 146 #define GTMPSC_MMCR_LO_CRCM_NONE (0 << 23)      /* CRC Mode */
 147 #define GTMPSC_MMCR_LO_RESe     BITS(27,26)
 148 #define GTMPSC_MMCR_LO_TRVD     BIT(28)         /* Transmit Reverse Data */
 149 #define GTMPSC_MMCR_LO_RRVD     BIT(29)         /* Receive  Reverse Data */
 150 #define GTMPSC_MMCR_LO_RESf     BIT(30)
 151 #define GTMPSC_MMCR_LO_GDE      BIT(31)         /* Glitch Detect Enable */
 152 #define GTMPSC_MMCR_LO_RES \
 153                 (GTMPSC_MMCR_LO_RESa|GTMPSC_MMCR_LO_RESb|GTMPSC_MMCR_LO_RESc \
 154                 |GTMPSC_MMCR_LO_RESd|GTMPSC_MMCR_LO_RESe|GTMPSC_MMCR_LO_RESf)
 155 /*
 156  * MPSC Main Configuration Register HI bits
 157  */
 158 #define GTMPSC_MMCR_HI_TCI       BIT(0)         /* TX Clock Invert */
 159 #define GTMPSC_MMCR_HI_TINV      BIT(1)         /* TX Bitstream Inversion */
 160 #define GTMPSC_MMCR_HI_TPL       BITS(4,2)      /* TX Preable Length */
 161 #define GTMPSC_MMCR_HI_TPL_NONE  0              /* no TX Preable (default) */
 162 #define GTMPSC_MMCR_HI_TPL_16    (6 << 2)       /* 16 byte preamble */
 163 #define GTMPSC_MMCR_HI_TPPT_MASK BITS(8,5)      /* TX Preable Pattern */
 164 #define GTMPSC_MMCR_HI_TPPT_NONE (0 << 5)       /* TX Preable Pattern */
 165 #define GTMPSC_MMCR_HI_TCDV_MASK BITS(10,9)     /* TX Clock Divide */
 166 #define GTMPSC_MMCR_HI_TCDV_1X   (0 << 9)       /* 1x clock mode */
 167 #define GTMPSC_MMCR_HI_TCDV_8X   (1 << 9)       /* 8x clock mode */
 168 #define GTMPSC_MMCR_HI_TCDV_16X  (2 << 9)       /* 16x clock mode */
 169 #define GTMPSC_MMCR_HI_TCDV_32X  (3 << 9)       /* 32x clock mode */
 170 #define GTMPSC_MMCR_HI_TDEC_MASK BITS(13,11)    /* TX Encoder */
 171 #define GTMPSC_MMCR_HI_TDEC_NRZ  (0 << 9)       /* NRZ (default) */
 172 #define GTMPSC_MMCR_HI_TDEC_NRZI (1 << 9)       /* NRZI (mark) */
 173 #define GTMPSC_MMCR_HI_TDEC_FM0  (2 << 9)       /* FM0 */
 174 #define GTMPSC_MMCR_HI_TDEC_MAN  (4 << 9)       /* Manchester */
 175 #define GTMPSC_MMCR_HI_TDEC_DMAN (6 << 9)       /* Differential Manchester */
 176                                                 /* all other values rsvd. */
 177 #define GTMPSC_MMCR_HI_RESa     BITS(15,14)
 178 #define GTMPSC_MMCR_HI_RINV     BIT(16)         /* RX Bitstream Inversion */
 179 #define GTMPSC_MMCR_HI_GDW      BITS(20,17)     /* Clock Glitch Width */
 180 #define GTMPSC_MMCR_HI_RESb     BIT(21)
 181 #define GTMPSC_MMCR_HI_RDW      BIT(22)         /* Reveive Data Width */
 182 #define GTMPSC_MMCR_HI_RSYL_MASK  BITS(24,23)   /* Reveive Sync Width */
 183 #define GTMPSC_MMCR_HI_RSYL_EXT   (0 << 23)     /* External sync */
 184 #define GTMPSC_MMCR_HI_RSYL_4BIT  (1 << 23)     /* 4-bit sync */
 185 #define GTMPSC_MMCR_HI_RSYL_8BIT  (2 << 23)     /* 8-bit sync */
 186 #define GTMPSC_MMCR_HI_RSYL_16BIT (3 << 23)     /* 16-bit sync */
 187 #define GTMPSC_MMCR_HI_RCDV_MASK BITS(26,25)     /* Receive Clock Divider */
 188 #define GTMPSC_MMCR_HI_RCDV_1X   (0 << 25)       /* 1x clock mode (default) */
 189 #define GTMPSC_MMCR_HI_RCDV_8X   (1 << 25)       /* 8x clock mode (default) */
 190 #define GTMPSC_MMCR_HI_RCDV_16X  (2 << 25)       /* 16x clock mode (default) */
 191 #define GTMPSC_MMCR_HI_RCDV_32X  (3 << 25)       /* 16x clock mode (default) */
 192 #define GTMPSC_MMCR_HI_RENC_MASK BITS(29,27)    /* Receive Encoder */
 193 #define GTMPSC_MMCR_HI_RENC_NRZ (0 << 27)       /* NRZ (default) */
 194 #define GTMPSC_MMCR_HI_RENC_NRZI (1 << 27)      /* NRZI */
 195 #define GTMPSC_MMCR_HI_RENC_FM0 (2 << 27)       /* FM0 */
 196 #define GTMPSC_MMCR_HI_RENC_MAN (4 << 27)       /* Manchester */
 197 #define GTMPSC_MMCR_HI_RENC_DMAN (6 << 27)      /* Differential Manchester */
 198                                                 /* all other values rsvd. */
 199 #define GTMPSC_MMCR_HI_SEDG_MASK BITS(31,30)    /* Sync Clock Edge */
 200 #define GTMPSC_MMCR_HI_SEDG_BOTH (0 << 30)      /* rising and falling (dflt) */
 201 #define GTMPSC_MMCR_HI_SEDG_RISE (1 << 30)      /* rising edge */
 202 #define GTMPSC_MMCR_HI_SEDG_FALL (2 << 30)      /* falling edge */
 203 #define GTMPSC_MMCR_HI_SEDG_NONE (3 << 30)      /* no adjustment */
 204 /*
 205  * SDMAx Command/Status Register bits for UART Mode, RX
 206  *
 207  * XXX these belong in sdmareg.h ?
 208  */
 209 #define SDMA_CSR_RX_PE          BIT(0)          /* Parity Error */
 210 #define SDMA_CSR_RX_CDL         BIT(1)          /* Carrier Detect Loss */
 211 #define SDMA_CSR_RX_RESa        BIT(2)
 212 #define SDMA_CSR_RX_FR          BIT(3)          /* Framing Error */
 213 #define SDMA_CSR_RX_RESb        BITS(5,4)
 214 #define SDMA_CSR_RX_OR          BIT(6)          /* Data Overrun */
 215 #define SDMA_CSR_RX_RESc        BITS(8,7)
 216 #define SDMA_CSR_RX_BR          BIT(9)          /* Break Received */
 217 #define SDMA_CSR_RX_MI          BIT(10)         /* Max Idle */
 218 #define SDMA_CSR_RX_ADDR        BIT(11)         /* Address */
 219 #define SDMA_CSR_RX_AMATCH      BIT(12)         /* Address match */
 220 #define SDMA_CSR_RX_CT          BIT(13)         /* Transparency Control char */
 221 #define SDMA_CSR_RX_C           BIT(14)         /* Control char */
 222 #define SDMA_CSR_RX_ES          BIT(15)         /* Error Summary */
 223 #define SDMA_CSR_RX_L           BIT(16)         /* Last */
 224 #define SDMA_CSR_RX_F           BIT(17)         /* First */
 225 #define SDMA_CSR_RX_RESd        BITS(22,18)
 226 #define SDMA_CSR_RX_EI          BIT(23)         /* Enable Interrupt */
 227 #define SDMA_CSR_RX_RESe        BITS(29,24)
 228 #define SDMA_CSR_RX_AUTO        BIT(30)         /* Auto Mode */
 229 #define SDMA_CSR_RX_OWN         BIT(31)         /* Owner */
 230 #define SDMA_CSR_RX_RES (SDMA_CSR_RX_RESa|SDMA_CSR_RX_RESb|SDMA_CSR_RX_RESc \
 231                          |SDMA_CSR_RX_RESd|SDMA_CSR_RX_RESe)
 232 /*
 233  * SDMAx Command/Status Register bits for UART Mode, TX
 234  */
 235 #define SDMA_CSR_TX_RESa        BIT(0)
 236 #define SDMA_CSR_TX_CTSL        BIT(1)          /* CTS Loss */
 237 #define SDMA_CSR_TX_RESb        BITS(14,2)
 238 #define SDMA_CSR_TX_ES          BIT(15)         /* Error Summary */
 239 #define SDMA_CSR_TX_L           BIT(16)         /* Last */
 240 #define SDMA_CSR_TX_F           BIT(17)         /* First */
 241 #define SDMA_CSR_TX_P           BIT(18)         /* Preamble */
 242 #define SDMA_CSR_TX_ADDR        BIT(19)         /* Address */
 243 #define SDMA_CSR_TX_NS          BIT(20)         /* No Stop Bit */
 244 #define SDMA_CSR_TX_RESc        BITS(22,21)
 245 #define SDMA_CSR_TX_EI          BIT(23)         /* Enable Interrupt */
 246 #define SDMA_CSR_TX_RESd        BITS(29,24)
 247 #define SDMA_CSR_TX_AUTO        BIT(30)         /* Auto Mode */
 248 #define SDMA_CSR_TX_OWN         BIT(31)         /* Owner */
 249 #define SDMA_CSR_TX_RES \
 250         (SDMA_CSR_TX_RESa|SDMA_CSR_TX_RESb|SDMA_CSR_TX_RESc|SDMA_CSR_TX_RESd)
 251 /*
 252  * MPSCx Protocol Configuration Register for UART Mode
 253  */
 254 #define GTMPSC_MPCR_RESa        BITS(5,0)
 255 #define GTMPSC_MPCR_DRT         BIT(6)          /* Disable Rx on Tx */
 256 #define GTMPSC_MPCR_ISO         BIT(7)          /* Isochronous Mode */
 257 #define GTMPSC_MPCR_RZS         BIT(8)          /* Rx Zero Stop Bit(s) */
 258 #define GTMPSC_MPCR_FRZ         BIT(9)          /* Freeze Tx */
 259 #define GTMPSC_MPCR_UM_MASK     BITS(11,10)     /* UART Mode mask */
 260 #define GTMPSC_MPCR_UM_NORM     (0 << 10)       /* Normal UART Mode */
 261 #define GTMPSC_MPCR_UM_MDROP    (1 << 10)       /* Multi-Drop UART Mode */
 262                                                 /* other values are resvd. */
 263 #define GTMPSC_MPCR_CLMASK      BITS(13,12)     /* Character Length mask */
 264 #define GTMPSC_MPCR_CL_5        (0 << 12)       /* 5 data bits */
 265 #define GTMPSC_MPCR_CL_6        (1 << 12)       /* 6 data bits */
 266 #define GTMPSC_MPCR_CL_7        (2 << 12)       /* 7 data bits */
 267 #define GTMPSC_MPCR_CL_8        (3 << 12)       /* 8 data bits */
 268 #define GTMPSC_MPCR_SBL_1       0x0             /* 1 stop bit */
 269 #define GTMPSC_MPCR_SBL_2       BIT(14)         /* 2 stop bits */
 270 #define GTMPSC_MPCR_FLC_NORM    0x0             /* Normal Flow Ctl mode */
 271 #define GTMPSC_MPCR_FLC_ASYNC   BIT(15)         /* Asynchronous Flow Ctl mode */
 272 #define GTMPSC_MPCR_RESb        BITS(31,16)
 273 #define GTMPSC_MPCR_RES (GTMPSC_MPCR_RESa|GTMPSC_MPCR_RESb)
 274 /*
 275  * MPSC Channel Register 1 for UART Mode "Break/Stuff"
 276  */
 277 #define GTMPSC_CHR1_TCS         BITS(7,0)       /* Constrol Stuff Character */
 278 #define GTMPSC_CHR1_BRK         BITS(23,16)     /* Break Count */
 279 #define GTMPSC_CHR1_RES         BITS(15,8)|BITS(31,24)
 280 /*
 281  * MPSC Channel Register 2 for UART Mode "Command"
 282  */
 283 #define GTMPSC_CHR2_RESa        BIT(0)
 284 #define GTMPSC_CHR2_TEV         BIT(1)          /* Tx Enb. Vert. Redundancy  */
 285 #define GTMPSC_CHR2_TPM_MASK    BITS(3,2)       /* Tx Parity Mode mask */
 286 #define GTMPSC_CHR2_TPM_ODD     (0 << 2)        /* Odd Tx Parity */
 287 #define GTMPSC_CHR2_TPM_LOW     (1 << 2)        /* Low (always 0) Tx Parity */
 288 #define GTMPSC_CHR2_TPM_EVEN    (2 << 2)        /* Even Tx Parity */
 289 #define GTMPSC_CHR2_TPM_HIGH    (3 << 2)        /* High (always 1) Tx Parity */
 290 #define GTMPSC_CHR2_RESb        BITS(6,4)
 291 #define GTMPSC_CHR2_TXABORT     BIT(7)          /* Tx Abort */
 292 #define GTMPSC_CHR2_RESc        BIT(8)
 293 #define GTMPSC_CHR2_TCS         BIT(9)          /* Tx TCS Char */
 294 #define GTMPSC_CHR2_RESd        BITS(16,10)
 295 #define GTMPSC_CHR2_REC         BIT(17)         /* Rx Enb. Vert. Redundancy */
 296 #define GTMPSC_CHR2_RPM_MASK    BITS(19,18)     /* Rx Parity Mode mask */
 297 #define GTMPSC_CHR2_RPM_ODD     (0 << 18)       /* Odd Rx Parity */
 298 #define GTMPSC_CHR2_RPM_LOW     (1 << 18)       /* Low (always 0) Rx Parity */
 299 #define GTMPSC_CHR2_RPM_EVEN    (2 << 18)       /* Even Rx Parity */
 300 #define GTMPSC_CHR2_RPM_HIGH    (3 << 18)       /* High (always 1) Rx Parity */
 301 #define GTMPSC_CHR2_RESe        BITS(22,20)
 302 #define GTMPSC_CHR2_RXABORT     BIT(23)         /* Rx Abort */
 303 #define GTMPSC_CHR2_RESf        BIT(24)
 304 #define GTMPSC_CHR2_CRD         BIT(25)         /* Close RX Descriptor */
 305 #define GTMPSC_CHR2_RESg        BITS(30,26)
 306 #define GTMPSC_CHR2_EH          BIT(31)         /* Enter Hunt */
 307 #define GTMPSC_CHR2_RES \
 308                 (GTMPSC_CHR2_RESa|GTMPSC_CHR2_RESb|GTMPSC_CHR2_RESc| \
 309                  GTMPSC_CHR2_RESd|GTMPSC_CHR2_RESe|GTMPSC_CHR2_RESf| \
 310                  GTMPSC_CHR2_RESg)
 311 /*
 312  * MPSC Channel Register 3 for UART Mode "Max Idle"
 313  */
 314 #define GTMPSC_CHR3_MIR         BITS(15,0)      /* Max Idle Char count */
 315 #define GTMPSC_CHR3_RES         BITS(31,16)
 316 /*
 317  * MPSC Channel Register 4 for UART Mode "Control Filtering"
 318  */
 319 #define GTMPSC_CHR4_CFR         BITS(7,0)       /* Control bit compare enable */
 320 #define GTMPSC_CHR4_RES         BITS(31,8)
 321 /*
 322  * MPSC Channel Registers 5..8 for UART Mode "UART Control Character"
 323  *
 324  * NOTE: two 16 bit CHRCC fields exist in each of Channel Registers 5..8
 325  */
 326 #define GTMPSC_CHRCC_SHIFT      16
 327 #define GTMPSC_CHRCC_CHAR       BITS(7,0)       /* the control character */
 328 #define GTMPSC_CHRCC_RES        BITS(11,8)
 329 #define GTMPSC_CHRCC_INT        BIT(12)         /* Interrupt */
 330 #define GTMPSC_CHRCC_CO         BIT(13)         /* ISO 3309 Control Octet */
 331 #define GTMPSC_CHRCC_R          BIT(14)         /* Reject */
 332 #define GTMPSC_CHRCC_V          BIT(15)         /* Valid */
 333 /*
 334  * MPSC Channel Register 9 for UART Mode "Address" (for multidrop operation)
 335  */
 336 #define GTMPSC_CHR9_AD1         BITS(7,0)       /* address #1 */
 337 #define GTMPSC_CHR9_RESa        BITS(14,8)
 338 #define GTMPSC_CHR9_MODE1       BIT(15)         /* mode #1 */
 339 #define GTMPSC_CHR9_AD2         BITS(23,16)     /* address #2 */
 340 #define GTMPSC_CHR9_RESb        BITS(30,24)
 341 #define GTMPSC_CHR9_MODE2       BIT(31)         /* mode #2 */
 342 #define GTMPSC_CHR9_RES (GTMPSC_CHR9_RESa|GTMPSC_CHR9_RESb)
 343 /*
 344  * MPSC Channel Register 10 for UART Mode "Event Status"
 345  */
 346 #define GTMPSC_CHR10_CTS        BIT(0)          /* Clear To Send */
 347 #define GTMPSC_CHR10_CD         BIT(1)          /* Carrier Detect */
 348 #define GTMPSC_CHR10_RESa       BIT(2)
 349 #define GTMPSC_CHR10_TIDLE      BIT(3)          /* Tx in Idle State */
 350 #define GTMPSC_CHR10_RESb       BIT(4)
 351 #define GTMPSC_CHR10_RHS        BIT(5)          /* Rx in HUNT State */
 352 #define GTMPSC_CHR10_RESc       BIT(6)
 353 #define GTMPSC_CHR10_RLS        BIT(7)          /* Rx Line STatus */
 354 #define GTMPSC_CHR10_RESd       BITS(10,8)
 355 #define GTMPSC_CHR10_RLIDL      BIT(11)         /* Rx IDLE Line */
 356 #define GTMPSC_CHR10_RESe       BITS(15,12)
 357 #define GTMPSC_CHR10_RCRn       BITS(23,16)     /* Received Control Char # */
 358 #define GTMPSC_CHR10_RESf       BITS(31,24)
 359 #define GTMPSC_CHR10_RES \
 360                 (GTMPSC_CHR10_RESa|GTMPSC_CHR10_RESb|GTMPSC_CHR10_RESc \
 361                 |GTMPSC_CHR10_RESd|GTMPSC_CHR10_RESe|GTMPSC_CHR10_RESf)
 362
 363
 364 #endif  /* _GTMPSCREG_H */