sys/dev/marvell/gtsdmareg.h

   1 /*      $NetBSD: gtsdmareg.h,v 1.1.2.4 2005/03/04 16:43:40 skrll Exp $  */
   2
   3 /*
   4  * Copyright (c) 2002 Allegro Networks, Inc., Wasabi Systems, Inc.
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  * 3. All advertising materials mentioning features or use of this software
  16  *    must display the following acknowledgement:
  17  *      This product includes software developed for the NetBSD Project by
  18  *      Allegro Networks, Inc., and Wasabi Systems, Inc.
  19  * 4. The name of Allegro Networks, Inc. may not be used to endorse
  20  *    or promote products derived from this software without specific prior
  21  *    written permission.
  22  * 5. The name of Wasabi Systems, Inc. may not be used to endorse
  23  *    or promote products derived from this software without specific prior
  24  *    written permission.
  25  *
  26  * THIS SOFTWARE IS PROVIDED BY ALLEGRO NETWORKS, INC. AND
  27  * WASABI SYSTEMS, INC. ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
  28  * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
  29  * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  30  * IN NO EVENT SHALL EITHER ALLEGRO NETWORKS, INC. OR WASABI SYSTEMS, INC.
  31  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  32  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  33  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  34  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  35  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  36  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  37  * POSSIBILITY OF SUCH DAMAGE.
  38  */
  39
  40 /*
  41  * gtsdmareg.h - register defines for GT-64260 SDMA
  42  *
  43  * creation     Sun Apr  8 20:22:51 PDT 2001    cliff
  44  */
  45
  46 #ifndef _GTSDMAREG_H
  47 #define _GTSDMAREG_H
  48
  49 #ifndef BIT
  50 #define BIT(bitno)          (1U << (bitno))
  51 #endif
  52 #ifndef BITS
  53 #define BITS(hi, lo)        ((~((~0) << ((hi) + 1))) & ((~0) << (lo)))
  54 #endif
  55
  56 /*******************************************************************************
  57  *
  58  * SDMA register address offsets relative to the base mapping
  59  */
  60 #define SDMA_SDC0       0x4000          /* SDMA #0 Configuration Register */
  61 #define SDMA_SDCM0      0x4008          /* SDMA #0 Command Register */
  62 #define SDMA_SCRDP0     0x4810          /* SDMA #0 Current RX Desc. Pointer */
  63 #define SDMA_SCTDP0     0x4c10          /* SDMA #0 Current TX Desc. Pointer */
  64 #define SDMA_SFTDP0     0x4c14          /* SDMA #0 First   TX Desc. Pointer */
  65 #define SDMA_SDC1       0x6000          /* SDMA #1 Configuration Register */
  66 #define SDMA_SDCM1      0x6008          /* SDMA #1 Command Register */
  67 #define SDMA_SCRDP1     0x6810          /* SDMA #1 Current RX Desc. Pointer */
  68 #define SDMA_SCTDP1     0x6c10          /* SDMA #1 Current TX Desc. Pointer */
  69 #define SDMA_SFTDP1     0x6c14          /* SDMA #1 First   TX Desc. Pointer */
  70 #define SDMA_ICAUSE     0xb800          /* Interrupt Cause Register */
  71 #define SDMA_IMASK      0xb880          /* Interrupt Mask Register */
  72
  73 #define SDMA_U_SDC(u)   (SDMA_SDC0 + (((u) & 1) << 13))
  74 #define SDMA_U_SDCM(u)  (SDMA_SDCM0 + (((u) & 1) << 13))
  75 #define SDMA_U_SCRDP(u) (SDMA_SCRDP0 + (((u) & 1) << 13))
  76 #define SDMA_U_SCTDP(u) (SDMA_SCTDP0 + (((u) & 1) << 13))
  77 #define SDMA_U_SFTDP(u) (SDMA_SFTDP0 + (((u) & 1) << 13))
  78
  79 /*******************************************************************************
  80  *
  81  * SDMA register values and bit definitions
  82  */
  83 /*
  84  * SDMA Configuration Register
  85  */
  86 #define SDMA_SDC_RFT            BIT(0)          /* RX FIFO Threshold */
  87 #define SDMA_SDC_SFM            BIT(1)          /* Single Frame Mode */
  88 #define SDMA_SDC_RC_MASK        BITS(5,2)       /* Re-TX  count */
  89 #define SDMA_SDC_RC_SHIFT       2
  90 #define SDMA_SDC_BLMR           BIT(6)          /* RX Big=0 Lil=1 Endian mode */
  91 #define SDMA_SDC_BLMT           BIT(7)          /* TX Big=0 Lil=1 Endian mode */
  92 #define SDMA_SDC_POVR           BIT(8)          /* PCI Override */
  93 #define SDMA_SDC_RIFB           BIT(9)          /* RX Intr on Frame boundaries */
  94 #define SDMA_SDC_RESa           BITS(11,10)
  95 #define SDMA_SDC_BSZ_MASK       BITS(13,12)     /* Maximum Burst Size */
  96 #define SDMA_SDC_BSZ_1x64       (0 << 12)       /* 1 64 bit word */
  97 #define SDMA_SDC_BSZ_2x64       (1 << 12)       /* 2 64 bit words */
  98 #define SDMA_SDC_BSZ_4x64       (2 << 12)       /* 4 64 bit words */
  99 #define SDMA_SDC_BSZ_8x64       (3 << 12)       /* 8 64 bit words */
 100 #define SDMA_SDC_RESb           BITS(31,14)
 101 #define SDMA_SDC_RES (SDMA_SDC_RESa|SDMA_SDC_RESb)
 102 /*
 103  * SDMA Command Register
 104  */
 105 #define SDMA_SDCM_RESa          BITS(6,0)
 106 #define SDMA_SDCM_ERD           BIT(7)          /* Enable RX DMA */
 107 #define SDMA_SDCM_RESb          BITS(14,8)
 108 #define SDMA_SDCM_AR            BIT(15)         /* Abort Receive */
 109 #define SDMA_SDCM_STD           BIT(16)         /* Stop TX */
 110 #define SDMA_SDCM_RESc          BITS(22,17)
 111 #define SDMA_SDCM_TXD           BIT(23)         /* TX Demand */
 112 #define SDMA_SDCM_RESd          BITS(30,24)
 113 #define SDMA_SDCM_AT            BIT(31)         /* Abort TX */
 114 #define SDMA_SDCM_RES \
 115                 (SDMA_SDCM_RESa|SDMA_SDCM_RESb|SDMA_SDCM_RESc|SDMA_SDCM_RESd)
 116 /*
 117  * SDMA Interrupt Cause and Mask Register bits
 118  */
 119 #define U__(bits,u)             ((bits) << (((u) % 2) * 8))
 120 #define SDMA_INTR_RXBUF(u)      U__(BIT(0),u)   /* SDMA #0 Rx Buffer Return */
 121 #define SDMA_INTR_RXERR(u)      U__(BIT(1),u)   /* SDMA #0 Rx Error */
 122 #define SDMA_INTR_TXBUF(u)      U__(BIT(2),u)   /* SDMA #0 Tx Buffer Return */
 123 #define SDMA_INTR_TXEND(u)      U__(BIT(3),u)   /* SDMA #0 Tx End */
 124 #define SDMA_INTR_RESa          BITS(7,4)
 125 #define SDMA_INTR_RESb          BITS(31,12)
 126 #define SDMA_INTR_RES           (SDMA_INTR_RESa|SDMA_INTR_RESb)
 127 #define SDMA_U_INTR_MASK(u)     U__(BITS(3,0),u)
 128
 129
 130 /*******************************************************************************
 131  *
 132  * SDMA descriptor structure and definitions
 133  */
 134 /*
 135  * SDMA descriptor structure used for both TX and RX
 136  * the `sdma_csr' and `sdma_cnt' fields differ for RX and TX
 137  * `sdma_csr' varies depending on how it is tasked;
 138  * see "gtmpscreg.h" for defines on SDMA descriptor CSR values
 139  * for MPSC UART mode.  Note that pointer fields are physical addrs.
 140  */
 141 typedef struct sdma_desc {
 142         u_int32_t sdma_cnt;             /* size (rx) or shadow (tx) and count */
 143         u_int32_t sdma_csr;             /* command/status */
 144         u_int32_t sdma_next;            /* next descriptor link */
 145         u_int32_t sdma_bufp;            /* buffer pointer */
 146 } sdma_desc_t;
 147
 148 #define SDMA_RX_CNT_BCNT_SHIFT          0               /* byte count */
 149 #define SDMA_RX_CNT_BCNT_MASK           BITS(15,0)      /*  "    "    */
 150 #define SDMA_RX_CNT_BUFSZ_SHIFT         16              /* buffer size */
 151 #define SDMA_RX_CNT_BUFSZNT_SIZE_MASK   BITS(31,19)     /*  "      "   */
 152 #define SDMA_RX_CNT_BUFP_MASK           BITS(31,3)      /* buffer pointer */
 153 #define SDMA_RX_CNT_NEXT_MASK           BITS(31,4)      /* next desc. pointer */
 154
 155 #define SDMA_TX_CNT_SBC_SHIFT           0               /* shadow byte count */
 156 #define SDMA_TX_CNT_SBC_MASK            BITS(15,0)      /*  "      "    "    */
 157 #define SDMA_TX_CNT_BCNT_SHIFT          16              /* byte count */
 158 #define SDMA_TX_CNT_BCNT_MASK           BITS(31,16      /*  "    "    */
 159 #define SDMA_TX_CNT_NEXT_MASK           BITS(31,4)      /* next desc. pointer */
 160
 161
 162 #endif  /* _GTSDMAREG_H */