sys/dev/mca/edcreg.h

   1 /*      $NetBSD: edcreg.h,v 1.4 2005/12/11 12:22:18 christos Exp $      */
   2
   3 /*
   4  * Copyright (c) 2001 The NetBSD Foundation, Inc.
   5  * All rights reserved.
   6  *
   7  * This code is derived from software contributed to The NetBSD Foundation
   8  * by Jaromir Dolecek.
   9  *
  10  * Redistribution and use in source and binary forms, with or without
  11  * modification, are permitted provided that the following conditions
  12  * are met:
  13  * 1. Redistributions of source code must retain the above copyright
  14  *    notice, this list of conditions and the following disclaimer.
  15  * 2. Redistributions in binary form must reproduce the above copyright
  16  *    notice, this list of conditions and the following disclaimer in the
  17  *    documentation and/or other materials provided with the distribution.
  18  *
  19  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
  20  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  21  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  22  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
  23  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  29  * POSSIBILITY OF SUCH DAMAGE.
  30  */
  31
  32 /*
  33  * Driver for MCA ESDI controllers and disks.
  34  */
  35
  36 #define ESDIC_IOPRM             0x3510
  37 #define ESDIC_IOALT             0x3518
  38 #define ESDIC_REG_NPORTS        8
  39 #define ESDIC_IRQ               14              /* this is fixed */
  40
  41 /* pos2 */
  42 #define IO_IS_ALT               0x02
  43 #define DRQ_MASK                0x3c
  44 #define FAIRNESS_ENABLE         0x40
  45
  46 /* pos3 */
  47 #define PACING_INT_MASK         0x30
  48
  49 /* pos4 */
  50 #define PACING_CTRL_DISABLE     0x01
  51 #define RELEASE_2               0x02    /* lower bit of Time to Release */
  52 #define RELEASE_1               0x04    /* higher bit of Time to Release */
  53
  54 /* controller registers */
  55 #define SIFR                    0       /* read Status Interface Register,
  56                                            2 bytes, little endian */
  57 #define SIFR_CMD_MASK           0x2f
  58
  59 #define CIFR                    0       /* write - Command Interface Reg,
  60                                            2 bytes, little endian */
  61 #define CIFR_LONG_CMD           (1<<14) /* 4 word command */
  62
  63 /* Command Codes */
  64 #define CMD_READ_DATA           0x01    /* uses DMA */
  65 #define CMD_WRITE_DATA          0x02    /* uses DMA */
  66 #define CMD_READ_VERIFY         0x03
  67 #define CMD_WRITE_VERIFY        0x04    /* uses DMA */
  68 #define CMD_SEEK                0x05
  69 #define CMD_PARK_HEAD           0x06
  70 #define CMD_GET_CMD_COMP_STATUS 0x07
  71 #define CMD_GET_DEV_STATUS      0x08
  72 #define CMD_GET_DEV_CONF        0x09
  73 #define CMD_GET_POS_INFO        0x0A
  74 #define CMD_TRANSLATE_RBA       0x0B
  75 #define CMD_WRITE_ATTACH_BUFF   0x10    /* uses DMA */
  76 #define CMD_READ_ATTACH_BUFF    0x11    /* uses DMA */
  77 #define CMD_RUN_DIAG_TEST       0x12
  78 #define CMD_GET_DIAG_STAT_BLOCK 0x14
  79 #define CMD_GET_MFG_HEADER      0x15    /* uses DMA */
  80 #define CMD_FORMAT_UNIT         0x16    /* uses DMA */
  81 #define CMD_FORMAT_PREPARE      0x17
  82 #define CMD_SET_MAX_RBA         0x1A
  83 #define CMD_SET_PWR_SAV_MODE    0x1B    /* optional */
  84 #define CMD_POWER_CONS_CMD      0x1C    /* optional */
  85
  86 #define BCR                     2       /* write */
  87 #define BCR_INT_ENABLE          0x01
  88 #define BCR_DMA_ENABLE          0x02
  89 #define BCR_RESET               0x80
  90
  91 #define BSR                     2       /* read */
  92 #define BSR_DMA_ENABLED         0x80
  93 #define BSR_INT_PENDING         0x40
  94 #define BSR_CMD_INPROGRESS      0x20
  95 #define BSR_BUSY                0x10
  96 #define BSR_SIFR_FULL           0x08    /* also called STATUS OUT */
  97 #define BSR_CIFR_FULL           0x04
  98 #define BSR_TRANSFER_REQ        0x02
  99 #define BSR_INTR                0x01
 100
 101 #define ISR                     3       /* read, Interrupt Status Register */
 102 #define ISR_DEV_SELECT_MASK     0xE0
 103 #define ISR_ATTACH_ERR          0x10
 104 #define ISR_INTR_ID_MASK        0x0F
 105 #define ISR_COMPLETED           0x01
 106 #define ISR_COMPLETED_WITH_ECC  0x03
 107 #define ISR_COMPLETED_RETRIES   0x05
 108 #define ISR_PARTIAL_FORMAT      0x06    /* Status available */
 109 #define ISR_COMPLETED_WARNING   0x08
 110 #define ISR_ABORT_COMPLETED     0x09
 111 #define ISR_RESET_COMPLETED     0x0A
 112 #define ISR_DATA_TRANSFER_RDY   0x0B    /* No Status Block */
 113 #define ISR_CMD_FAILED          0x0C
 114 #define ISR_DMA_ERROR           0x0D
 115 #define ISR_CMD_BLOCK_ERROR     0x0E
 116 #define ISR_ATTN_ERROR          0x0F
 117
 118 /* Macros to get info from command status block */
 119 #define SB_GET_CMD_STATUS(sb)   (((sb)[1] & 0xff00) >> 8)
 120 #define SB_RESBLKCNT_IDX        3
 121
 122 #define ATN                     3       /* write, Attention register */
 123 #define ATN_CMD_REQ             1
 124 #define ATN_END_INT             2       /* End of Interrupt (EOI) */
 125 #define ATN_ABORT_CMD           3
 126 #define ATN_RESET_ATTACHMENT    4
 127
 128 #define DASD_DEVNO_CONTROLLER   7       /* Device number for controller */