| blob | 08a50c4528eda8a0523914ba74db8e4a665aa941 |
1 /* $NetBSD: aic79xx.reg,v 1.11 2005/12/11 12:22:18 christos Exp $ */
3 /*
4 * Aic79xx register and scratch ram definitions.
5 *
6 * Copyright (c) 1994-2001 Justin T. Gibbs.
7 * Copyright (c) 2000-2002 Adaptec Inc.
8 * All rights reserved.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions, and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * substantially similar to the "NO WARRANTY" disclaimer below
18 * ("Disclaimer") and any redistribution must be conditioned upon
19 * including a substantially similar Disclaimer requirement for further
20 * binary redistribution.
21 * 3. Neither the names of the above-listed copyright holders nor the names
22 * of any contributors may be used to endorse or promote products derived
23 * from this software without specific prior written permission.
24 *
25 * Alternatively, this software may be distributed under the terms of the
26 * GNU General Public License ("GPL") version 2 as published by the Free
27 * Software Foundation.
28 *
29 * NO WARRANTY
30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
33 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
34 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
36 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
37 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
38 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
39 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
40 * POSSIBILITY OF SUCH DAMAGES.
41 *
42 * $FreeBSD: src/sys/dev/aic7xxx/aic79xx.reg,v 1.15 2003/06/10 03:25:24 gibbs Exp $
43 */
44 VERSION = "Id: //depot/aic7xxx/aic7xxx/aic79xx.reg#70 $"
46 /*
47 * This file is processed by the aic7xxx_asm utility for use in assembling
48 * firmware for the aic79xx family of SCSI host adapters as well as to generate
49 * a C header file for use in the kernel portion of the Aic79xx driver.
50 */
52 /* Register window Modes */
53 #define M_DFF0 0
54 #define M_DFF1 1
55 #define M_CCHAN 2
56 #define M_SCSI 3
57 #define M_CFG 4
58 #define M_DST_SHIFT 4
60 #define MK_MODE(src, dst) ((src) | ((dst) << M_DST_SHIFT))
61 #define SET_MODE(src, dst) \
62 SET_SRC_MODE src; \
63 SET_DST_MODE dst; \
64 if ((ahd->bugs & AHD_SET_MODE_BUG) != 0) { \
65 mvi MK_MODE(src, dst) call set_mode_work_around; \
66 } else { \
67 mvi MODE_PTR, MK_MODE(src, dst); \
68 }
70 #define TOGGLE_DFF_MODE \
71 if ((ahd->bugs & AHD_SET_MODE_BUG) != 0) { \
72 call toggle_dff_mode_work_around; \
73 } else { \
74 xor MODE_PTR, MK_MODE(M_DFF1, M_DFF1); \
75 }
77 #define RESTORE_MODE(mode) \
78 if ((ahd->bugs & AHD_SET_MODE_BUG) != 0) { \
79 mov mode call set_mode_work_around; \
80 } else { \
81 mov MODE_PTR, mode; \
82 }
84 #define SET_SEQINTCODE(code) \
85 if ((ahd->bugs & AHD_INTCOLLISION_BUG) != 0) { \
86 mvi code call set_seqint_work_around; \
87 } else { \
88 mvi SEQINTCODE, code; \
89 }
91 /*
92 * Mode Pointer
93 * Controls which of the 5, 512byte, address spaces should be used
94 * as the source and destination of any register accesses in our
95 * register window.
96 */
97 register MODE_PTR {
98 address 0x000
99 access_mode RW
100 field DST_MODE 0x70
101 field SRC_MODE 0x07
102 mode_pointer
103 }
105 const SRC_MODE_SHIFT 0
106 const DST_MODE_SHIFT 4
108 /*
109 * Host Interrupt Status
110 */
111 register INTSTAT {
112 address 0x001
113 access_mode RW
114 field HWERRINT 0x80
115 field BRKADRINT 0x40
116 field SWTMINT 0x20
117 field PCIINT 0x10
118 field SCSIINT 0x08
119 field SEQINT 0x04
120 field CMDCMPLT 0x02
121 field SPLTINT 0x01
122 mask INT_PEND 0xFF
123 }
125 /*
126 * Sequencer Interrupt Code
127 */
128 register SEQINTCODE {
129 address 0x002
130 access_mode RW
131 field {
132 NO_SEQINT, /* No seqint pending. */
133 BAD_PHASE, /* unknown scsi bus phase */
134 SEND_REJECT, /* sending a message reject */
135 PROTO_VIOLATION, /* Protocol Violation */
136 NO_MATCH, /* no cmd match for reconnect */
137 IGN_WIDE_RES, /* Complex IGN Wide Res Msg */
138 PDATA_REINIT, /*
139 * Returned to data phase
140 * that requires data
141 * transfer pointers to be
142 * recalculated from the
143 * transfer residual.
144 */
145 HOST_MSG_LOOP, /*
146 * The bus is ready for the
147 * host to perform another
148 * message transaction. This
149 * mechanism is used for things
150 * like sync/wide negotiation
151 * that require a kernel based
152 * message state engine.
153 */
154 BAD_STATUS, /* Bad status from target */
155 DATA_OVERRUN, /*
156 * Target attempted to write
157 * beyond the bounds of its
158 * command.
159 */
160 MKMSG_FAILED, /*
161 * Target completed command
162 * without honoring our ATN
163 * request to issue a message.
164 */
165 MISSED_BUSFREE, /*
166 * The sequencer never saw
167 * the bus go free after
168 * either a command complete
169 * or disconnect message.
170 */
171 DUMP_CARD_STATE,
172 ILLEGAL_PHASE,
173 INVALID_SEQINT,
174 CFG4ISTAT_INTR,
175 STATUS_OVERRUN,
176 CFG4OVERRUN,
177 ENTERING_NONPACK,
178 TASKMGMT_FUNC_COMPLETE, /*
179 * Task management function
180 * request completed with
181 * an expected busfree.
182 */
183 TASKMGMT_CMD_CMPLT_OKAY, /*
184 * A command with a non-zero
185 * task management function
186 * has completed via the normal
187 * command completion method
188 * for commands with a zero
189 * task management function.
190 * This happens when an attempt
191 * to abort a command loses
192 * the race for the command to
193 * complete normally.
194 */
195 TRACEPOINT0,
196 TRACEPOINT1,
197 TRACEPOINT2,
198 TRACEPOINT3,
199 SAW_HWERR,
200 BAD_SCB_STATUS
201 }
202 }
204 /*
205 * Clear Host Interrupt
206 */
207 register CLRINT {
208 address 0x003
209 access_mode WO
210 field CLRHWERRINT 0x80 /* Rev B or greater */
211 field CLRBRKADRINT 0x40
212 field CLRSWTMINT 0x20
213 field CLRPCIINT 0x10
214 field CLRSCSIINT 0x08
215 field CLRSEQINT 0x04
216 field CLRCMDINT 0x02
217 field CLRSPLTINT 0x01
218 }
220 /*
221 * Error Register
222 */
223 register ERROR {
224 address 0x004
225 access_mode RO
226 field CIOPARERR 0x80
227 field CIOACCESFAIL 0x40 /* Rev B or greater */
228 field MPARERR 0x20
229 field DPARERR 0x10
230 field SQPARERR 0x08
231 field ILLOPCODE 0x04
232 field DSCTMOUT 0x02
233 }
235 /*
236 * Clear Error
237 */
238 register CLRERR {
239 address 0x004
240 access_mode WO
241 field CLRCIOPARERR 0x80
242 field CLRCIOACCESFAIL 0x40 /* Rev B or greater */
243 field CLRMPARERR 0x20
244 field CLRDPARERR 0x10
245 field CLRSQPARERR 0x08
246 field CLRILLOPCODE 0x04
247 field CLRDSCTMOUT 0x02
248 }
250 /*
251 * Host Control Register
252 * Overall host control of the device.
253 */
254 register HCNTRL {
255 address 0x005
256 access_mode RW
257 field SEQ_RESET 0x80 /* Rev B or greater */
258 field POWRDN 0x40
259 field SWINT 0x10
260 field SWTIMER_START_B 0x08 /* Rev B or greater */
261 field PAUSE 0x04
262 field INTEN 0x02
263 field CHIPRST 0x01
264 field CHIPRSTACK 0x01
265 }
267 /*
268 * Host New SCB Queue Offset
269 */
270 register HNSCB_QOFF {
271 address 0x006
272 access_mode RW
273 size 2
274 }
276 /*
277 * Host Empty SCB Queue Offset
278 */
279 register HESCB_QOFF {
280 address 0x008
281 access_mode RW
282 }
284 /*
285 * Host Mailbox
286 */
287 register HS_MAILBOX {
288 address 0x00B
289 access_mode RW
290 mask HOST_TQINPOS 0x80 /* Boundary at either 0 or 128 */
291 mask ENINT_COALESCE 0x40 /* Perform interrupt coalescing */
292 }
294 /*
295 * Sequencer Interrupt Status
296 */
297 register SEQINTSTAT {
298 address 0x00C
299 access_mode RO
300 field SEQ_SWTMRTO 0x10
301 field SEQ_SEQINT 0x08
302 field SEQ_SCSIINT 0x04
303 field SEQ_PCIINT 0x02
304 field SEQ_SPLTINT 0x01
305 }
307 /*
308 * Clear SEQ Interrupt
309 */
310 register CLRSEQINTSTAT {
311 address 0x00C
312 access_mode WO
313 field CLRSEQ_SWTMRTO 0x10
314 field CLRSEQ_SEQINT 0x08
315 field CLRSEQ_SCSIINT 0x04
316 field CLRSEQ_PCIINT 0x02
317 field CLRSEQ_SPLTINT 0x01
318 }
320 /*
321 * Software Timer
322 */
323 register SWTIMER {
324 address 0x00E
325 access_mode RW
326 size 2
327 }
329 /*
330 * SEQ New SCB Queue Offset
331 */
332 register SNSCB_QOFF {
333 address 0x010
334 access_mode RW
335 size 2
336 modes M_CCHAN
337 }
339 /*
340 * SEQ Empty SCB Queue Offset
341 */
342 register SESCB_QOFF {
343 address 0x012
344 access_mode RW
345 modes M_CCHAN
346 }
348 /*
349 * SEQ Done SCB Queue Offset
350 */
351 register SDSCB_QOFF {
352 address 0x014
353 access_mode RW
354 modes M_CCHAN
355 size 2
356 }
358 /*
359 * Queue Offset Control & Status
360 */
361 register QOFF_CTLSTA {
362 address 0x016
363 access_mode RW
364 modes M_CCHAN
365 field EMPTY_SCB_AVAIL 0x80
366 field NEW_SCB_AVAIL 0x40
367 field SDSCB_ROLLOVR 0x20
368 field HS_MAILBOX_ACT 0x10
369 field SCB_QSIZE 0x0F {
370 SCB_QSIZE_4,
371 SCB_QSIZE_8,
372 SCB_QSIZE_16,
373 SCB_QSIZE_32,
374 SCB_QSIZE_64,
375 SCB_QSIZE_128,
376 SCB_QSIZE_256,
377 SCB_QSIZE_512,
378 SCB_QSIZE_1024,
379 SCB_QSIZE_2048,
380 SCB_QSIZE_4096,
381 SCB_QSIZE_8192,
382 SCB_QSIZE_16384
383 }
384 }
386 /*
387 * Interrupt Control
388 */
389 register INTCTL {
390 address 0x018
391 access_mode RW
392 field SWTMINTMASK 0x80
393 field SWTMINTEN 0x40
394 field SWTIMER_START 0x20
395 field AUTOCLRCMDINT 0x10
396 field PCIINTEN 0x08
397 field SCSIINTEN 0x04
398 field SEQINTEN 0x02
399 field SPLTINTEN 0x01
400 }
402 /*
403 * Data FIFO Control
404 */
405 register DFCNTRL {
406 address 0x019
407 access_mode RW
408 modes M_DFF0, M_DFF1
409 field PRELOADEN 0x80
410 field SCSIENWRDIS 0x40 /* Rev B only. */
411 field SCSIEN 0x20
412 field SCSIENACK 0x20
413 field HDMAEN 0x08
414 field HDMAENACK 0x08
415 field DIRECTION 0x04
416 field DIRECTIONACK 0x04
417 field FIFOFLUSH 0x02
418 field FIFOFLUSHACK 0x02
419 field DIRECTIONEN 0x01
420 }
422 /*
423 * Device Space Command 0
424 */
425 register DSCOMMAND0 {
426 address 0x019
427 access_mode RW
428 modes M_CFG
429 field CACHETHEN 0x80 /* Cache Threshold enable */
430 field DPARCKEN 0x40 /* Data Parity Check Enable */
431 field MPARCKEN 0x20 /* Memory Parity Check Enable */
432 field EXTREQLCK 0x10 /* External Request Lock */
433 field DISABLE_TWATE 0x02 /* Rev B or greater */
434 field CIOPARCKEN 0x01 /* Internal bus parity error enable */
435 }
437 /*
438 * Data FIFO Status
439 */
440 register DFSTATUS {
441 address 0x01A
442 access_mode RO
443 modes M_DFF0, M_DFF1
444 field PRELOAD_AVAIL 0x80
445 field PKT_PRELOAD_AVAIL 0x40
446 field MREQPEND 0x10
447 field HDONE 0x08
448 field DFTHRESH 0x04
449 field FIFOFULL 0x02
450 field FIFOEMP 0x01
451 }
453 /*
454 * S/G Cache Pointer
455 */
456 register SG_CACHE_PRE {
457 address 0x01B
458 access_mode WO
459 modes M_DFF0, M_DFF1
460 field SG_ADDR_MASK 0xf8
461 field ODD_SEG 0x04
462 field LAST_SEG 0x02
463 }
465 register SG_CACHE_SHADOW {
466 address 0x01B
467 access_mode RO
468 modes M_DFF0, M_DFF1
469 field SG_ADDR_MASK 0xf8
470 field ODD_SEG 0x04
471 field LAST_SEG 0x02
472 field LAST_SEG_DONE 0x01
473 }
475 /*
476 * Arbiter Control
477 */
478 register ARBCTL {
479 address 0x01B
480 access_mode RW
481 modes M_CFG
482 field RESET_HARB 0x80
483 field RETRY_SWEN 0x08
484 field USE_TIME 0x07
485 }
487 /*
488 * Data Channel Host Address
489 */
490 register HADDR {
491 address 0x070
492 access_mode RW
493 size 8
494 modes M_DFF0, M_DFF1
495 }
497 /*
498 * Host Overlay DMA Address
499 */
500 register HODMAADR {
501 address 0x070
502 access_mode RW
503 size 8
504 modes M_SCSI
505 }
507 /*
508 * PCI PLL Delay.
509 */
510 register PLLDELAY {
511 address 0x070
512 access_mode RW
513 size 1
514 modes M_CFG
515 field SPLIT_DROP_REQ 0x80
516 }
518 /*
519 * Data Channel Host Count
520 */
521 register HCNT {
522 address 0x078
523 access_mode RW
524 size 3
525 modes M_DFF0, M_DFF1
526 }
528 /*
529 * Host Overlay DMA Count
530 */
531 register HODMACNT {
532 address 0x078
533 access_mode RW
534 size 2
535 modes M_SCSI
536 }
538 /*
539 * Host Overlay DMA Enable
540 */
541 register HODMAEN {
542 address 0x07A
543 access_mode RW
544 modes M_SCSI
545 }
547 /*
548 * Scatter/Gather Host Address
549 */
550 register SGHADDR {
551 address 0x07C
552 access_mode RW
553 size 8
554 modes M_DFF0, M_DFF1
555 }
557 /*
558 * SCB Host Address
559 */
560 register SCBHADDR {
561 address 0x07C
562 access_mode RW
563 size 8
564 modes M_CCHAN
565 }
567 /*
568 * Scatter/Gather Host Count
569 */
570 register SGHCNT {
571 address 0x084
572 access_mode RW
573 modes M_DFF0, M_DFF1
574 }
576 /*
577 * SCB Host Count
578 */
579 register SCBHCNT {
580 address 0x084
581 access_mode RW
582 modes M_CCHAN
583 }
585 /*
586 * Data FIFO Threshold
587 */
588 register DFF_THRSH {
589 address 0x088
590 access_mode RW
591 modes M_CFG
592 field WR_DFTHRSH 0x70 {
593 WR_DFTHRSH_MIN,
594 WR_DFTHRSH_25,
595 WR_DFTHRSH_50,
596 WR_DFTHRSH_63,
597 WR_DFTHRSH_75,
598 WR_DFTHRSH_85,
599 WR_DFTHRSH_90,
600 WR_DFTHRSH_MAX
601 }
602 field RD_DFTHRSH 0x07 {
603 RD_DFTHRSH_MIN,
604 RD_DFTHRSH_25,
605 RD_DFTHRSH_50,
606 RD_DFTHRSH_63,
607 RD_DFTHRSH_75,
608 RD_DFTHRSH_85,
609 RD_DFTHRSH_90,
610 RD_DFTHRSH_MAX
611 }
612 }
614 /*
615 * ROM Address
616 */
617 register ROMADDR {
618 address 0x08A
619 access_mode RW
620 size 3
621 }
623 /*
624 * ROM Control
625 */
626 register ROMCNTRL {
627 address 0x08D
628 access_mode RW
629 field ROMOP 0xE0
630 field ROMSPD 0x18
631 field REPEAT 0x02
632 field RDY 0x01
633 }
635 /*
636 * ROM Data
637 */
638 register ROMDATA {
639 address 0x08E
640 access_mode RW
641 }
643 /*
644 * Data Channel Receive Message 0
645 */
646 register DCHRXMSG0 {
647 address 0x090
648 access_mode RO
649 modes M_DFF0, M_DFF1
650 field CDNUM 0xF8
651 field CFNUM 0x07
652 }
654 /*
655 * CMC Recieve Message 0
656 */
657 register CMCRXMSG0 {
658 address 0x090
659 access_mode RO
660 modes M_CCHAN
661 field CDNUM 0xF8
662 field CFNUM 0x07
663 }
665 /*
666 * Overlay Recieve Message 0
667 */
668 register OVLYRXMSG0 {
669 address 0x090
670 access_mode RO
671 modes M_SCSI
672 field CDNUM 0xF8
673 field CFNUM 0x07
674 }
676 /*
677 * Relaxed Order Enable
678 */
679 register ROENABLE {
680 address 0x090
681 access_mode RW
682 modes M_CFG
683 field MSIROEN 0x20
684 field OVLYROEN 0x10
685 field CMCROEN 0x08
686 field SGROEN 0x04
687 field DCH1ROEN 0x02
688 field DCH0ROEN 0x01
689 }
691 /*
692 * Data Channel Receive Message 1
693 */
694 register DCHRXMSG1 {
695 address 0x091
696 access_mode RO
697 modes M_DFF0, M_DFF1
698 field CBNUM 0xFF
699 }
701 /*
702 * CMC Recieve Message 1
703 */
704 register CMCRXMSG1 {
705 address 0x091
706 access_mode RO
707 modes M_CCHAN
708 field CBNUM 0xFF
709 }
711 /*
712 * Overlay Recieve Message 1
713 */
714 register OVLYRXMSG1 {
715 address 0x091
716 access_mode RO
717 modes M_SCSI
718 field CBNUM 0xFF
719 }
721 /*
722 * No Snoop Enable
723 */
724 register NSENABLE {
725 address 0x091
726 access_mode RW
727 modes M_CFG
728 field MSINSEN 0x20
729 field OVLYNSEN 0x10
730 field CMCNSEN 0x08
731 field SGNSEN 0x04
732 field DCH1NSEN 0x02
733 field DCH0NSEN 0x01
734 }
736 /*
737 * Data Channel Receive Message 2
738 */
739 register DCHRXMSG2 {
740 address 0x092
741 access_mode RO
742 modes M_DFF0, M_DFF1
743 field MINDEX 0xFF
744 }
746 /*
747 * CMC Recieve Message 2
748 */
749 register CMCRXMSG2 {
750 address 0x092
751 access_mode RO
752 modes M_CCHAN
753 field MINDEX 0xFF
754 }
756 /*
757 * Overlay Recieve Message 2
758 */
759 register OVLYRXMSG2 {
760 address 0x092
761 access_mode RO
762 modes M_SCSI
763 field MINDEX 0xFF
764 }
766 /*
767 * Outstanding Split Transactions
768 */
769 register OST {
770 address 0x092
771 access_mode RW
772 modes M_CFG
773 }
775 /*
776 * Data Channel Receive Message 3
777 */
778 register DCHRXMSG3 {
779 address 0x093
780 access_mode RO
781 modes M_DFF0, M_DFF1
782 field MCLASS 0x0F
783 }
785 /*
786 * CMC Recieve Message 3
787 */
788 register CMCRXMSG3 {
789 address 0x093
790 access_mode RO
791 modes M_CCHAN
792 field MCLASS 0x0F
793 }
795 /*
796 * Overlay Recieve Message 3
797 */
798 register OVLYRXMSG3 {
799 address 0x093
800 access_mode RO
801 modes M_SCSI
802 field MCLASS 0x0F
803 }
805 /*
806 * PCI-X Control
807 */
808 register PCIXCTL {
809 address 0x093
810 access_mode RW
811 modes M_CFG
812 field SERRPULSE 0x80
813 field UNEXPSCIEN 0x20
814 field SPLTSMADIS 0x10
815 field SPLTSTADIS 0x08
816 field SRSPDPEEN 0x04
817 field TSCSERREN 0x02
818 field CMPABCDIS 0x01
819 }
821 /*
822 * CMC Sequencer Byte Count
823 */
824 register CMCSEQBCNT {
825 address 0x094
826 access_mode RO
827 modes M_CCHAN
828 }
830 /*
831 * Overlay Sequencer Byte Count
832 */
833 register OVLYSEQBCNT {
834 address 0x094
835 access_mode RO
836 modes M_SCSI
837 }
839 /*
840 * Data Channel Sequencer Byte Count
841 */
842 register DCHSEQBCNT {
843 address 0x094
844 access_mode RO
845 size 2
846 modes M_DFF0, M_DFF1
847 }
849 /*
850 * Data Channel Split Status 0
851 */
852 register DCHSPLTSTAT0 {
853 address 0x096
854 access_mode RW
855 modes M_DFF0, M_DFF1
856 field STAETERM 0x80
857 field SCBCERR 0x40
858 field SCADERR 0x20
859 field SCDATBUCKET 0x10
860 field CNTNOTCMPLT 0x08
861 field RXOVRUN 0x04
862 field RXSCEMSG 0x02
863 field RXSPLTRSP 0x01
864 }
866 /*
867 * CMC Split Status 0
868 */
869 register CMCSPLTSTAT0 {
870 address 0x096
871 access_mode RW
872 modes M_CCHAN
873 field STAETERM 0x80
874 field SCBCERR 0x40
875 field SCADERR 0x20
876 field SCDATBUCKET 0x10
877 field CNTNOTCMPLT 0x08
878 field RXOVRUN 0x04
879 field RXSCEMSG 0x02
880 field RXSPLTRSP 0x01
881 }
883 /*
884 * Overlay Split Status 0
885 */
886 register OVLYSPLTSTAT0 {
887 address 0x096
888 access_mode RW
889 modes M_SCSI
890 field STAETERM 0x80
891 field SCBCERR 0x40
892 field SCADERR 0x20
893 field SCDATBUCKET 0x10
894 field CNTNOTCMPLT 0x08
895 field RXOVRUN 0x04
896 field RXSCEMSG 0x02
897 field RXSPLTRSP 0x01
898 }
900 /*
901 * Data Channel Split Status 1
902 */
903 register DCHSPLTSTAT1 {
904 address 0x097
905 access_mode RW
906 modes M_DFF0, M_DFF1
907 field RXDATABUCKET 0x01
908 }
910 /*
911 * CMC Split Status 1
912 */
913 register CMCSPLTSTAT1 {
914 address 0x097
915 access_mode RW
916 modes M_CCHAN
917 field RXDATABUCKET 0x01
918 }
920 /*
921 * Overlay Split Status 1
922 */
923 register OVLYSPLTSTAT1 {
924 address 0x097
925 access_mode RW
926 modes M_SCSI
927 field RXDATABUCKET 0x01
928 }
930 /*
931 * S/G Receive Message 0
932 */
933 register SGRXMSG0 {
934 address 0x098
935 access_mode RO
936 modes M_DFF0, M_DFF1
937 field CDNUM 0xF8
938 field CFNUM 0x07
939 }
941 /*
942 * S/G Receive Message 1
943 */
944 register SGRXMSG1 {
945 address 0x099
946 access_mode RO
947 modes M_DFF0, M_DFF1
948 field CBNUM 0xFF
949 }
951 /*
952 * S/G Receive Message 2
953 */
954 register SGRXMSG2 {
955 address 0x09A
956 access_mode RO
957 modes M_DFF0, M_DFF1
958 field MINDEX 0xFF
959 }
961 /*
962 * S/G Receive Message 3
963 */
964 register SGRXMSG3 {
965 address 0x09B
966 access_mode RO
967 modes M_DFF0, M_DFF1
968 field MCLASS 0x0F
969 }
971 /*
972 * Slave Split Out Address 0
973 */
974 register SLVSPLTOUTADR0 {
975 address 0x098
976 access_mode RO
977 modes M_SCSI
978 field LOWER_ADDR 0x7F
979 }
981 /*
982 * Slave Split Out Address 1
983 */
984 register SLVSPLTOUTADR1 {
985 address 0x099
986 access_mode RO
987 modes M_SCSI
988 field REQ_DNUM 0xF8
989 field REQ_FNUM 0x07
990 }
992 /*
993 * Slave Split Out Address 2
994 */
995 register SLVSPLTOUTADR2 {
996 address 0x09A
997 access_mode RO
998 modes M_SCSI
999 field REQ_BNUM 0xFF
1000 }
1002 /*
1003 * Slave Split Out Address 3
1004 */
1005 register SLVSPLTOUTADR3 {
1006 address 0x09B
1007 access_mode RO
1008 modes M_SCSI
1009 field RLXORD 020
1010 field TAG_NUM 0x1F
1011 }
1013 /*
1014 * SG Sequencer Byte Count
1015 */
1016 register SGSEQBCNT {
1017 address 0x09C
1018 access_mode RO
1019 modes M_DFF0, M_DFF1
1020 }
1022 /*
1023 * Slave Split Out Attribute 0
1024 */
1025 register SLVSPLTOUTATTR0 {
1026 address 0x09C
1027 access_mode RO
1028 modes M_SCSI
1029 field LOWER_BCNT 0xFF
1030 }
1032 /*
1033 * Slave Split Out Attribute 1
1034 */
1035 register SLVSPLTOUTATTR1 {
1036 address 0x09D
1037 access_mode RO
1038 modes M_SCSI
1039 field CMPLT_DNUM 0xF8
1040 field CMPLT_FNUM 0x07
1041 }
1043 /*
1044 * Slave Split Out Attribute 2
1045 */
1046 register SLVSPLTOUTATTR2 {
1047 address 0x09E
1048 access_mode RO
1049 size 2
1050 modes M_SCSI
1051 field CMPLT_BNUM 0xFF
1052 }
1053 /*
1054 * S/G Split Status 0
1055 */
1056 register SGSPLTSTAT0 {
1057 address 0x09E
1058 access_mode RW
1059 modes M_DFF0, M_DFF1
1060 field STAETERM 0x80
1061 field SCBCERR 0x40
1062 field SCADERR 0x20
1063 field SCDATBUCKET 0x10
1064 field CNTNOTCMPLT 0x08
1065 field RXOVRUN 0x04
1066 field RXSCEMSG 0x02
1067 field RXSPLTRSP 0x01
1068 }
1070 /*
1071 * S/G Split Status 1
1072 */
1073 register SGSPLTSTAT1 {
1074 address 0x09F
1075 access_mode RW
1076 modes M_DFF0, M_DFF1
1077 field RXDATABUCKET 0x01
1078 }
1080 /*
1081 * Special Function
1082 */
1083 register SFUNCT {
1084 address 0x09f
1085 access_mode RW
1086 modes M_CFG
1087 field TEST_GROUP 0xF0
1088 field TEST_NUM 0x0F
1089 }
1091 /*
1092 * Data FIFO 0 PCI Status
1093 */
1094 register DF0PCISTAT {
1095 address 0x0A0
1096 access_mode RW
1097 modes M_CFG
1098 field DPE 0x80
1099 field SSE 0x40
1100 field RMA 0x20
1101 field RTA 0x10
1102 field SCAAPERR 0x08
1103 field RDPERR 0x04
1104 field TWATERR 0x02
1105 field DPR 0x01
1106 }
1108 /*
1109 * Data FIFO 1 PCI Status
1110 */
1111 register DF1PCISTAT {
1112 address 0x0A1
1113 access_mode RW
1114 modes M_CFG
1115 field DPE 0x80
1116 field SSE 0x40
1117 field RMA 0x20
1118 field RTA 0x10
1119 field SCAAPERR 0x08
1120 field RDPERR 0x04
1121 field TWATERR 0x02
1122 field DPR 0x01
1123 }
1125 /*
1126 * S/G PCI Status
1127 */
1128 register SGPCISTAT {
1129 address 0x0A2
1130 access_mode RW
1131 modes M_CFG
1132 field DPE 0x80
1133 field SSE 0x40
1134 field RMA 0x20
1135 field RTA 0x10
1136 field SCAAPERR 0x08
1137 field RDPERR 0x04
1138 field DPR 0x01
1139 }
1141 /*
1142 * CMC PCI Status
1143 */
1144 register CMCPCISTAT {
1145 address 0x0A3
1146 access_mode RW
1147 modes M_CFG
1148 field DPE 0x80
1149 field SSE 0x40
1150 field RMA 0x20
1151 field RTA 0x10
1152 field SCAAPERR 0x08
1153 field RDPERR 0x04
1154 field TWATERR 0x02
1155 field DPR 0x01
1156 }
1158 /*
1159 * Overlay PCI Status
1160 */
1161 register OVLYPCISTAT {
1162 address 0x0A4
1163 access_mode RW
1164 modes M_CFG
1165 field DPE 0x80
1166 field SSE 0x40
1167 field RMA 0x20
1168 field RTA 0x10
1169 field SCAAPERR 0x08
1170 field RDPERR 0x04
1171 field DPR 0x01
1172 }
1174 /*
1175 * PCI Status for MSI Master DMA Transfer
1176 */
1177 register MSIPCISTAT {
1178 address 0x0A6
1179 access_mode RW
1180 modes M_CFG
1181 field SSE 0x40
1182 field RMA 0x20
1183 field RTA 0x10
1184 field CLRPENDMSI 0x08
1185 field TWATERR 0x02
1186 field DPR 0x01
1187 }
1189 /*
1190 * PCI Status for Target
1191 */
1192 register TARGPCISTAT {
1193 address 0x0A7
1194 access_mode RW
1195 modes M_CFG
1196 field DPE 0x80
1197 field SSE 0x40
1198 field STA 0x08
1199 field TWATERR 0x02
1200 }
1202 /*
1203 * LQ Packet In
1204 * The last LQ Packet recieved
1205 */
1206 register LQIN {
1207 address 0x020
1208 access_mode RW
1209 size 20
1210 modes M_DFF0, M_DFF1, M_SCSI
1211 }
1213 /*
1214 * SCB Type Pointer
1215 * SCB offset for Target Mode SCB type information
1216 */
1217 register TYPEPTR {
1218 address 0x020
1219 access_mode RW
1220 modes M_CFG
1221 }
1223 /*
1224 * Queue Tag Pointer
1225 * SCB offset to the Two Byte tag identifier used for target mode.
1226 */
1227 register TAGPTR {
1228 address 0x021
1229 access_mode RW
1230 modes M_CFG
1231 }
1233 /*
1234 * Logical Unit Number Pointer
1235 * SCB offset to the LSB (little endian) of the lun field.
1236 */
1237 register LUNPTR {
1238 address 0x022
1239 access_mode RW
1240 modes M_CFG
1241 }
1243 /*
1244 * Data Length Pointer
1245 * SCB offset for the 4 byte data length field in target mode.
1246 */
1247 register DATALENPTR {
1248 address 0x023
1249 access_mode RW
1250 modes M_CFG
1251 }
1253 /*
1254 * Status Length Pointer
1255 * SCB offset to the two byte status field in target SCBs.
1256 */
1257 register STATLENPTR {
1258 address 0x024
1259 access_mode RW
1260 modes M_CFG
1261 }
1263 /*
1264 * Command Length Pointer
1265 * Scb offset for the CDB length field in initiator SCBs.
1266 */
1267 register CMDLENPTR {
1268 address 0x025
1269 access_mode RW
1270 modes M_CFG
1271 }
1273 /*
1274 * Task Attribute Pointer
1275 * Scb offset for the byte field specifying the attribute byte
1276 * to be used in command packets.
1277 */
1278 register ATTRPTR {
1279 address 0x026
1280 access_mode RW
1281 modes M_CFG
1282 }
1284 /*
1285 * Task Management Flags Pointer
1286 * Scb offset for the byte field specifying the attribute flags
1287 * byte to be used in command packets.
1288 */
1289 register FLAGPTR {
1290 address 0x027
1291 access_mode RW
1292 modes M_CFG
1293 }
1295 /*
1296 * Command Pointer
1297 * Scb offset for the first byte in the CDB for initiator SCBs.
1298 */
1299 register CMDPTR {
1300 address 0x028
1301 access_mode RW
1302 modes M_CFG
1303 }
1305 /*
1306 * Queue Next Pointer
1307 * Scb offset for the 2 byte "next scb link".
1308 */
1309 register QNEXTPTR {
1310 address 0x029
1311 access_mode RW
1312 modes M_CFG
1313 }
1315 /*
1316 * SCSI ID Pointer
1317 * Scb offset to the value to place in the SCSIID register
1318 * during target mode connections.
1319 */
1320 register IDPTR {
1321 address 0x02A
1322 access_mode RW
1323 modes M_CFG
1324 }
1326 /*
1327 * Command Aborted Byte Pointer
1328 * Offset to the SCB flags field that includes the
1329 * "SCB aborted" status bit.
1330 */
1331 register ABRTBYTEPTR {
1332 address 0x02B
1333 access_mode RW
1334 modes M_CFG
1335 }
1337 /*
1338 * Command Aborted Bit Pointer
1339 * Bit offset in the SCB flags field for "SCB aborted" status.
1340 */
1341 register ABRTBITPTR {
1342 address 0x02C
1343 access_mode RW
1344 modes M_CFG
1345 }
1347 /*
1348 * Rev B or greater.
1349 */
1350 register MAXCMDBYTES {
1351 address 0x02D
1352 access_mode RW
1353 modes M_CFG
1354 }
1356 /*
1357 * Rev B or greater.
1358 */
1359 register MAXCMD2RCV {
1360 address 0x02E
1361 access_mode RW
1362 modes M_CFG
1363 }
1365 /*
1366 * Rev B or greater.
1367 */
1368 register SHORTTHRESH {
1369 address 0x02F
1370 access_mode RW
1371 modes M_CFG
1372 }
1374 /*
1375 * Logical Unit Number Length
1376 * The length, in bytes, of the SCB lun field.
1377 */
1378 register LUNLEN {
1379 address 0x030
1380 access_mode RW
1381 modes M_CFG
1382 mask ILUNLEN 0x0F
1383 mask TLUNLEN 0xF0
1384 }
1385 const LUNLEN_SINGLE_LEVEL_LUN 0xF
1387 /*
1388 * CDB Limit
1389 * The size, in bytes, of the embedded CDB field in initator SCBs.
1390 */
1391 register CDBLIMIT {
1392 address 0x031
1393 access_mode RW
1394 modes M_CFG
1395 }
1397 /*
1398 * Maximum Commands
1399 * The maximum number of commands to issue during a
1400 * single packetized connection.
1401 */
1402 register MAXCMD {
1403 address 0x032
1404 access_mode RW
1405 modes M_CFG
1406 }
1408 /*
1409 * Maximum Command Counter
1410 * The number of commands already sent during this connection
1411 */
1412 register MAXCMDCNT {
1413 address 0x033
1414 access_mode RW
1415 modes M_CFG
1416 }
1418 /*
1419 * LQ Packet Reserved Bytes
1420 * The bytes to be sent in the currently reserved fileds
1421 * of all LQ packets.
1422 */
1423 register LQRSVD01 {
1424 address 0x034
1425 access_mode RW
1426 modes M_SCSI
1427 }
1428 register LQRSVD16 {
1429 address 0x035
1430 access_mode RW
1431 modes M_SCSI
1432 }
1433 register LQRSVD17 {
1434 address 0x036
1435 access_mode RW
1436 modes M_SCSI
1437 }
1439 /*
1440 * Command Reserved 0
1441 * The byte to be sent for the reserved byte 0 of
1442 * outgoing command packets.
1443 */
1444 register CMDRSVD0 {
1445 address 0x037
1446 access_mode RW
1447 modes M_CFG
1448 }
1450 /*
1451 * LQ Manager Control 0
1452 */
1453 register LQCTL0 {
1454 address 0x038
1455 access_mode RW
1456 modes M_CFG
1457 field LQITARGCLT 0xC0
1458 field LQIINITGCLT 0x30
1459 field LQ0TARGCLT 0x0C
1460 field LQ0INITGCLT 0x03
1461 }
1463 /*
1464 * LQ Manager Control 1
1465 */
1466 register LQCTL1 {
1467 address 0x038
1468 access_mode RW
1469 modes M_DFF0, M_DFF1, M_SCSI
1470 field PCI2PCI 0x04
1471 field SINGLECMD 0x02
1472 field ABORTPENDING 0x01
1473 }
1475 /*
1476 * LQ Manager Control 2
1477 */
1478 register LQCTL2 {
1479 address 0x039
1480 access_mode RW
1481 modes M_DFF0, M_DFF1, M_SCSI
1482 field LQIRETRY 0x80
1483 field LQICONTINUE 0x40
1484 field LQITOIDLE 0x20
1485 field LQIPAUSE 0x10
1486 field LQORETRY 0x08
1487 field LQOCONTINUE 0x04
1488 field LQOTOIDLE 0x02
1489 field LQOPAUSE 0x01
1490 }
1492 /*
1493 * SCSI RAM BIST0
1494 */
1495 register SCSBIST0 {
1496 address 0x039
1497 access_mode RW
1498 modes M_CFG
1499 field GSBISTERR 0x40
1500 field GSBISTDONE 0x20
1501 field GSBISTRUN 0x10
1502 field OSBISTERR 0x04
1503 field OSBISTDONE 0x02
1504 field OSBISTRUN 0x01
1505 }
1507 /*
1508 * SCSI Sequence Control0
1509 */
1510 register SCSISEQ0 {
1511 address 0x03A
1512 access_mode RW
1513 modes M_DFF0, M_DFF1, M_SCSI
1514 field TEMODEO 0x80
1515 field ENSELO 0x40
1516 field ENARBO 0x20
1517 field FORCEBUSFREE 0x10
1518 field SCSIRSTO 0x01
1519 }
1521 /*
1522 * SCSI RAM BIST 1
1523 */
1524 register SCSBIST1 {
1525 address 0x03A
1526 access_mode RW
1527 modes M_CFG
1528 field NTBISTERR 0x04
1529 field NTBISTDONE 0x02
1530 field NTBISTRUN 0x01
1531 }
1533 /*
1534 * SCSI Sequence Control 1
1535 */
1536 register SCSISEQ1 {
1537 address 0x03B
1538 access_mode RW
1539 modes M_DFF0, M_DFF1, M_SCSI
1540 field MANUALCTL 0x40
1541 field ENSELI 0x20
1542 field ENRSELI 0x10
1543 field MANUALP 0x0C
1544 field ENAUTOATNP 0x02
1545 field ALTSTIM 0x01
1546 }
1548 /*
1549 * SCSI Transfer Control 0
1550 */
1551 register SXFRCTL0 {
1552 address 0x03C
1553 access_mode RW
1554 modes M_SCSI
1555 field DFON 0x80
1556 field DFPEXP 0x40
1557 field BIOSCANCELEN 0x10
1558 field SPIOEN 0x08
1559 }
1561 /*
1562 * SCSI Transfer Control 1
1563 */
1564 register SXFRCTL1 {
1565 address 0x03D
1566 access_mode RW
1567 modes M_SCSI
1568 field BITBUCKET 0x80
1569 field ENSACHK 0x40
1570 field ENSPCHK 0x20
1571 field STIMESEL 0x18
1572 field ENSTIMER 0x04
1573 field ACTNEGEN 0x02
1574 field STPWEN 0x01
1575 }
1577 /*
1578 * SCSI Transfer Control 2
1579 */
1580 register SXFRCTL2 {
1581 address 0x03E
1582 access_mode RW
1583 modes M_SCSI
1584 field AUTORSTDIS 0x10
1585 field CMDDMAEN 0x08
1586 field ASU 0x07
1587 }
1589 /*
1590 * SCSI Bus Initiator IDs
1591 * Bitmask of observed initiators on the bus.
1592 */
1593 register BUSINITID {
1594 address 0x03C
1595 access_mode RW
1596 modes M_CFG
1597 size 2
1598 }
1600 /*
1601 * Data Length Counters
1602 * Packet byte counter.
1603 */
1604 register DLCOUNT {
1605 address 0x03C
1606 access_mode RW
1607 modes M_DFF0, M_DFF1
1608 size 3
1609 }
1611 /*
1612 * Data FIFO Status
1613 */
1614 register DFFSTAT {
1615 address 0x03F
1616 access_mode RW
1617 modes M_SCSI
1618 field FIFO1FREE 0x20
1619 field FIFO0FREE 0x10
1620 /*
1621 * On the B, this enum only works
1622 * in the read direction. For writes,
1623 * you must use the B version of the
1624 * CURRFIFO_0 definition which is defined
1625 * as a constant outside of this register
1626 * definition to avoid confusing the
1627 * register pretty printing code.
1628 */
1629 enum CURRFIFO 0x03 {
1630 CURRFIFO_0,
1631 CURRFIFO_1,
1632 CURRFIFO_NONE 0x3
1633 }
1634 }
1636 const B_CURRFIFO_0 0x2
1638 /*
1639 * SCSI Bus Target IDs
1640 * Bitmask of observed targets on the bus.
1641 */
1642 register BUSTARGID {
1643 address 0x03E
1644 access_mode RW
1645 modes M_CFG
1646 size 2
1647 }
1649 /*
1650 * SCSI Control Signal Out
1651 */
1652 register SCSISIGO {
1653 address 0x040
1654 access_mode RW
1655 modes M_DFF0, M_DFF1, M_SCSI
1656 field CDO 0x80
1657 field IOO 0x40
1658 field MSGO 0x20
1659 field ATNO 0x10
1660 field SELO 0x08
1661 field BSYO 0x04
1662 field REQO 0x02
1663 field ACKO 0x01
1664 /*
1665 * Possible phases to write into SCSISIG0
1666 */
1667 enum PHASE_MASK CDO|IOO|MSGO {
1668 P_DATAOUT 0x0,
1669 P_DATAIN IOO,
1670 P_DATAOUT_DT P_DATAOUT|MSGO,
1671 P_DATAIN_DT P_DATAIN|MSGO,
1672 P_COMMAND CDO,
1673 P_MESGOUT CDO|MSGO,
1674 P_STATUS CDO|IOO,
1675 P_MESGIN CDO|IOO|MSGO
1676 }
1677 }
1679 register SCSISIGI {
1680 address 0x041
1681 access_mode RO
1682 modes M_DFF0, M_DFF1, M_SCSI
1683 field CDI 0x80
1684 field IOI 0x40
1685 field MSGI 0x20
1686 field ATNI 0x10
1687 field SELI 0x08
1688 field BSYI 0x04
1689 field REQI 0x02
1690 field ACKI 0x01
1691 /*
1692 * Possible phases in SCSISIGI
1693 */
1694 enum PHASE_MASK CDO|IOO|MSGO {
1695 P_DATAOUT 0x0,
1696 P_DATAIN IOO,
1697 P_DATAOUT_DT P_DATAOUT|MSGO,
1698 P_DATAIN_DT P_DATAIN|MSGO,
1699 P_COMMAND CDO,
1700 P_MESGOUT CDO|MSGO,
1701 P_STATUS CDO|IOO,
1702 P_MESGIN CDO|IOO|MSGO
1703 }
1704 }
1706 /*
1707 * Multiple Target IDs
1708 * Bitmask of ids to respond as a target.
1709 */
1710 register MULTARGID {
1711 address 0x040
1712 access_mode RW
1713 modes M_CFG
1714 size 2
1715 }
1717 /*
1718 * SCSI Phase
1719 */
1720 register SCSIPHASE {
1721 address 0x042
1722 access_mode RO
1723 modes M_DFF0, M_DFF1, M_SCSI
1724 field STATUS_PHASE 0x20
1725 field COMMAND_PHASE 0x10
1726 field MSG_IN_PHASE 0x08
1727 field MSG_OUT_PHASE 0x04
1728 field DATA_PHASE_MASK 0x03 {
1729 DATA_OUT_PHASE 0x01,
1730 DATA_IN_PHASE 0x02
1731 }
1732 }
1734 /*
1735 * SCSI Data 0 Image
1736 */
1737 register SCSIDAT0_IMG {
1738 address 0x043
1739 access_mode RW
1740 modes M_DFF0, M_DFF1, M_SCSI
1741 }
1743 /*
1744 * SCSI Latched Data
1745 */
1746 register SCSIDAT {
1747 address 0x044
1748 access_mode RW
1749 modes M_DFF0, M_DFF1, M_SCSI
1750 size 2
1751 }
1753 /*
1754 * SCSI Data Bus
1755 */
1756 register SCSIBUS {
1757 address 0x046
1758 access_mode RW
1759 modes M_DFF0, M_DFF1, M_SCSI
1760 size 2
1761 }
1763 /*
1764 * Target ID In
1765 */
1766 register TARGIDIN {
1767 address 0x048
1768 access_mode RO
1769 modes M_DFF0, M_DFF1, M_SCSI
1770 field CLKOUT 0x80
1771 field TARGID 0x0F
1772 }
1774 /*
1775 * Selection/Reselection ID
1776 * Upper four bits are the device id. The ONEBIT is set when the re/selecting
1777 * device did not set its own ID.
1778 */
1779 register SELID {
1780 address 0x049
1781 access_mode RW
1782 modes M_DFF0, M_DFF1, M_SCSI
1783 field SELID_MASK 0xf0
1784 field ONEBIT 0x08
1785 }
1787 /*
1788 * SCSI Block Control
1789 * Controls Bus type and channel selection. SELWIDE allows for the
1790 * coexistence of 8bit and 16bit devices on a wide bus.
1791 */
1792 register SBLKCTL {
1793 address 0x04A
1794 access_mode RW
1795 modes M_DFF0, M_DFF1, M_SCSI
1796 field DIAGLEDEN 0x80
1797 field DIAGLEDON 0x40
1798 field ENAB40 0x08 /* LVD transceiver active */
1799 field ENAB20 0x04 /* SE/HVD transceiver active */
1800 field SELWIDE 0x02
1801 }
1803 /*
1804 * Option Mode
1805 */
1806 register OPTIONMODE {
1807 address 0x04A
1808 access_mode RW
1809 modes M_CFG
1810 field BIOSCANCTL 0x80
1811 field AUTOACKEN 0x40
1812 field BIASCANCTL 0x20
1813 field BUSFREEREV 0x10
1814 field ENDGFORMCHK 0x04
1815 field AUTO_MSGOUT_DE 0x02
1816 mask OPTIONMODE_DEFAULTS AUTO_MSGOUT_DE
1817 }
1819 /*
1820 * SCSI Status 0
1821 */
1822 register SSTAT0 {
1823 address 0x04B
1824 access_mode RO
1825 modes M_DFF0, M_DFF1, M_SCSI
1826 field TARGET 0x80 /* Board acting as target */
1827 field SELDO 0x40 /* Selection Done */
1828 field SELDI 0x20 /* Board has been selected */
1829 field SELINGO 0x10 /* Selection In Progress */
1830 field IOERR 0x08 /* LVD Tranceiver mode changed */
1831 field OVERRUN 0x04 /* SCSI Offset overrun detected */
1832 field SPIORDY 0x02 /* SCSI PIO Ready */
1833 field ARBDO 0x01 /* Arbitration Done Out */
1834 }
1836 /*
1837 * Clear SCSI Interrupt 0
1838 * Writing a 1 to a bit clears the associated SCSI Interrupt in SSTAT0.
1839 */
1840 register CLRSINT0 {
1841 address 0x04B
1842 access_mode WO
1843 modes M_DFF0, M_DFF1, M_SCSI
1844 field CLRSELDO 0x40
1845 field CLRSELDI 0x20
1846 field CLRSELINGO 0x10
1847 field CLRIOERR 0x08
1848 field CLROVERRUN 0x04
1849 field CLRSPIORDY 0x02
1850 field CLRARBDO 0x01
1851 }
1853 /*
1854 * SCSI Interrupt Mode 0
1855 * Setting any bit will enable the corresponding function
1856 * in SIMODE0 to interrupt via the IRQ pin.
1857 */
1858 register SIMODE0 {
1859 address 0x04B
1860 access_mode RW
1861 modes M_CFG
1862 field ENSELDO 0x40
1863 field ENSELDI 0x20
1864 field ENSELINGO 0x10
1865 field ENIOERR 0x08
1866 field ENOVERRUN 0x04
1867 field ENSPIORDY 0x02
1868 field ENARBDO 0x01
1869 }
1871 /*
1872 * SCSI Status 1
1873 */
1874 register SSTAT1 {
1875 address 0x04C
1876 access_mode RO
1877 modes M_DFF0, M_DFF1, M_SCSI
1878 field SELTO 0x80
1879 field ATNTARG 0x40
1880 field SCSIRSTI 0x20
1881 field PHASEMIS 0x10
1882 field BUSFREE 0x08
1883 field SCSIPERR 0x04
1884 field STRB2FAST 0x02
1885 field REQINIT 0x01
1886 }
1888 /*
1889 * Clear SCSI Interrupt 1
1890 * Writing a 1 to a bit clears the associated SCSI Interrupt in SSTAT1.
1891 */
1892 register CLRSINT1 {
1893 address 0x04C
1894 access_mode WO
1895 modes M_DFF0, M_DFF1, M_SCSI
1896 field CLRSELTIMEO 0x80
1897 field CLRATNO 0x40
1898 field CLRSCSIRSTI 0x20
1899 field CLRBUSFREE 0x08
1900 field CLRSCSIPERR 0x04
1901 field CLRSTRB2FAST 0x02
1902 field CLRREQINIT 0x01
1903 }
1905 /*
1906 * SCSI Status 2
1907 */
1908 register SSTAT2 {
1909 address 0x04d
1910 access_mode RO
1911 modes M_DFF0, M_DFF1, M_SCSI
1912 field BUSFREETIME 0xc0 {
1913 BUSFREE_LQO 0x40,
1914 BUSFREE_DFF0 0x80,
1915 BUSFREE_DFF1 0xC0
1916 }
1917 field NONPACKREQ 0x20
1918 field EXP_ACTIVE 0x10 /* SCSI Expander Active */
1919 field BSYX 0x08 /* Busy Expander */
1920 field WIDE_RES 0x04 /* Modes 0 and 1 only */
1921 field SDONE 0x02 /* Modes 0 and 1 only */
1922 field DMADONE 0x01 /* Modes 0 and 1 only */
1923 }
1925 /*
1926 * Clear SCSI Interrupt 2
1927 */
1928 register CLRSINT2 {
1929 address 0x04D
1930 access_mode WO
1931 modes M_DFF0, M_DFF1, M_SCSI
1932 field CLRNONPACKREQ 0x20
1933 field CLRWIDE_RES 0x04 /* Modes 0 and 1 only */
1934 field CLRSDONE 0x02 /* Modes 0 and 1 only */
1935 field CLRDMADONE 0x01 /* Modes 0 and 1 only */
1936 }
1938 /*
1939 * SCSI Interrupt Mode 2
1940 */
1941 register SIMODE2 {
1942 address 0x04D
1943 access_mode RW
1944 modes M_CFG
1945 field ENWIDE_RES 0x04
1946 field ENSDONE 0x02
1947 field ENDMADONE 0x01
1948 }
1950 /*
1951 * Physical Error Diagnosis
1952 */
1953 register PERRDIAG {
1954 address 0x04E
1955 access_mode RO
1956 modes M_DFF0, M_DFF1, M_SCSI
1957 field HIZERO 0x80
1958 field HIPERR 0x40
1959 field PREVPHASE 0x20
1960 field PARITYERR 0x10
1961 field AIPERR 0x08
1962 field CRCERR 0x04
1963 field DGFORMERR 0x02
1964 field DTERR 0x01
1965 }
1967 /*
1968 * LQI Manager Current State
1969 */
1970 register LQISTATE {
1971 address 0x04E
1972 access_mode RO
1973 modes M_CFG
1974 }
1976 /*
1977 * SCSI Offset Count
1978 */
1979 register SOFFCNT {
1980 address 0x04F
1981 access_mode RO
1982 modes M_DFF0, M_DFF1, M_SCSI
1983 }
1985 /*
1986 * LQO Manager Current State
1987 */
1988 register LQOSTATE {
1989 address 0x04F
1990 access_mode RO
1991 modes M_CFG
1992 }
1994 /*
1995 * LQI Manager Status
1996 */
1997 register LQISTAT0 {
1998 address 0x050
1999 access_mode RO
2000 modes M_DFF0, M_DFF1, M_SCSI
2001 field LQIATNQAS 0x20
2002 field LQICRCT1 0x10
2003 field LQICRCT2 0x08
2004 field LQIBADLQT 0x04
2005 field LQIATNLQ 0x02
2006 field LQIATNCMD 0x01
2007 }
2009 /*
2010 * Clear LQI Interrupts 0
2011 */
2012 register CLRLQIINT0 {
2013 address 0x050
2014 access_mode WO
2015 modes M_DFF0, M_DFF1, M_SCSI
2016 field CLRLQIATNQAS 0x20
2017 field CLRLQICRCT1 0x10
2018 field CLRLQICRCT2 0x08
2019 field CLRLQIBADLQT 0x04
2020 field CLRLQIATNLQ 0x02
2021 field CLRLQIATNCMD 0x01
2022 }
2024 /*
2025 * LQI Manager Interrupt Mode 0
2026 */
2027 register LQIMODE0 {
2028 address 0x050
2029 access_mode RW
2030 modes M_CFG
2031 field ENLQIATNQASK 0x20
2032 field ENLQICRCT1 0x10
2033 field ENLQICRCT2 0x08
2034 field ENLQIBADLQT 0x04
2035 field ENLQIATNLQ 0x02
2036 field ENLQIATNCMD 0x01
2037 }
2039 /*
2040 * LQI Manager Status 1
2041 */
2042 register LQISTAT1 {
2043 address 0x051
2044 access_mode RO
2045 modes M_DFF0, M_DFF1, M_SCSI
2046 field LQIPHASE_LQ 0x80
2047 field LQIPHASE_NLQ 0x40
2048 field LQIABORT 0x20
2049 field LQICRCI_LQ 0x10
2050 field LQICRCI_NLQ 0x08
2051 field LQIBADLQI 0x04
2052 field LQIOVERI_LQ 0x02
2053 field LQIOVERI_NLQ 0x01
2054 }
2056 /*
2057 * Clear LQI Manager Interrupts1
2058 */
2059 register CLRLQIINT1 {
2060 address 0x051
2061 access_mode WO
2062 modes M_DFF0, M_DFF1, M_SCSI
2063 field CLRLQIPHASE_LQ 0x80
2064 field CLRLQIPHASE_NLQ 0x40
2065 field CLRLIQABORT 0x20
2066 field CLRLQICRCI_LQ 0x10
2067 field CLRLQICRCI_NLQ 0x08
2068 field CLRLQIBADLQI 0x04
2069 field CLRLQIOVERI_LQ 0x02
2070 field CLRLQIOVERI_NLQ 0x01
2071 }
2073 /*
2074 * LQI Manager Interrupt Mode 1
2075 */
2076 register LQIMODE1 {
2077 address 0x051
2078 access_mode RW
2079 modes M_CFG
2080 field ENLQIPHASE_LQ 0x80 /* LQIPHASE1 */
2081 field ENLQIPHASE_NLQ 0x40 /* LQIPHASE2 */
2082 field ENLIQABORT 0x20
2083 field ENLQICRCI_LQ 0x10 /* LQICRCI1 */
2084 field ENLQICRCI_NLQ 0x08 /* LQICRCI2 */
2085 field ENLQIBADLQI 0x04
2086 field ENLQIOVERI_LQ 0x02 /* LQIOVERI1 */
2087 field ENLQIOVERI_NLQ 0x01 /* LQIOVERI2 */
2088 }
2090 /*
2091 * LQI Manager Status 2
2092 */
2093 register LQISTAT2 {
2094 address 0x052
2095 access_mode RO
2096 modes M_DFF0, M_DFF1, M_SCSI
2097 field PACKETIZED 0x80
2098 field LQIPHASE_OUTPKT 0x40
2099 field LQIWORKONLQ 0x20
2100 field LQIWAITFIFO 0x10
2101 field LQISTOPPKT 0x08
2102 field LQISTOPLQ 0x04
2103 field LQISTOPCMD 0x02
2104 field LQIGSAVAIL 0x01
2105 }
2107 /*
2108 * SCSI Status 3
2109 */
2110 register SSTAT3 {
2111 address 0x053
2112 access_mode RO
2113 modes M_DFF0, M_DFF1, M_SCSI
2114 field NTRAMPERR 0x02
2115 field OSRAMPERR 0x01
2116 }
2118 /*
2119 * Clear SCSI Status 3
2120 */
2121 register CLRSINT3 {
2122 address 0x053
2123 access_mode WO
2124 modes M_DFF0, M_DFF1, M_SCSI
2125 field CLRNTRAMPERR 0x02
2126 field CLROSRAMPERR 0x01
2127 }
2129 /*
2130 * SCSI Interrupt Mode 3
2131 */
2132 register SIMODE3 {
2133 address 0x053
2134 access_mode RW
2135 modes M_CFG
2136 field ENNTRAMPERR 0x02
2137 field ENOSRAMPERR 0x01
2138 }
2140 /*
2141 * LQO Manager Status 0
2142 */
2143 register LQOSTAT0 {
2144 address 0x054
2145 access_mode RO
2146 modes M_DFF0, M_DFF1, M_SCSI
2147 field LQOTARGSCBPERR 0x10
2148 field LQOSTOPT2 0x08
2149 field LQOATNLQ 0x04
2150 field LQOATNPKT 0x02
2151 field LQOTCRC 0x01
2152 }
2154 /*
2155 * Clear LQO Manager interrupt 0
2156 */
2157 register CLRLQOINT0 {
2158 address 0x054
2159 access_mode WO
2160 modes M_DFF0, M_DFF1, M_SCSI
2161 field CLRLQOTARGSCBPERR 0x10
2162 field CLRLQOSTOPT2 0x08
2163 field CLRLQOATNLQ 0x04
2164 field CLRLQOATNPKT 0x02
2165 field CLRLQOTCRC 0x01
2166 }
2168 /*
2169 * LQO Manager Interrupt Mode 0
2170 */
2171 register LQOMODE0 {
2172 address 0x054
2173 access_mode RW
2174 modes M_CFG
2175 field ENLQOTARGSCBPERR 0x10
2176 field ENLQOSTOPT2 0x08
2177 field ENLQOATNLQ 0x04
2178 field ENLQOATNPKT 0x02
2179 field ENLQOTCRC 0x01
2180 }
2182 /*
2183 * LQO Manager Status 1
2184 */
2185 register LQOSTAT1 {
2186 address 0x055
2187 access_mode RO
2188 modes M_DFF0, M_DFF1, M_SCSI
2189 field LQOINITSCBPERR 0x10
2190 field LQOSTOPI2 0x08
2191 field LQOBADQAS 0x04
2192 field LQOBUSFREE 0x02
2193 field LQOPHACHGINPKT 0x01
2194 }
2196 /*
2197 * Clear LOQ Interrupt 1
2198 */
2199 register CLRLQOINT1 {
2200 address 0x055
2201 access_mode WO
2202 modes M_DFF0, M_DFF1, M_SCSI
2203 field CLRLQOINITSCBPERR 0x10
2204 field CLRLQOSTOPI2 0x08
2205 field CLRLQOBADQAS 0x04
2206 field CLRLQOBUSFREE 0x02
2207 field CLRLQOPHACHGINPKT 0x01
2208 }
2210 /*
2211 * LQO Manager Interrupt Mode 1
2212 */
2213 register LQOMODE1 {
2214 address 0x055
2215 access_mode RW
2216 modes M_CFG
2217 field ENLQOINITSCBPERR 0x10
2218 field ENLQOSTOPI2 0x08
2219 field ENLQOBADQAS 0x04
2220 field ENLQOBUSFREE 0x02
2221 field ENLQOPHACHGINPKT 0x01
2222 }
2224 /*
2225 * LQO Manager Status 2
2226 */
2227 register LQOSTAT2 {
2228 address 0x056
2229 access_mode RO
2230 modes M_DFF0, M_DFF1, M_SCSI
2231 field LQOPKT 0xE0
2232 field LQOWAITFIFO 0x10
2233 field LQOPHACHGOUTPKT 0x02 /* outside of packet boundaries. */
2234 field LQOSTOP0 0x01 /* Stopped after sending all packets */
2235 }
2237 /*
2238 * Output Synchronizer Space Count
2239 */
2240 register OS_SPACE_CNT {
2241 address 0x056
2242 access_mode RO
2243 modes M_CFG
2244 }
2246 /*
2247 * SCSI Interrupt Mode 1
2248 * Setting any bit will enable the corresponding function
2249 * in SIMODE1 to interrupt via the IRQ pin.
2250 */
2251 register SIMODE1 {
2252 address 0x057
2253 access_mode RW
2254 modes M_DFF0, M_DFF1, M_SCSI
2255 field ENSELTIMO 0x80
2256 field ENATNTARG 0x40
2257 field ENSCSIRST 0x20
2258 field ENPHASEMIS 0x10
2259 field ENBUSFREE 0x08
2260 field ENSCSIPERR 0x04
2261 field ENSTRB2FAST 0x02
2262 field ENREQINIT 0x01
2263 }
2265 /*
2266 * Good Status FIFO
2267 */
2268 register GSFIFO {
2269 address 0x058
2270 access_mode RO
2271 size 2
2272 modes M_DFF0, M_DFF1, M_SCSI
2273 }
2275 /*
2276 * Data FIFO SCSI Transfer Control
2277 */
2278 register DFFSXFRCTL {
2279 address 0x05A
2280 access_mode RW
2281 modes M_DFF0, M_DFF1
2282 field DFFBITBUCKET 0x08
2283 field CLRSHCNT 0x04
2284 field CLRCHN 0x02
2285 field RSTCHN 0x01
2286 }
2288 /*
2289 * Next SCSI Control Block
2290 */
2291 register NEXTSCB {
2292 address 0x05A
2293 access_mode RW
2294 size 2
2295 modes M_SCSI
2296 }
2298 /* Rev B only. */
2299 register LQOSCSCTL {
2300 address 0x05A
2301 access_mode RW
2302 size 1
2303 modes M_CFG
2304 field LQOH2A_VERSION 0x80
2305 field LQONOCHKOVER 0x01
2306 }
2308 /*
2309 * SEQ Interrupts
2310 */
2311 register SEQINTSRC {
2312 address 0x05B
2313 access_mode RO
2314 modes M_DFF0, M_DFF1
2315 field CTXTDONE 0x40
2316 field SAVEPTRS 0x20
2317 field CFG4DATA 0x10
2318 field CFG4ISTAT 0x08
2319 field CFG4TSTAT 0x04
2320 field CFG4ICMD 0x02
2321 field CFG4TCMD 0x01
2322 }
2324 /*
2325 * Clear Arp Interrupts
2326 */
2327 register CLRSEQINTSRC {
2328 address 0x05B
2329 access_mode WO
2330 modes M_DFF0, M_DFF1
2331 field CLRCTXTDONE 0x40
2332 field CLRSAVEPTRS 0x20
2333 field CLRCFG4DATA 0x10
2334 field CLRCFG4ISTAT 0x08
2335 field CLRCFG4TSTAT 0x04
2336 field CLRCFG4ICMD 0x02
2337 field CLRCFG4TCMD 0x01
2338 }
2340 /*
2341 * SEQ Interrupt Enabled (Shared)
2342 */
2343 register SEQIMODE {
2344 address 0x05C
2345 access_mode RW
2346 modes M_DFF0, M_DFF1
2347 field ENCTXTDONE 0x40
2348 field ENSAVEPTRS 0x20
2349 field ENCFG4DATA 0x10
2350 field ENCFG4ISTAT 0x08
2351 field ENCFG4TSTAT 0x04
2352 field ENCFG4ICMD 0x02
2353 field ENCFG4TCMD 0x01
2354 }
2356 /*
2357 * Current SCSI Control Block
2358 */
2359 register CURRSCB {
2360 address 0x05C
2361 access_mode RW
2362 size 2
2363 modes M_SCSI
2364 }
2366 /*
2367 * Data FIFO Status
2368 */
2369 register MDFFSTAT {
2370 address 0x05D
2371 access_mode RO
2372 modes M_DFF0, M_DFF1
2373 field SHCNTNEGATIVE 0x40 /* Rev B or higher */
2374 field SHCNTMINUS1 0x20 /* Rev B or higher */
2375 field LASTSDONE 0x10
2376 field SHVALID 0x08
2377 field DLZERO 0x04 /* FIFO data ends on packet boundary. */
2378 field DATAINFIFO 0x02
2379 field FIFOFREE 0x01
2380 }
2382 /*
2383 * CRC Control
2384 */
2385 register CRCCONTROL {
2386 address 0x05d
2387 access_mode RW
2388 modes M_CFG
2389 field CRCVALCHKEN 0x40
2390 }
2392 /*
2393 * SCSI Test Control
2394 */
2395 register SCSITEST {
2396 address 0x05E
2397 access_mode RW
2398 modes M_CFG
2399 field CNTRTEST 0x08
2400 field SEL_TXPLL_DEBUG 0x04
2401 }
2403 /*
2404 * Data FIFO Queue Tag
2405 */
2406 register DFFTAG {
2407 address 0x05E
2408 access_mode RW
2409 size 2
2410 modes M_DFF0, M_DFF1
2411 }
2413 /*
2414 * Last SCSI Control Block
2415 */
2416 register LASTSCB {
2417 address 0x05E
2418 access_mode RW
2419 size 2
2420 modes M_SCSI
2421 }
2423 /*
2424 * SCSI I/O Cell Power-down Control
2425 */
2426 register IOPDNCTL {
2427 address 0x05F
2428 access_mode RW
2429 modes M_CFG
2430 field DISABLE_OE 0x80
2431 field PDN_IDIST 0x04
2432 field PDN_DIFFSENSE 0x01
2433 }
2435 /*
2436 * Shaddow Host Address.
2437 */
2438 register SHADDR {
2439 address 0x060
2440 access_mode RO
2441 size 8
2442 modes M_DFF0, M_DFF1
2443 }
2445 /*
2446 * Data Group CRC Interval.
2447 */
2448 register DGRPCRCI {
2449 address 0x060
2450 access_mode RW
2451 size 2
2452 modes M_CFG
2453 }
2455 /*
2456 * Data Transfer Negotiation Address
2457 */
2458 register NEGOADDR {
2459 address 0x060
2460 access_mode RW
2461 modes M_SCSI
2462 }
2464 /*
2465 * Data Transfer Negotiation Data - Period Byte
2466 */
2467 register NEGPERIOD {
2468 address 0x061
2469 access_mode RW
2470 modes M_SCSI
2471 }
2473 /*
2474 * Packetized CRC Interval
2475 */
2476 register PACKCRCI {
2477 address 0x062
2478 access_mode RW
2479 size 2
2480 modes M_CFG
2481 }
2483 /*
2484 * Data Transfer Negotiation Data - Offset Byte
2485 */
2486 register NEGOFFSET {
2487 address 0x062
2488 access_mode RW
2489 modes M_SCSI
2490 }
2492 /*
2493 * Data Transfer Negotiation Data - PPR Options
2494 */
2495 register NEGPPROPTS {
2496 address 0x063
2497 access_mode RW
2498 modes M_SCSI
2499 field PPROPT_PACE 0x08
2500 field PPROPT_QAS 0x04
2501 field PPROPT_DT 0x02
2502 field PPROPT_IUT 0x01
2503 }
2505 /*
2506 * Data Transfer Negotiation Data - Connection Options
2507 */
2508 register NEGCONOPTS {
2509 address 0x064
2510 access_mode RW
2511 modes M_SCSI
2512 field ENSNAPSHOT 0x40
2513 field RTI_WRTDIS 0x20
2514 field RTI_OVRDTRN 0x10
2515 field ENSLOWCRC 0x08
2516 field ENAUTOATNI 0x04
2517 field ENAUTOATNO 0x02
2518 field WIDEXFER 0x01
2519 }
2521 /*
2522 * Negotiation Table Annex Column Index.
2523 */
2524 register ANNEXCOL {
2525 address 0x065
2526 access_mode RW
2527 modes M_SCSI
2528 }
2530 register SCSCHKN {
2531 address 0x066
2532 access_mode RW
2533 modes M_CFG
2534 field STSELSKIDDIS 0x40
2535 field CURRFIFODEF 0x20
2536 field WIDERESEN 0x10
2537 field SDONEMSKDIS 0x08
2538 field DFFACTCLR 0x04
2539 field SHVALIDSTDIS 0x02
2540 field LSTSGCLRDIS 0x01
2541 }
2543 const AHD_ANNEXCOL_PER_DEV0 4
2544 const AHD_NUM_PER_DEV_ANNEXCOLS 4
2545 const AHD_ANNEXCOL_PRECOMP_SLEW 4
2546 const AHD_PRECOMP_MASK 0x07
2547 const AHD_PRECOMP_SHIFT 0
2548 const AHD_PRECOMP_CUTBACK_17 0x04
2549 const AHD_PRECOMP_CUTBACK_29 0x06
2550 const AHD_PRECOMP_CUTBACK_37 0x07
2551 const AHD_SLEWRATE_MASK 0x78
2552 const AHD_SLEWRATE_SHIFT 3
2553 /*
2554 * Rev A has only a single bit (high bit of field) of slew adjustment.
2555 * Rev B has 4 bits. The current default happens to be the same for both.
2556 */
2557 const AHD_SLEWRATE_DEF_REVA 0x08
2558 const AHD_SLEWRATE_DEF_REVB 0x08
2560 /* Rev A does not have any amplitude setting. */
2561 const AHD_ANNEXCOL_AMPLITUDE 6
2562 const AHD_AMPLITUDE_MASK 0x7
2563 const AHD_AMPLITUDE_SHIFT 0
2564 const AHD_AMPLITUDE_DEF 0x7
2566 /*
2567 * Negotiation Table Annex Data Port.
2568 */
2569 register ANNEXDAT {
2570 address 0x066
2571 access_mode RW
2572 modes M_SCSI
2573 }
2575 /*
2576 * Initiator's Own Id.
2577 * The SCSI ID to use for Selection Out and seen during a reselection..
2578 */
2579 register IOWNID {
2580 address 0x067
2581 access_mode RW
2582 modes M_SCSI
2583 }
2585 /*
2586 * 960MHz Phase-Locked Loop Control 0
2587 */
2588 register PLL960CTL0 {
2589 address 0x068
2590 access_mode RW
2591 modes M_CFG
2592 field PLL_VCOSEL 0x80
2593 field PLL_PWDN 0x40
2594 field PLL_NS 0x30
2595 field PLL_ENLUD 0x08
2596 field PLL_ENLPF 0x04
2597 field PLL_DLPF 0x02
2598 field PLL_ENFBM 0x01
2599 }
2601 /*
2602 * Target Own Id
2603 */
2604 register TOWNID {
2605 address 0x069
2606 access_mode RW
2607 modes M_SCSI
2608 }
2610 /*
2611 * 960MHz Phase-Locked Loop Control 1
2612 */
2613 register PLL960CTL1 {
2614 address 0x069
2615 access_mode RW
2616 modes M_CFG
2617 field PLL_CNTEN 0x80
2618 field PLL_CNTCLR 0x40
2619 field PLL_RST 0x01
2620 }
2622 /*
2623 * Expander Signature
2624 */
2625 register XSIG {
2626 address 0x06A
2627 access_mode RW
2628 modes M_SCSI
2629 }
2631 /*
2632 * Shadow Byte Count
2633 */
2634 register SHCNT {
2635 address 0x068
2636 access_mode RW
2637 size 3
2638 modes M_DFF0, M_DFF1
2639 }
2641 /*
2642 * Selection Out ID
2643 */
2644 register SELOID {
2645 address 0x06B
2646 access_mode RW
2647 modes M_SCSI
2648 }
2650 /*
2651 * 960-MHz Phase-Locked Loop Test Count
2652 */
2653 register PLL960CNT0 {
2654 address 0x06A
2655 access_mode RO
2656 size 2
2657 modes M_CFG
2658 }
2660 /*
2661 * 400-MHz Phase-Locked Loop Control 0
2662 */
2663 register PLL400CTL0 {
2664 address 0x06C
2665 access_mode RW
2666 modes M_CFG
2667 field PLL_VCOSEL 0x80
2668 field PLL_PWDN 0x40
2669 field PLL_NS 0x30
2670 field PLL_ENLUD 0x08
2671 field PLL_ENLPF 0x04
2672 field PLL_DLPF 0x02
2673 field PLL_ENFBM 0x01
2674 }
2676 /*
2677 * Arbitration Fairness
2678 */
2679 register FAIRNESS {
2680 address 0x06C
2681 access_mode RW
2682 size 2
2683 modes M_SCSI
2684 }
2686 /*
2687 * 400-MHz Phase-Locked Loop Control 1
2688 */
2689 register PLL400CTL1 {
2690 address 0x06D
2691 access_mode RW
2692 modes M_CFG
2693 field PLL_CNTEN 0x80
2694 field PLL_CNTCLR 0x40
2695 field PLL_RST 0x01
2696 }
2698 /*
2699 * Arbitration Unfairness
2700 */
2701 register UNFAIRNESS {
2702 address 0x06E
2703 access_mode RW
2704 size 2
2705 modes M_SCSI
2706 }
2708 /*
2709 * 400-MHz Phase-Locked Loop Test Count
2710 */
2711 register PLL400CNT0 {
2712 address 0x06E
2713 access_mode RO
2714 size 2
2715 modes M_CFG
2716 }
2718 /*
2719 * SCB Page Pointer
2720 */
2721 register SCBPTR {
2722 address 0x0A8
2723 access_mode RW
2724 size 2
2725 modes M_DFF0, M_DFF1, M_CCHAN, M_SCSI
2726 }
2728 /*
2729 * CMC SCB Array Count
2730 * Number of bytes to transfer between CMC SCB memory and SCBRAM.
2731 * Transfers must be 8byte aligned and sized.
2732 */
2733 register CCSCBACNT {
2734 address 0x0AB
2735 access_mode RW
2736 modes M_CCHAN
2737 }
2739 /*
2740 * SCB Autopointer
2741 * SCB-Next Address Snooping logic. When an SCB is transferred to
2742 * the card, the next SCB address to be used by the CMC array can
2743 * be autoloaded from that transfer.
2744 */
2745 register SCBAUTOPTR {
2746 address 0x0AB
2747 access_mode RW
2748 modes M_CFG
2749 field AUSCBPTR_EN 0x80
2750 field SCBPTR_ADDR 0x38
2751 field SCBPTR_OFF 0x07
2752 }
2754 /*
2755 * CMC SG Ram Address Pointer
2756 */
2757 register CCSGADDR {
2758 address 0x0AC
2759 access_mode RW
2760 modes M_DFF0, M_DFF1
2761 }
2763 /*
2764 * CMC SCB RAM Address Pointer
2765 */
2766 register CCSCBADDR {
2767 address 0x0AC
2768 access_mode RW
2769 modes M_CCHAN
2770 }
2772 /*
2773 * CMC SCB Ram Back-up Address Pointer
2774 * Indicates the true stop location of transfers halted prior
2775 * to SCBHCNT going to 0.
2776 */
2777 register CCSCBADR_BK {
2778 address 0x0AC
2779 access_mode RO
2780 modes M_CFG
2781 }
2783 /*
2784 * CMC SG Control
2785 */
2786 register CCSGCTL {
2787 address 0x0AD
2788 access_mode RW
2789 modes M_DFF0, M_DFF1
2790 field CCSGDONE 0x80
2791 field SG_CACHE_AVAIL 0x10
2792 field CCSGENACK 0x08
2793 mask CCSGEN 0x0C
2794 field SG_FETCH_REQ 0x02
2795 field CCSGRESET 0x01
2796 }
2798 /*
2799 * CMD SCB Control
2800 */
2801 register CCSCBCTL {
2802 address 0x0AD
2803 access_mode RW
2804 modes M_CCHAN
2805 field CCSCBDONE 0x80
2806 field ARRDONE 0x40
2807 field CCARREN 0x10
2808 field CCSCBEN 0x08
2809 field CCSCBDIR 0x04
2810 field CCSCBRESET 0x01
2811 }
2813 /*
2814 * CMC Ram BIST
2815 */
2816 register CMC_RAMBIST {
2817 address 0x0AD
2818 access_mode RW
2819 modes M_CFG
2820 field SG_ELEMENT_SIZE 0x80
2821 field SCBRAMBIST_FAIL 0x40
2822 field SG_BIST_FAIL 0x20
2823 field SG_BIST_EN 0x10
2824 field CMC_BUFFER_BIST_FAIL 0x02
2825 field CMC_BUFFER_BIST_EN 0x01
2826 }
2828 /*
2829 * CMC SG RAM Data Port
2830 */
2831 register CCSGRAM {
2832 address 0x0B0
2833 access_mode RW
2834 modes M_DFF0, M_DFF1
2835 }
2837 /*
2838 * CMC SCB RAM Data Port
2839 */
2840 register CCSCBRAM {
2841 address 0x0B0
2842 access_mode RW
2843 modes M_CCHAN
2844 }
2846 /*
2847 * Flex DMA Address.
2848 */
2849 register FLEXADR {
2850 address 0x0B0
2851 access_mode RW
2852 size 3
2853 modes M_SCSI
2854 }
2856 /*
2857 * Flex DMA Byte Count
2858 */
2859 register FLEXCNT {
2860 address 0x0B3
2861 access_mode RW
2862 size 2
2863 modes M_SCSI
2864 }
2866 /*
2867 * Flex DMA Status
2868 */
2869 register FLEXDMASTAT {
2870 address 0x0B5
2871 access_mode RW
2872 modes M_SCSI
2873 field FLEXDMAERR 0x02
2874 field FLEXDMADONE 0x01
2875 }
2877 /*
2878 * Flex DMA Data Port
2879 */
2880 register FLEXDATA {
2881 address 0x0B6
2882 access_mode RW
2883 modes M_SCSI
2884 }
2886 /*
2887 * Board Data
2888 */
2889 register BRDDAT {
2890 address 0x0B8
2891 access_mode RW
2892 modes M_SCSI
2893 }
2895 /*
2896 * Board Control
2897 */
2898 register BRDCTL {
2899 address 0x0B9
2900 access_mode RW
2901 modes M_SCSI
2902 field FLXARBACK 0x80
2903 field FLXARBREQ 0x40
2904 field BRDADDR 0x38
2905 field BRDEN 0x04
2906 field BRDRW 0x02
2907 field BRDSTB 0x01
2908 }
2910 /*
2911 * Serial EEPROM Address
2912 */
2913 register SEEADR {
2914 address 0x0BA
2915 access_mode RW
2916 modes M_SCSI
2917 }
2919 /*
2920 * Serial EEPROM Data
2921 */
2922 register SEEDAT {
2923 address 0x0BC
2924 access_mode RW
2925 size 2
2926 modes M_SCSI
2927 }
2929 /*
2930 * Serial EEPROM Status
2931 */
2932 register SEESTAT {
2933 address 0x0BE
2934 access_mode RO
2935 modes M_SCSI
2936 field INIT_DONE 0x80
2937 field SEEOPCODE 0x70
2938 field LDALTID_L 0x08
2939 field SEEARBACK 0x04
2940 field SEEBUSY 0x02
2941 field SEESTART 0x01
2942 }
2944 /*
2945 * Serial EEPROM Control
2946 */
2947 register SEECTL {
2948 address 0x0BE
2949 access_mode RW
2950 modes M_SCSI
2951 field SEEOPCODE 0x70 {
2952 SEEOP_ERASE 0x70,
2953 SEEOP_READ 0x60,
2954 SEEOP_WRITE 0x50,
2955 /*
2956 * The following four commands use special
2957 * addresses for differentiation.
2958 */
2959 SEEOP_ERAL 0x40
2960 }
2961 mask SEEOP_EWEN 0x40
2962 mask SEEOP_WALL 0x40
2963 mask SEEOP_EWDS 0x40
2964 field SEERST 0x02
2965 field SEESTART 0x01
2966 }
2968 const SEEOP_ERAL_ADDR 0x80
2969 const SEEOP_EWEN_ADDR 0xC0
2970 const SEEOP_WRAL_ADDR 0x40
2971 const SEEOP_EWDS_ADDR 0x00
2973 /*
2974 * SCB Counter
2975 */
2976 register SCBCNT {
2977 address 0x0BF
2978 access_mode RW
2979 modes M_SCSI
2980 }
2982 /*
2983 * Data FIFO Write Address
2984 * Pointer to the next QWD location to be written to the data FIFO.
2985 */
2986 register DFWADDR {
2987 address 0x0C0
2988 access_mode RW
2989 size 2
2990 modes M_DFF0, M_DFF1
2991 }
2993 /*
2994 * DSP Filter Control
2995 */
2996 register DSPFLTRCTL {
2997 address 0x0C0
2998 access_mode RW
2999 modes M_CFG
3000 field FLTRDISABLE 0x20
3001 field EDGESENSE 0x10
3002 field DSPFCNTSEL 0x0F
3003 }
3005 /*
3006 * DSP Data Channel Control
3007 */
3008 register DSPDATACTL {
3009 address 0x0C1
3010 access_mode RW
3011 modes M_CFG
3012 field BYPASSENAB 0x80
3013 field DESQDIS 0x10
3014 field RCVROFFSTDIS 0x04
3015 field XMITOFFSTDIS 0x02
3016 }
3018 /*
3019 * Data FIFO Read Address
3020 * Pointer to the next QWD location to be read from the data FIFO.
3021 */
3022 register DFRADDR {
3023 address 0x0C2
3024 access_mode RW
3025 size 2
3026 modes M_DFF0, M_DFF1
3027 }
3029 /*
3030 * DSP REQ Control
3031 */
3032 register DSPREQCTL {
3033 address 0x0C2
3034 access_mode RW
3035 modes M_CFG
3036 field MANREQCTL 0xC0
3037 field MANREQDLY 0x3F
3038 }
3040 /*
3041 * DSP ACK Control
3042 */
3043 register DSPACKCTL {
3044 address 0x0C3
3045 access_mode RW
3046 modes M_CFG
3047 field MANACKCTL 0xC0
3048 field MANACKDLY 0x3F
3049 }
3051 /*
3052 * Data FIFO Data
3053 * Read/Write byte port into the data FIFO. The read and write
3054 * FIFO pointers increment with each read and write respectively
3055 * to this port.
3056 */
3057 register DFDAT {
3058 address 0x0C4
3059 access_mode RW
3060 modes M_DFF0, M_DFF1
3061 }
3063 /*
3064 * DSP Channel Select
3065 */
3066 register DSPSELECT {
3067 address 0x0C4
3068 access_mode RW
3069 modes M_CFG
3070 field AUTOINCEN 0x80
3071 field DSPSEL 0x1F
3072 }
3074 const NUMDSPS 0x14
3076 /*
3077 * Write Bias Control
3078 */
3079 register WRTBIASCTL {
3080 address 0x0C5
3081 access_mode WO
3082 modes M_CFG
3083 field AUTOXBCDIS 0x80
3084 field XMITMANVAL 0x3F
3085 }
3087 /*
3088 * Currently the WRTBIASCTL is the same as the default.
3089 */
3090 const WRTBIASCTL_HP_DEFAULT 0x0
3092 /*
3093 * Receiver Bias Control
3094 */
3095 register RCVRBIOSCTL {
3096 address 0x0C6
3097 access_mode WO
3098 modes M_CFG
3099 field AUTORBCDIS 0x80
3100 field RCVRMANVAL 0x3F
3101 }
3103 /*
3104 * Write Bias Calculator
3105 */
3106 register WRTBIASCALC {
3107 address 0x0C7
3108 access_mode RO
3109 modes M_CFG
3110 }
3112 /*
3113 * Data FIFO Pointers
3114 * Contains the byte offset from DFWADDR and DWRADDR to the current
3115 * FIFO write/read locations.
3116 */
3117 register DFPTRS {
3118 address 0x0C8
3119 access_mode RW
3120 modes M_DFF0, M_DFF1
3121 }
3123 /*
3124 * Receiver Bias Calculator
3125 */
3126 register RCVRBIASCALC {
3127 address 0x0C8
3128 access_mode RO
3129 modes M_CFG
3130 }
3132 /*
3133 * Data FIFO Backup Read Pointer
3134 * Contains the data FIFO address to be restored if the last
3135 * data accessed from the data FIFO was not transferred successfully.
3136 */
3137 register DFBKPTR {
3138 address 0x0C9
3139 access_mode RW
3140 size 2
3141 modes M_DFF0, M_DFF1
3142 }
3144 /*
3145 * Skew Calculator
3146 */
3147 register SKEWCALC {
3148 address 0x0C9
3149 access_mode RO
3150 modes M_CFG
3151 }
3153 /*
3154 * Data FIFO Debug Control
3155 */
3156 register DFDBCTL {
3157 address 0x0CB
3158 access_mode RW
3159 modes M_DFF0, M_DFF1
3160 field DFF_CIO_WR_RDY 0x20
3161 field DFF_CIO_RD_RDY 0x10
3162 field DFF_DIR_ERR 0x08
3163 field DFF_RAMBIST_FAIL 0x04
3164 field DFF_RAMBIST_DONE 0x02
3165 field DFF_RAMBIST_EN 0x01
3166 }
3168 /*
3169 * Data FIFO Space Count
3170 * Number of FIFO locations that are free.
3171 */
3172 register DFSCNT {
3173 address 0x0CC
3174 access_mode RO
3175 size 2
3176 modes M_DFF0, M_DFF1
3177 }
3179 /*
3180 * Data FIFO Byte Count
3181 * Number of filled FIFO locations.
3182 */
3183 register DFBCNT {
3184 address 0x0CE
3185 access_mode RO
3186 size 2
3187 modes M_DFF0, M_DFF1
3188 }
3190 /*
3191 * Sequencer Program Overlay Address.
3192 * Low address must be written prior to high address.
3193 */
3194 register OVLYADDR {
3195 address 0x0D4
3196 modes M_SCSI
3197 size 2
3198 access_mode RW
3199 }
3201 /*
3202 * Sequencer Control 0
3203 * Error detection mode, speed configuration,
3204 * single step, breakpoints and program load.
3205 */
3206 register SEQCTL0 {
3207 address 0x0D6
3208 access_mode RW
3209 field PERRORDIS 0x80
3210 field PAUSEDIS 0x40
3211 field FAILDIS 0x20
3212 field FASTMODE 0x10
3213 field BRKADRINTEN 0x08
3214 field STEP 0x04
3215 field SEQRESET 0x02
3216 field LOADRAM 0x01
3217 }
3219 /*
3220 * Sequencer Control 1
3221 * Instruction RAM Diagnostics
3222 */
3223 register SEQCTL1 {
3224 address 0x0D7
3225 access_mode RW
3226 field OVRLAY_DATA_CHK 0x08
3227 field RAMBIST_DONE 0x04
3228 field RAMBIST_FAIL 0x02
3229 field RAMBIST_EN 0x01
3230 }
3232 /*
3233 * Sequencer Flags
3234 * Zero and Carry state of the ALU.
3235 */
3236 register FLAGS {
3237 address 0x0D8
3238 access_mode RO
3239 field ZERO 0x02
3240 field CARRY 0x01
3241 }
3243 /*
3244 * Sequencer Interrupt Control
3245 */
3246 register SEQINTCTL {
3247 address 0x0D9
3248 access_mode RW
3249 field INTVEC1DSL 0x80
3250 field INT1_CONTEXT 0x20
3251 field SCS_SEQ_INT1M1 0x10
3252 field SCS_SEQ_INT1M0 0x08
3253 field INTMASK2 0x04
3254 field INTMASK1 0x02
3255 field IRET 0x01
3256 }
3258 /*
3259 * Sequencer RAM Data Port
3260 * Single byte window into the Sequencer Instruction Ram area starting
3261 * at the address specified by OVLYADDR. To write a full instruction word,
3262 * simply write four bytes in succession. OVLYADDR will increment after the
3263 * most significant instruction byte (the byte with the parity bit) is written.
3264 */
3265 register SEQRAM {
3266 address 0x0DA
3267 access_mode RW
3268 }
3270 /*
3271 * Sequencer Program Counter
3272 * Low byte must be written prior to high byte.
3273 */
3274 register PRGMCNT {
3275 address 0x0DE
3276 access_mode RW
3277 size 2
3278 }
3280 /*
3281 * Accumulator
3282 */
3283 register ACCUM {
3284 address 0x0E0
3285 access_mode RW
3286 accumulator
3287 }
3289 /*
3290 * Source Index Register
3291 * Incrementing index for reads of SINDIR and the destination (low byte only)
3292 * for any immediate operands passed in jmp, jc, jnc, call instructions.
3293 * Example:
3294 * mvi 0xFF call some_routine;
3295 *
3296 * Will set SINDEX[0] to 0xFF and call the routine "some_routine.
3297 */
3298 register SINDEX {
3299 address 0x0E2
3300 access_mode RW
3301 size 2
3302 sindex
3303 }
3305 /*
3306 * Destination Index Register
3307 * Incrementing index for writes to DINDIR. Can be used as a scratch register.
3308 */
3309 register DINDEX {
3310 address 0x0E4
3311 access_mode RW
3312 size 2
3313 }
3315 /*
3316 * Break Address
3317 * Sequencer instruction breakpoint address address.
3318 */
3319 register BRKADDR0 {
3320 address 0x0E6
3321 access_mode RW
3322 }
3324 register BRKADDR1 {
3325 address 0x0E6
3326 access_mode RW
3327 field BRKDIS 0x80 /* Disable Breakpoint */
3328 }
3330 /*
3331 * All Ones
3332 * All reads to this register return the value 0xFF.
3333 */
3334 register ALLONES {
3335 address 0x0E8
3336 access_mode RO
3337 allones
3338 }
3340 /*
3341 * All Zeros
3342 * All reads to this register return the value 0.
3343 */
3344 register ALLZEROS {
3345 address 0x0EA
3346 access_mode RO
3347 allzeros
3348 }
3350 /*
3351 * No Destination
3352 * Writes to this register have no effect.
3353 */
3354 register NONE {
3355 address 0x0EA
3356 access_mode WO
3357 none
3358 }
3360 /*
3361 * Source Index Indirect
3362 * Reading this register is equivalent to reading (register_base + SINDEX) and
3363 * incrementing SINDEX by 1.
3364 */
3365 register SINDIR {
3366 address 0x0EC
3367 access_mode RO
3368 }
3370 /*
3371 * Destination Index Indirect
3372 * Writing this register is equivalent to writing to (register_base + DINDEX)
3373 * and incrementing DINDEX by 1.
3374 */
3375 register DINDIR {
3376 address 0x0ED
3377 access_mode WO
3378 }
3380 /*
3381 * Function One
3382 * 2's complement to bit value conversion. Write the 2's complement value
3383 * (0-7 only) to the top nibble and retrieve the bit indexed by that value
3384 * on the next read of this register.
3385 * Example:
3386 * Write 0x60
3387 * Read 0x40
3388 */
3389 register FUNCTION1 {
3390 address 0x0F0
3391 access_mode RW
3392 }
3394 /*
3395 * Stack
3396 * Window into the stack. Each stack location is 10 bits wide reported
3397 * low byte followed by high byte. There are 8 stack locations.
3398 */
3399 register STACK {
3400 address 0x0F2
3401 access_mode RW
3402 }
3404 /*
3405 * Interrupt Vector 1 Address
3406 * Interrupt branch address for SCS SEQ_INT1 mode 0 and 1 interrupts.
3407 */
3408 register INTVEC1_ADDR {
3409 address 0x0F4
3410 access_mode RW
3411 size 2
3412 modes M_CFG
3413 }
3415 /*
3416 * Current Address
3417 * Address of the SEQRAM instruction currently executing instruction.
3418 */
3419 register CURADDR {
3420 address 0x0F4
3421 access_mode RW
3422 size 2
3423 modes M_SCSI
3424 }
3426 /*
3427 * Interrupt Vector 2 Address
3428 * Interrupt branch address for HST_SEQ_INT2 interrupts.
3429 */
3430 register INTVEC2_ADDR {
3431 address 0x0F6
3432 access_mode RW
3433 size 2
3434 modes M_CFG
3435 }
3437 /*
3438 * Last Address
3439 * Address of the SEQRAM instruction executed prior to the current instruction.
3440 */
3441 register LASTADDR {
3442 address 0x0F6
3443 access_mode RW
3444 size 2
3445 modes M_SCSI
3446 }
3448 register AHD_PCI_CONFIG_BASE {
3449 address 0x100
3450 access_mode RW
3451 size 256
3452 modes M_CFG
3453 }
3455 /* ---------------------- Scratch RAM Offsets ------------------------- */
3456 scratch_ram {
3457 /* Mode Specific */
3458 address 0x0A0
3459 size 8
3460 modes 0, 1, 2, 3
3461 REG0 {
3462 size 2
3463 }
3464 REG1 {
3465 size 2
3466 }
3467 REG_ISR {
3468 size 2
3469 }
3470 SG_STATE {
3471 size 1
3472 field SEGS_AVAIL 0x01
3473 field LOADING_NEEDED 0x02
3474 field FETCH_INPROG 0x04
3475 }
3476 /*
3477 * Track whether the transfer byte count for
3478 * the current data phase is odd.
3479 */
3480 DATA_COUNT_ODD {
3481 size 1
3482 }
3483 }
3485 scratch_ram {
3486 /* Mode Specific */
3487 address 0x0F8
3488 size 8
3489 modes 0, 1, 2, 3
3490 LONGJMP_ADDR {
3491 size 2
3492 }
3493 ACCUM_SAVE {
3494 size 1
3495 }
3496 }
3499 scratch_ram {
3500 address 0x100
3501 size 128
3502 modes 0, 1, 2, 3
3503 /*
3504 * Per "other-id" execution queues. We use an array of
3505 * tail pointers into lists of SCBs sorted by "other-id".
3506 * The execution head pointer threads the head SCBs for
3507 * each list.
3508 */
3509 WAITING_SCB_TAILS {
3510 size 32
3511 }
3512 WAITING_TID_HEAD {
3513 size 2
3514 }
3515 WAITING_TID_TAIL {
3516 size 2
3517 }
3518 /*
3519 * SCBID of the next SCB in the new SCB queue.
3520 */
3521 NEXT_QUEUED_SCB_ADDR {
3522 size 4
3523 }
3524 /*
3525 * head of list of SCBs that have
3526 * completed but have not been
3527 * put into the qoutfifo.
3528 */
3529 COMPLETE_SCB_HEAD {
3530 size 2
3531 }
3532 /*
3533 * The list of completed SCBs in
3534 * the active DMA.
3535 */
3536 COMPLETE_SCB_DMAINPROG_HEAD {
3537 size 2
3538 }
3539 /*
3540 * head of list of SCBs that have
3541 * completed but need to be uploaded
3542 * to the host prior to being completed.
3543 */
3544 COMPLETE_DMA_SCB_HEAD {
3545 size 2
3546 }
3547 /* Counting semaphore to prevent new select-outs */
3548 QFREEZE_COUNT {
3549 size 2
3550 }
3551 /*
3552 * Mode to restore on legacy idle loop exit.
3553 */
3554 SAVED_MODE {
3555 size 1
3556 }
3557 /*
3558 * Single byte buffer used to designate the type or message
3559 * to send to a target.
3560 */
3561 MSG_OUT {
3562 size 1
3563 }
3564 /* Parameters for DMA Logic */
3565 DMAPARAMS {
3566 size 1
3567 field PRELOADEN 0x80
3568 field WIDEODD 0x40
3569 field SCSIEN 0x20
3570 field SDMAEN 0x10
3571 field SDMAENACK 0x10
3572 field HDMAEN 0x08
3573 field HDMAENACK 0x08
3574 field DIRECTION 0x04 /* Set indicates PCI->SCSI */
3575 field FIFOFLUSH 0x02
3576 field FIFORESET 0x01
3577 }
3578 SEQ_FLAGS {
3579 size 1
3580 field NOT_IDENTIFIED 0x80
3581 field NO_CDB_SENT 0x40
3582 field TARGET_CMD_IS_TAGGED 0x40
3583 field DPHASE 0x20
3584 /* Target flags */
3585 field TARG_CMD_PENDING 0x10
3586 field CMDPHASE_PENDING 0x08
3587 field DPHASE_PENDING 0x04
3588 field SPHASE_PENDING 0x02
3589 field NO_DISCONNECT 0x01
3590 }
3591 /*
3592 * Temporary storage for the
3593 * target/channel/lun of a
3594 * reconnecting target
3595 */
3596 SAVED_SCSIID {
3597 size 1
3598 }
3599 SAVED_LUN {
3600 size 1
3601 }
3602 /*
3603 * The last bus phase as seen by the sequencer.
3604 */
3605 LASTPHASE {
3606 size 1
3607 field CDI 0x80
3608 field IOI 0x40
3609 field MSGI 0x20
3610 field P_BUSFREE 0x01
3611 enum PHASE_MASK CDO|IOO|MSGO {
3612 P_DATAOUT 0x0,
3613 P_DATAIN IOO,
3614 P_DATAOUT_DT P_DATAOUT|MSGO,
3615 P_DATAIN_DT P_DATAIN|MSGO,
3616 P_COMMAND CDO,
3617 P_MESGOUT CDO|MSGO,
3618 P_STATUS CDO|IOO,
3619 P_MESGIN CDO|IOO|MSGO
3620 }
3621 }
3622 /*
3623 * Value to "or" into the SCBPTR[1] value to
3624 * indicate that an entry in the QINFIFO is valid.
3625 */
3626 QOUTFIFO_ENTRY_VALID_TAG {
3627 size 1
3628 }
3629 /*
3630 * Base address of our shared data with the kernel driver in host
3631 * memory. This includes the qoutfifo and target mode
3632 * incoming command queue.
3633 */
3634 SHARED_DATA_ADDR {
3635 size 4
3636 }
3637 /*
3638 * Pointer to location in host memory for next
3639 * position in the qoutfifo.
3640 */
3641 QOUTFIFO_NEXT_ADDR {
3642 size 4
3643 }
3644 /*
3645 * Kernel and sequencer offsets into the queue of
3646 * incoming target mode command descriptors. The
3647 * queue is full when the KERNEL_TQINPOS == TQINPOS.
3648 */
3649 KERNEL_TQINPOS {
3650 size 1
3651 }
3652 TQINPOS {
3653 size 1
3654 }
3655 ARG_1 {
3656 size 1
3657 mask SEND_MSG 0x80
3658 mask SEND_SENSE 0x40
3659 mask SEND_REJ 0x20
3660 mask MSGOUT_PHASEMIS 0x10
3661 mask EXIT_MSG_LOOP 0x08
3662 mask CONT_MSG_LOOP_WRITE 0x04
3663 mask CONT_MSG_LOOP_READ 0x03
3664 mask CONT_MSG_LOOP_TARG 0x02
3665 alias RETURN_1
3666 }
3667 ARG_2 {
3668 size 1
3669 alias RETURN_2
3670 }
3672 /*
3673 * Snapshot of MSG_OUT taken after each message is sent.
3674 */
3675 LAST_MSG {
3676 size 1
3677 }
3679 /*
3680 * Sequences the kernel driver has okayed for us. This allows
3681 * the driver to do things like prevent initiator or target
3682 * operations.
3683 */
3684 SCSISEQ_TEMPLATE {
3685 size 1
3686 field MANUALCTL 0x40
3687 field ENSELI 0x20
3688 field ENRSELI 0x10
3689 field MANUALP 0x0C
3690 field ENAUTOATNP 0x02
3691 field ALTSTIM 0x01
3692 }
3694 /*
3695 * The initiator specified tag for this target mode transaction.
3696 */
3697 INITIATOR_TAG {
3698 size 1
3699 }
3701 SEQ_FLAGS2 {
3702 size 1
3703 field TARGET_MSG_PENDING 0x02
3704 field SELECTOUT_QFROZEN 0x04
3705 }
3707 ALLOCFIFO_SCBPTR {
3708 size 2
3709 }
3711 /*
3712 * The maximum amount of time to wait, when interrupt coalescing
3713 * is enabled, before issueing a CMDCMPLT interrupt for a completed
3714 * command.
3715 */
3716 INT_COALESCING_TIMER {
3717 size 2
3718 }
3720 /*
3721 * The maximum number of commands to coalesce into a single interrupt.
3722 * Actually the 2's complement of that value to simplify sequencer
3723 * code.
3724 */
3725 INT_COALESCING_MAXCMDS {
3726 size 1
3727 }
3729 /*
3730 * The minimum number of commands still outstanding required
3731 * to continue coalescing (2's complement of value).
3732 */
3733 INT_COALESCING_MINCMDS {
3734 size 1
3735 }
3737 /*
3738 * Number of commands "in-flight".
3739 */
3740 CMDS_PENDING {
3741 size 2
3742 }
3744 /*
3745 * The count of commands that have been coalesced.
3746 */
3747 INT_COALESCING_CMDCOUNT {
3748 size 1
3749 }
3751 /*
3752 * Since the HS_MAIBOX is self clearing, copy its contents to
3753 * this position in scratch ram every time it changes.
3754 */
3755 LOCAL_HS_MAILBOX {
3756 size 1
3757 }
3758 /*
3759 * Target-mode CDB type to CDB length table used
3760 * in non-packetized operation.
3761 */
3762 CMDSIZE_TABLE {
3763 size 8
3764 }
3765 }
3767 /************************* Hardware SCB Definition ****************************/
3768 scb {
3769 address 0x180
3770 size 64
3771 modes 0, 1, 2, 3
3772 SCB_RESIDUAL_DATACNT {
3773 size 4
3774 alias SCB_CDB_STORE
3775 alias SCB_HOST_CDB_PTR
3776 }
3777 SCB_RESIDUAL_SGPTR {
3778 size 4
3779 field SG_ADDR_MASK 0xf8 /* In the last byte */
3780 field SG_OVERRUN_RESID 0x02 /* In the first byte */
3781 field SG_LIST_NULL 0x01 /* In the first byte */
3782 }
3783 SCB_SCSI_STATUS {
3784 size 1
3785 alias SCB_HOST_CDB_LEN
3786 }
3787 SCB_TARGET_PHASES {
3788 size 1
3789 }
3790 SCB_TARGET_DATA_DIR {
3791 size 1
3792 }
3793 SCB_TARGET_ITAG {
3794 size 1
3795 }
3796 SCB_SENSE_BUSADDR {
3797 /*
3798 * Only valid if CDB length is less than 13 bytes or
3799 * we are using a CDB pointer. Otherwise contains
3800 * the last 4 bytes of embedded cdb information.
3801 */
3802 size 4
3803 alias SCB_NEXT_COMPLETE
3804 }
3805 SCB_TAG {
3806 alias SCB_FIFO_USE_COUNT
3807 size 2
3808 }
3809 SCB_CONTROL {
3810 size 1
3811 field TARGET_SCB 0x80
3812 field DISCENB 0x40
3813 field TAG_ENB 0x20
3814 field MK_MESSAGE 0x10
3815 field STATUS_RCVD 0x08
3816 field DISCONNECTED 0x04
3817 field SCB_TAG_TYPE 0x03
3818 }
3819 SCB_SCSIID {
3820 size 1
3821 field TID 0xF0
3822 field OID 0x0F
3823 }
3824 SCB_LUN {
3825 size 1
3826 field LID 0xff
3827 }
3828 SCB_TASK_ATTRIBUTE {
3829 size 1
3830 /*
3831 * Overloaded field for non-packetized
3832 * ignore wide residue message handling.
3833 */
3834 field SCB_XFERLEN_ODD 0x01
3835 }
3836 SCB_CDB_LEN {
3837 size 1
3838 field SCB_CDB_LEN_PTR 0x80 /* CDB in host memory */
3839 }
3840 SCB_TASK_MANAGEMENT {
3841 size 1
3842 }
3843 SCB_DATAPTR {
3844 size 8
3845 }
3846 SCB_DATACNT {
3847 /*
3848 * The last byte is really the high address bits for
3849 * the data address.
3850 */
3851 size 4
3852 field SG_LAST_SEG 0x80 /* In the fourth byte */
3853 field SG_HIGH_ADDR_BITS 0x7F /* In the fourth byte */
3854 }
3855 SCB_SGPTR {
3856 size 4
3857 field SG_STATUS_VALID 0x04 /* In the first byte */
3858 field SG_FULL_RESID 0x02 /* In the first byte */
3859 field SG_LIST_NULL 0x01 /* In the first byte */
3860 }
3861 SCB_BUSADDR {
3862 size 4
3863 }
3864 SCB_NEXT {
3865 alias SCB_NEXT_SCB_BUSADDR
3866 size 2
3867 }
3868 SCB_NEXT2 {
3869 size 2
3870 }
3871 SCB_SPARE {
3872 size 8
3873 alias SCB_PKT_LUN
3874 }
3875 SCB_DISCONNECTED_LISTS {
3876 size 8
3877 }
3878 }
3880 /*********************************** Constants ********************************/
3881 const MK_MESSAGE_BIT_OFFSET 4
3882 const TID_SHIFT 4
3883 const TARGET_CMD_CMPLT 0xfe
3884 const INVALID_ADDR 0x80
3885 #define SCB_LIST_NULL 0xff
3886 #define QOUTFIFO_ENTRY_VALID_TOGGLE 0x80
3888 const CCSGADDR_MAX 0x80
3889 const CCSCBADDR_MAX 0x80
3890 const CCSGRAM_MAXSEGS 16
3892 /* Selection Timeout Timer Constants */
3893 const STIMESEL_SHIFT 3
3894 const STIMESEL_MIN 0x18
3895 const STIMESEL_BUG_ADJ 0x8
3897 /* WDTR Message values */
3898 const BUS_8_BIT 0x00
3899 const BUS_16_BIT 0x01
3900 const BUS_32_BIT 0x02
3902 /* Offset maximums */
3903 const MAX_OFFSET 0xfe
3904 const MAX_OFFSET_PACED 0xfe
3905 const MAX_OFFSET_PACED_BUG 0x7f
3906 /*
3907 * Some 160 devices incorrectly accept 0xfe as a
3908 * sync offset, but will overrun this value. Limit
3909 * to 0x7f for speed lower than U320 which will
3910 * avoid the persistent sync offset overruns.
3911 */
3912 const MAX_OFFSET_NON_PACED 0x7f
3913 const HOST_MSG 0xff
3915 /*
3916 * The size of our sense buffers.
3917 * Sense buffer mapping can be handled in either of two ways.
3918 * The first is to allocate a dmamap for each transaction.
3919 * Depending on the architecture, dmamaps can be costly. The
3920 * alternative is to statically map the buffers in much the same
3921 * way we handle our scatter gather lists. The driver implements
3922 * the later.
3923 */
3924 const AHD_SENSE_BUFSIZE 256
3926 /* Target mode command processing constants */
3927 const CMD_GROUP_CODE_SHIFT 0x05
3929 const STATUS_BUSY 0x08
3930 const STATUS_QUEUE_FULL 0x28
3931 const STATUS_PKT_SENSE 0xFF
3932 const TARGET_DATA_IN 1
3934 const SCB_TRANSFER_SIZE_FULL_LUN 56
3935 const SCB_TRANSFER_SIZE_1BYTE_LUN 48
3936 /* PKT_OVERRUN_BUFSIZE must be a multiple of 256 less than 64K */
3937 const PKT_OVERRUN_BUFSIZE 512
3939 /*
3940 * Timer parameters.
3941 */
3942 const AHD_TIMER_US_PER_TICK 25
3943 const AHD_TIMER_MAX_TICKS 0xFFFF
3944 const AHD_TIMER_MAX_US (AHD_TIMER_MAX_TICKS * AHD_TIMER_US_PER_TICK)
3946 /*
3947 * Downloaded (kernel inserted) constants
3948 */
3949 const SG_PREFETCH_CNT download
3950 const SG_PREFETCH_CNT_LIMIT download
3951 const SG_PREFETCH_ALIGN_MASK download
3952 const SG_PREFETCH_ADDR_MASK download
3953 const SG_SIZEOF download
3954 const PKT_OVERRUN_BUFOFFSET download
3955 const SCB_TRANSFER_SIZE download
3957 /*
3958 * BIOS SCB offsets
3959 */
3960 const NVRAM_SCB_OFFSET 0x2C