sys/dev/microcode/i8255x/rcvbundl.h

   1 /*      $NetBSD: rcvbundl.h,v 1.1.14.1 2005/03/04 16:44:05 skrll Exp $  */
   2
   3 /*
   4 Copyright (c) 1999-2001, Intel Corporation
   5
   6 All rights reserved.
   7
   8 Redistribution and use in source and binary forms, with or without
   9 modification, are permitted provided that the following conditions are met:
  10
  11  1. Redistributions of source code must retain the above copyright notice,
  12     this list of conditions and the following disclaimer.
  13
  14  2. Redistributions in binary form must reproduce the above copyright notice,
  15     this list of conditions and the following disclaimer in the documentation
  16     and/or other materials provided with the distribution.
  17
  18  3. Neither the name of Intel Corporation nor the names of its contributors
  19     may be used to endorse or promote products derived from this software
  20     without specific prior written permission.
  21
  22 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
  23 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  24 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  25 DISCLAIMED. IN NO EVENT SHALL CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
  26 INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27 LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
  28 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
  29 LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
  30 NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
  31 EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32 */
  33 /*
  34 rcvbundl.h
  35
  36 Author:  Patrick J Luhmann (PJL)
  37 Date:    05/30/2000
  38 Version: 3.28
  39
  40 This file contains the loadable micro code arrays to implement receive bundling on the
  41 D101 A-step, D101 B-step, D101M (B-step only), D101S, D102 B-step,
  42 D102 B-step with TCO work around and D012 C-step.
  43
  44 Each controller has its own specific micro code array.  The array for one controller
  45 is totally incompatible with any other controller, and if used will most likely
  46 cause the controller to lock up and stop responding to the driver.  Each micro
  47 code array has its own parameter offsets (described below), and they each have
  48 their own version number (which should not be confused with the version of the
  49 rcvbundl.h file given above).
  50
  51 */
  52
  53 /*  Size of loadable micro code image for each supported chip.  */
  54 #ifndef D100_NUM_MICROCODE_DWORDS
  55 #define     D100_NUM_MICROCODE_DWORDS    66
  56 #endif
  57 #ifndef D101_NUM_MICROCODE_DWORDS
  58 #define     D101_NUM_MICROCODE_DWORDS    102
  59 #endif
  60 #ifndef D101M_NUM_MICROCODE_DWORDS
  61 #define     D101M_NUM_MICROCODE_DWORDS   134
  62 #endif
  63 #ifndef D101S_NUM_MICROCODE_DWORDS
  64 #define     D101S_NUM_MICROCODE_DWORDS   134
  65 #endif
  66 #ifndef D102_NUM_MICROCODE_DWORDS
  67 #define     D102_NUM_MICROCODE_DWORDS    134
  68 #endif
  69 #ifndef D102_NUM_TCO_MICROCODE_DWORDS
  70 #define     D102_NUM_TCO_MICROCODE_DWORDS    134
  71 #endif
  72
  73
  74 /*************************************************************************
  75 *  CPUSaver parameters
  76 *
  77 *  All CPUSaver parameters are 16-bit literals that are part of a
  78 *  "move immediate value" instruction.  By changing the value of
  79 *  the literal in the instruction before the code is loaded, the
  80 *  driver can change algorithm.
  81 *
  82 *  CPUSAVER_DWORD - This is the location of the instruction that loads
  83 *    the dead-man timer with its inital value.  By writing a 16-bit
  84 *    value to the low word of this instruction, the driver can change
  85 *    the timer value.  The current default is either x600 or x800;
  86 *    experiments show that the value probably should stay within the
  87 *    range of x200 - x1000.
  88 *
  89 *  CPUSAVER_BUNDLE_MAX_DWORD - This is the location of the instruction
  90 *    that sets the maximum number of frames that will be bundled.  In
  91 *    some situations, such as the TCP windowing algorithm, it may be
  92 *    better to limit the growth of the bundle size than let it go as
  93 *    high as it can, because that could cause too much added latency.
  94 *    The default is six, because this is the number of packets in the
  95 *    default TCP window size.  A value of 1 would make CPUSaver indicate
  96 *    an interrupt for every frame received.  If you do not want to put
  97 *    a limit on the bundle size, set this value to xFFFF.
  98 *
  99 *  CPUSAVER_MIN_SIZE_DWORD - This is the location of the instruction
 100 *    that contains a bit-mask describing the minimum size frame that
 101 *    will be bundled.  The default masks the lower 7 bits, which means
 102 *    that any frame less than 128 bytes in length will not be bundled,
 103 *    but will instead immediately generate an interrupt.  This does
 104 *    not affect the current bundle in any way.  Any frame that is 128
 105 *    bytes or large will be bundled normally.  This feature is meant
 106 *    to provide immediate indication of ACK frames in a TCP environment.
 107 *    Customers were seeing poor performance when a machine with CPUSaver
 108 *    enabled was sending but not receiving.  The delay introduced when
 109 *    the ACKs were received was enough to reduce total throughput, because
 110 *    the sender would sit idle until the ACK was finally seen.
 111 *
 112 *    The current default is 0xFF80, which masks out the lower 7 bits.
 113 *    This means that any frame which is x7F (127) bytes or smaller
 114 *    will cause an immediate interrupt.  Because this value must be a
 115 *    bit mask, there are only a few valid values that can be used.  To
 116 *    turn this feature off, the driver can write the value xFFFF to the
 117 *    lower word of this instruction (in the same way that the other
 118 *    parameters are used).  Likewise, a value of 0xF800 (2047) would
 119 *    cause an interrupt to be generated for every frame, because all
 120 *    standard Ethernet frames are <= 2047 bytes in length.
 121 *************************************************************************/
 122
 123
 124
 125 /********************************************************/
 126 /*  CPUSaver micro code for the D101A                   */
 127 /********************************************************/
 128
 129 /*  Version 2.0  */
 130
 131 /*  This value is the same for both A and B step of 558.  */
 132 #define D101_CPUSAVER_DWORD         72
 133
 134
 135 #define     D101_A_RCVBUNDLE_UCODE \
 136 {\
 137 0x03B301BB, \
 138 0x0046FFFF, \
 139 0xFFFFFFFF, \
 140 0x051DFFFF, \
 141 0xFFFFFFFF, \
 142 0xFFFFFFFF, \
 143 0x000C0001, \
 144 0x00101212, \
 145 0x000C0008, \
 146 0x003801BC, \
 147 0x00000000, \
 148 0x00124818, \
 149 0x000C1000, \
 150 0x00220809, \
 151 0x00010200, \
 152 0x00124818, \
 153 0x000CFFFC, \
 154 0x003803B5, \
 155 0x00000000, \
 156 0x00000000, \
 157 0x00000000, \
 158 0x00000000, \
 159 0x0010009C, \
 160 0x0024B81D, \
 161 0x00130836, \
 162 0x000C0001, \
 163 0x0026081C, \
 164 0x0020C81B, \
 165 0x00130824, \
 166 0x00222819, \
 167 0x00101213, \
 168 0x00041000, \
 169 0x003A03B3, \
 170 0x00010200, \
 171 0x00101B13, \
 172 0x00238081, \
 173 0x00213049, \
 174 0x0038003B, \
 175 0x00000000, \
 176 0x00000000, \
 177 0x00000000, \
 178 0x00000000, \
 179 0x00000000, \
 180 0x00000000, \
 181 0x00000000, \
 182 0x00000000, \
 183 0x00000000, \
 184 0x00000000, \
 185 0x00000000, \
 186 0x00000000, \
 187 0x00000000, \
 188 0x00000000, \
 189 0x00000000, \
 190 0x00000000, \
 191 0x0010009C, \
 192 0x0024B83E, \
 193 0x00130826, \
 194 0x000C0001, \
 195 0x0026083B, \
 196 0x00010200, \
 197 0x00134824, \
 198 0x000C0001, \
 199 0x00101213, \
 200 0x00041000, \
 201 0x0038051E, \
 202 0x00101313, \
 203 0x00010400, \
 204 0x00380521, \
 205 0x00050600, \
 206 0x00100824, \
 207 0x00101310, \
 208 0x00041000, \
 209 0x00080600, \
 210 0x00101B10, \
 211 0x0038051E, \
 212 0x00000000, \
 213 0x00000000, \
 214 0x00000000, \
 215 0x00000000, \
 216 0x00000000, \
 217 0x00000000, \
 218 0x00000000, \
 219 0x00000000, \
 220 0x00000000, \
 221 0x00000000, \
 222 0x00000000, \
 223 0x00000000, \
 224 0x00000000, \
 225 0x00000000, \
 226 0x00000000, \
 227 0x00000000, \
 228 0x00000000, \
 229 0x00000000, \
 230 0x00000000, \
 231 0x00000000, \
 232 0x00000000, \
 233 0x00000000, \
 234 0x00000000, \
 235 0x00000000, \
 236 0x00000000, \
 237 0x00000000, \
 238 0x00000000, \
 239 }
 240
 241
 242 /********************************************************/
 243 /*  CPUSaver micro code for the D101B                   */
 244 /********************************************************/
 245
 246 /*  Version 2.0  */
 247
 248 #define     D101_B0_RCVBUNDLE_UCODE \
 249 {\
 250 0x03B401BC, \
 251 0x0047FFFF, \
 252 0xFFFFFFFF, \
 253 0x051EFFFF, \
 254 0xFFFFFFFF, \
 255 0xFFFFFFFF, \
 256 0x000C0001, \
 257 0x00101B92, \
 258 0x000C0008, \
 259 0x003801BD, \
 260 0x00000000, \
 261 0x00124818, \
 262 0x000C1000, \
 263 0x00220809, \
 264 0x00010200, \
 265 0x00124818, \
 266 0x000CFFFC, \
 267 0x003803B6, \
 268 0x00000000, \
 269 0x00000000, \
 270 0x00000000, \
 271 0x00000000, \
 272 0x0010009C, \
 273 0x0024B81D, \
 274 0x0013082F, \
 275 0x000C0001, \
 276 0x0026081C, \
 277 0x0020C81B, \
 278 0x00130837, \
 279 0x00222819, \
 280 0x00101B93, \
 281 0x00041000, \
 282 0x003A03B4, \
 283 0x00010200, \
 284 0x00101793, \
 285 0x00238082, \
 286 0x0021304A, \
 287 0x0038003C, \
 288 0x00000000, \
 289 0x00000000, \
 290 0x00000000, \
 291 0x00000000, \
 292 0x00000000, \
 293 0x00000000, \
 294 0x00000000, \
 295 0x00000000, \
 296 0x00000000, \
 297 0x00000000, \
 298 0x00000000, \
 299 0x00000000, \
 300 0x00000000, \
 301 0x00000000, \
 302 0x00000000, \
 303 0x00000000, \
 304 0x0010009C, \
 305 0x0024B83E, \
 306 0x00130826, \
 307 0x000C0001, \
 308 0x0026083B, \
 309 0x00010200, \
 310 0x00134837, \
 311 0x000C0001, \
 312 0x00101B93, \
 313 0x00041000, \
 314 0x0038051F, \
 315 0x00101313, \
 316 0x00010400, \
 317 0x00380522, \
 318 0x00050600, \
 319 0x00100837, \
 320 0x00101310, \
 321 0x00041000, \
 322 0x00080600, \
 323 0x00101790, \
 324 0x0038051F, \
 325 0x00000000, \
 326 0x00000000, \
 327 0x00000000, \
 328 0x00000000, \
 329 0x00000000, \
 330 0x00000000, \
 331 0x00000000, \
 332 0x00000000, \
 333 0x00000000, \
 334 0x00000000, \
 335 0x00000000, \
 336 0x00000000, \
 337 0x00000000, \
 338 0x00000000, \
 339 0x00000000, \
 340 0x00000000, \
 341 0x00000000, \
 342 0x00000000, \
 343 0x00000000, \
 344 0x00000000, \
 345 0x00000000, \
 346 0x00000000, \
 347 0x00000000, \
 348 0x00000000, \
 349 0x00000000, \
 350 0x00000000, \
 351 0x00000000, \
 352 }
 353
 354
 355 /********************************************************/
 356 /*  CPUSaver micro code for the D101M (B-step only)     */
 357 /********************************************************/
 358
 359 /*  Version 2.10  */
 360
 361 /*  Parameter values for the D101M B-step  */
 362 #define D101M_CPUSAVER_DWORD                78
 363 #define D101M_CPUSAVER_BUNDLE_MAX_DWORD     65
 364 #define D101M_CPUSAVER_MIN_SIZE_DWORD       126
 365
 366
 367 #define D101M_B_RCVBUNDLE_UCODE \
 368 {\
 369 0x00550215, \
 370 0xFFFF0437, \
 371 0xFFFFFFFF, \
 372 0x06A70789, \
 373 0xFFFFFFFF, \
 374 0x0558FFFF, \
 375 0x000C0001, \
 376 0x00101312, \
 377 0x000C0008, \
 378 0x00380216, \
 379 0x0010009C, \
 380 0x00204056, \
 381 0x002380CC, \
 382 0x00380056, \
 383 0x0010009C, \
 384 0x00244C0B, \
 385 0x00000800, \
 386 0x00124818, \
 387 0x00380438, \
 388 0x00000000, \
 389 0x00140000, \
 390 0x00380555, \
 391 0x00308000, \
 392 0x00100662, \
 393 0x00100561, \
 394 0x000E0408, \
 395 0x00134861, \
 396 0x000C0002, \
 397 0x00103093, \
 398 0x00308000, \
 399 0x00100624, \
 400 0x00100561, \
 401 0x000E0408, \
 402 0x00100861, \
 403 0x000C007E, \
 404 0x00222C21, \
 405 0x000C0002, \
 406 0x00103093, \
 407 0x00380C7A, \
 408 0x00080000, \
 409 0x00103090, \
 410 0x00380C7A, \
 411 0x00000000, \
 412 0x00000000, \
 413 0x00000000, \
 414 0x00000000, \
 415 0x0010009C, \
 416 0x00244C2D, \
 417 0x00010004, \
 418 0x00041000, \
 419 0x003A0437, \
 420 0x00044010, \
 421 0x0038078A, \
 422 0x00000000, \
 423 0x00100099, \
 424 0x00206C7A, \
 425 0x0010009C, \
 426 0x00244C48, \
 427 0x00130824, \
 428 0x000C0001, \
 429 0x00101213, \
 430 0x00260C75, \
 431 0x00041000, \
 432 0x00010004, \
 433 0x00130826, \
 434 0x000C0006, \
 435 0x002206A8, \
 436 0x0013C926, \
 437 0x00101313, \
 438 0x003806A8, \
 439 0x00000000, \
 440 0x00000000, \
 441 0x00000000, \
 442 0x00000000, \
 443 0x00000000, \
 444 0x00000000, \
 445 0x00000000, \
 446 0x00000000, \
 447 0x00080600, \
 448 0x00101B10, \
 449 0x00050004, \
 450 0x00100826, \
 451 0x00101210, \
 452 0x00380C34, \
 453 0x00000000, \
 454 0x00000000, \
 455 0x0021155B, \
 456 0x00100099, \
 457 0x00206559, \
 458 0x0010009C, \
 459 0x00244559, \
 460 0x00130836, \
 461 0x000C0000, \
 462 0x00220C62, \
 463 0x000C0001, \
 464 0x00101B13, \
 465 0x00229C0E, \
 466 0x00210C0E, \
 467 0x00226C0E, \
 468 0x00216C0E, \
 469 0x0022FC0E, \
 470 0x00215C0E, \
 471 0x00214C0E, \
 472 0x00380555, \
 473 0x00010004, \
 474 0x00041000, \
 475 0x00278C67, \
 476 0x00040800, \
 477 0x00018100, \
 478 0x003A0437, \
 479 0x00130826, \
 480 0x000C0001, \
 481 0x00220559, \
 482 0x00101313, \
 483 0x00380559, \
 484 0x00000000, \
 485 0x00000000, \
 486 0x00000000, \
 487 0x00000000, \
 488 0x00000000, \
 489 0x00000000, \
 490 0x00000000, \
 491 0x00000000, \
 492 0x00130831, \
 493 0x0010090B, \
 494 0x00124813, \
 495 0x000CFF80, \
 496 0x002606AB, \
 497 0x00041000, \
 498 0x003806A8, \
 499 0x00000000, \
 500 0x00000000, \
 501 0x00000000, \
 502 0x00000000, \
 503 }
 504
 505
 506 /********************************************************/
 507 /*  CPUSaver micro code for the D101S                   */
 508 /********************************************************/
 509
 510 /*  Version 1.20  */
 511
 512 /*  Parameter values for the D101S  */
 513 #define D101S_CPUSAVER_DWORD                78
 514 #define D101S_CPUSAVER_BUNDLE_MAX_DWORD     67
 515 #define D101S_CPUSAVER_MIN_SIZE_DWORD       129
 516
 517
 518 #define D101S_RCVBUNDLE_UCODE \
 519 {\
 520 0x00550242, \
 521 0xFFFF047E, \
 522 0xFFFFFFFF, \
 523 0x06FF0818, \
 524 0xFFFFFFFF, \
 525 0x05A6FFFF, \
 526 0x000C0001, \
 527 0x00101312, \
 528 0x000C0008, \
 529 0x00380243, \
 530 0x0010009C, \
 531 0x00204056, \
 532 0x002380D0, \
 533 0x00380056, \
 534 0x0010009C, \
 535 0x00244F8B, \
 536 0x00000800, \
 537 0x00124818, \
 538 0x0038047F, \
 539 0x00000000, \
 540 0x00140000, \
 541 0x003805A3, \
 542 0x00308000, \
 543 0x00100610, \
 544 0x00100561, \
 545 0x000E0408, \
 546 0x00134861, \
 547 0x000C0002, \
 548 0x00103093, \
 549 0x00308000, \
 550 0x00100624, \
 551 0x00100561, \
 552 0x000E0408, \
 553 0x00100861, \
 554 0x000C007E, \
 555 0x00222FA1, \
 556 0x000C0002, \
 557 0x00103093, \
 558 0x00380F90, \
 559 0x00080000, \
 560 0x00103090, \
 561 0x00380F90, \
 562 0x00000000, \
 563 0x00000000, \
 564 0x00000000, \
 565 0x00000000, \
 566 0x0010009C, \
 567 0x00244FAD, \
 568 0x00010004, \
 569 0x00041000, \
 570 0x003A047E, \
 571 0x00044010, \
 572 0x00380819, \
 573 0x00000000, \
 574 0x00100099, \
 575 0x00206FFD, \
 576 0x0010009A, \
 577 0x0020AFFD, \
 578 0x0010009C, \
 579 0x00244FC8, \
 580 0x00130824, \
 581 0x000C0001, \
 582 0x00101213, \
 583 0x00260FF8, \
 584 0x00041000, \
 585 0x00010004, \
 586 0x00130826, \
 587 0x000C0006, \
 588 0x00220700, \
 589 0x0013C926, \
 590 0x00101313, \
 591 0x00380700, \
 592 0x00000000, \
 593 0x00000000, \
 594 0x00000000, \
 595 0x00000000, \
 596 0x00000000, \
 597 0x00000000, \
 598 0x00080600, \
 599 0x00101B10, \
 600 0x00050004, \
 601 0x00100826, \
 602 0x00101210, \
 603 0x00380FB6, \
 604 0x00000000, \
 605 0x00000000, \
 606 0x002115A9, \
 607 0x00100099, \
 608 0x002065A7, \
 609 0x0010009A, \
 610 0x0020A5A7, \
 611 0x0010009C, \
 612 0x002445A7, \
 613 0x00130836, \
 614 0x000C0000, \
 615 0x00220FE4, \
 616 0x000C0001, \
 617 0x00101B13, \
 618 0x00229F8E, \
 619 0x00210F8E, \
 620 0x00226F8E, \
 621 0x00216F8E, \
 622 0x0022FF8E, \
 623 0x00215F8E, \
 624 0x00214F8E, \
 625 0x003805A3, \
 626 0x00010004, \
 627 0x00041000, \
 628 0x00278FE9, \
 629 0x00040800, \
 630 0x00018100, \
 631 0x003A047E, \
 632 0x00130826, \
 633 0x000C0001, \
 634 0x002205A7, \
 635 0x00101313, \
 636 0x003805A7, \
 637 0x00000000, \
 638 0x00000000, \
 639 0x00000000, \
 640 0x00000000, \
 641 0x00000000, \
 642 0x00000000, \
 643 0x00000000, \
 644 0x00000000, \
 645 0x00000000, \
 646 0x00130831, \
 647 0x0010090B, \
 648 0x00124813, \
 649 0x000CFF80, \
 650 0x00260703, \
 651 0x00041000, \
 652 0x00380700, \
 653 0x00000000, \
 654 }
 655
 656
 657 /********************************************************/
 658 /*  CPUSaver micro code for the D102 B-step             */
 659 /********************************************************/
 660
 661 /*  Version 2.0  */
 662
 663 /*
 664     This version of CPUSaver is different from all others in
 665     a different way.  It combines the CPUSaver algorithm with
 666     fixes for bugs in the B-step hardware (specifically, bugs
 667     with Inline Receive).
 668     Thus, when CPUSaver is disabled, this micro code image will
 669     still need to be loaded.  Before this happens, the hit addresses
 670     for the CPUSaver algorithm must be set to 0x1FFFF.  The hit
 671     addresses for CPUSaver are (starting with 0, and remember that
 672
 673 */
 674
 675 /*  Parameter values for the D102 B-step  */
 676 #define D102_B_CPUSAVER_DWORD                91
 677 #define D102_B_CPUSAVER_BUNDLE_MAX_DWORD     115
 678 #define D102_B_CPUSAVER_MIN_SIZE_DWORD       70
 679
 680
 681 #define     D102_B_RCVBUNDLE_UCODE \
 682 {\
 683 0x006F0276, \
 684 0x02BF0E93, \
 685 0x1FFF0ED9, \
 686 0x0D2508FA, \
 687 0x04D21FFF, \
 688 0x0EA10892, \
 689 0x00300001, \
 690 0x0140D871, \
 691 0x00300008, \
 692 0x00E00277, \
 693 0x01406C57, \
 694 0x00816073, \
 695 0x008700FA, \
 696 0x00E00070, \
 697 0x00E00E94, \
 698 0x00200004, \
 699 0x01410000, \
 700 0x014B6F6F, \
 701 0x0030FFFF, \
 702 0x01486F72, \
 703 0x00E81F9B, \
 704 0x00E00EA3, \
 705 0x003C0040, \
 706 0x00380920, \
 707 0x00C02000, \
 708 0x0150ED38, \
 709 0x0150EE39, \
 710 0x0150EF3A, \
 711 0x003C0040, \
 712 0x01506F0D, \
 713 0x01600E72, \
 714 0x00380AE0, \
 715 0x00E002C0, \
 716 0x00300001, \
 717 0x014C0000, \
 718 0x008404DC, \
 719 0x014C6F72, \
 720 0x00E01F9D, \
 721 0x01406C51, \
 722 0x0080DFC2, \
 723 0x01406C52, \
 724 0x00815FC2, \
 725 0x01406C57, \
 726 0x00917FD5, \
 727 0x00E01FE6, \
 728 0x00000000, \
 729 0x01406C57, \
 730 0x00919FAD, \
 731 0x00038800, \
 732 0x00300000, \
 733 0x00E81FF2, \
 734 0x014D6FC4, \
 735 0x00E008FB, \
 736 0x00000000, \
 737 0x00822D30, \
 738 0x01406C51, \
 739 0x0080CD26, \
 740 0x01406C52, \
 741 0x00814D26, \
 742 0x01406C57, \
 743 0x00916D26, \
 744 0x014C6FD7, \
 745 0x00300000, \
 746 0x00841FDB, \
 747 0x00300001, \
 748 0x0140D772, \
 749 0x00E012B3, \
 750 0x014C6F91, \
 751 0x0150710B, \
 752 0x01496F72, \
 753 0x0030FF80, \
 754 0x00940EDD, \
 755 0x00102000, \
 756 0x00E00EDA, \
 757 0x01406C57, \
 758 0x00917FFD, \
 759 0x00001000, \
 760 0x00E01FFD, \
 761 0x00138800, \
 762 0x00300001, \
 763 0x00E81FF2, \
 764 0x00202500, \
 765 0x00E81F9B, \
 766 0x01600EC5, \
 767 0x00E00893, \
 768 0x00000000, \
 769 0x01406CD5, \
 770 0x0091EEA3, \
 771 0x00904EA3, \
 772 0x00901F89, \
 773 0x00E00EA3, \
 774 0x00200600, \
 775 0x0140D76F, \
 776 0x00138400, \
 777 0x01406FD8, \
 778 0x0140D96F, \
 779 0x00E01FE6, \
 780 0x00038400, \
 781 0x00102000, \
 782 0x00971FE0, \
 783 0x00101000, \
 784 0x00050200, \
 785 0x00E804D2, \
 786 0x014C6FD8, \
 787 0x00300001, \
 788 0x00840D26, \
 789 0x0140D872, \
 790 0x00E00D26, \
 791 0x014C6FD9, \
 792 0x00300001, \
 793 0x0140D972, \
 794 0x00941FBD, \
 795 0x00102000, \
 796 0x00038400, \
 797 0x014C6FD8, \
 798 0x00300006, \
 799 0x00840EDA, \
 800 0x014F71D8, \
 801 0x0140D872, \
 802 0x00E00EDA, \
 803 0x00340020, \
 804 0x014C6FED, \
 805 0x01603472, \
 806 0x016035EE, \
 807 0x016036EF, \
 808 0x00300004, \
 809 0x01611C71, \
 810 0x00300014, \
 811 0x00200A00, \
 812 0x00E810B9, \
 813 0x00600000, \
 814 0x01496F50, \
 815 0x00E004D3, \
 816 0x00000000, \
 817 }
 818
 819
 820
 821
 822 /********************************************************/
 823 /*  TCO micro code for the D102 B-step             */
 824 /********************************************************/
 825
 826 /*  Version 2.0  */
 827
 828 /*
 829     This version is a fix to TCO bug. This version can be loaded instead
 830     the CPUSaver version by modifing the registry key "LoadTcoUCodeInsteadOfCpuSaver"
 831
 832 */
 833
 834
 835 #define     D102_B_TCO_UCODE \
 836 {\
 837 0x1FFF0ED3, \
 838 0x02BF0E93, \
 839 0x1FFF1FFF, \
 840 0x1FFF08FA, \
 841 0x1FFF1FFF, \
 842 0x0EA10892, \
 843 0x00906ED8, \
 844 0x01406C55, \
 845 0x00E00ED4, \
 846 0x00000000, \
 847 0x00000000, \
 848 0x00000000, \
 849 0x00000000, \
 850 0x00000000, \
 851 0x00E00E94, \
 852 0x00200004, \
 853 0x01410000, \
 854 0x014B6F6F, \
 855 0x0030FFFF, \
 856 0x01486F72, \
 857 0x00E81F9B, \
 858 0x00E00EA3, \
 859 0x003C0040, \
 860 0x00380920, \
 861 0x00C02000, \
 862 0x0150ED38, \
 863 0x0150EE39, \
 864 0x0150EF3A, \
 865 0x003C0040, \
 866 0x01506F0D, \
 867 0x01600E72, \
 868 0x00380AE0, \
 869 0x00E002C0, \
 870 0x00300001, \
 871 0x014C0000, \
 872 0x008404DC, \
 873 0x014C6F72, \
 874 0x00E01F9D, \
 875 0x00000000, \
 876 0x00000000, \
 877 0x00000000, \
 878 0x00000000, \
 879 0x00000000, \
 880 0x00000000, \
 881 0x00000000, \
 882 0x00000000, \
 883 0x01406C57, \
 884 0x00919FAD, \
 885 0x00038800, \
 886 0x00300000, \
 887 0x00E81FD5, \
 888 0x014D6FC4, \
 889 0x00E008FB, \
 890 0x00000000, \
 891 0x00000000, \
 892 0x00000000, \
 893 0x00000000, \
 894 0x00000000, \
 895 0x00000000, \
 896 0x00000000, \
 897 0x00000000, \
 898 0x00000000, \
 899 0x00000000, \
 900 0x00000000, \
 901 0x00000000, \
 902 0x00000000, \
 903 0x00000000, \
 904 0x00000000, \
 905 0x00000000, \
 906 0x00000000, \
 907 0x00000000, \
 908 0x00000000, \
 909 0x00000000, \
 910 0x00000000, \
 911 0x00000000, \
 912 0x00000000, \
 913 0x00000000, \
 914 0x00000000, \
 915 0x00138800, \
 916 0x00300001, \
 917 0x00E81FD5, \
 918 0x00202500, \
 919 0x00E81F9B, \
 920 0x01600EC5, \
 921 0x00E00893, \
 922 0x00000000, \
 923 0x01406CD5, \
 924 0x0091EEA3, \
 925 0x00904EA3, \
 926 0x00901F89, \
 927 0x00E00EA3, \
 928 0x00340020, \
 929 0x014C6FED, \
 930 0x01603472, \
 931 0x016035EE, \
 932 0x016036EF, \
 933 0x00300004, \
 934 0x01611C71, \
 935 0x00300014, \
 936 0x00200A00, \
 937 0x00E810B9, \
 938 0x00600000, \
 939 0x00000000, \
 940 0x00000000, \
 941 0x00000000, \
 942 0x00000000, \
 943 0x00000000, \
 944 0x00000000, \
 945 0x00000000, \
 946 0x00000000, \
 947 0x00000000, \
 948 0x00000000, \
 949 0x00000000, \
 950 0x00000000, \
 951 0x00000000, \
 952 0x00000000, \
 953 0x00000000, \
 954 0x00000000, \
 955 0x00000000, \
 956 0x00000000, \
 957 0x00000000, \
 958 0x00000000, \
 959 0x00000000, \
 960 0x00000000, \
 961 0x00000000, \
 962 0x00000000, \
 963 0x00000000, \
 964 0x00000000, \
 965 0x00000000, \
 966 0x00000000, \
 967 0x00000000, \
 968 0x00000000, \
 969 0x00000000, \
 970 0x00000000, \
 971 }
 972
 973
 974
 975 /********************************************************/
 976 /*  Micro code for the D102 C-step                      */
 977 /********************************************************/
 978
 979 /*  Parameter values for the D102 C-step  */
 980 #define D102_C_CPUSAVER_DWORD                46
 981 #define D102_C_CPUSAVER_BUNDLE_MAX_DWORD     54
 982 #define D102_C_CPUSAVER_MIN_SIZE_DWORD      133 /* not implemented */
 983
 984
 985
 986
 987
 988 #if 0
 989 // this uCode include the CPU Saver and the TCO work around
 990 //for IP fregments.
 991 #endif
 992 #define     D102_C_RCVBUNDLE_UCODE \
 993 { \
 994 0x00700279, \
 995 0x0E6104E2, \
 996 0x02BF0CAE, \
 997 0x1519150C, \
 998 0x1FFF0E5B, \
 999 0x1FFF1FFF, \
1000 0x00E014D8, \
1001 0x00000000, \
1002 0x00000000, \
1003 0x00000000, \
1004 0x00E014DC, \
1005 0x00000000, \
1006 0x00000000, \
1007 0x00000000, \
1008 0x00E014F4, \
1009 0x00000000, \
1010 0x00000000, \
1011 0x00000000, \
1012 0x00000000, \
1013 0x00000000, \
1014 0x00000000, \
1015 0x00000000, \
1016 0x00E014E0, \
1017 0x00000000, \
1018 0x00000000, \
1019 0x00000000, \
1020 0x00000000, \
1021 0x00000000, \
1022 0x00000000, \
1023 0x00000000, \
1024 0x00000000, \
1025 0x00000000, \
1026 0x00000000, \
1027 0x00000000, \
1028 0x00000000, \
1029 0x00000000, \
1030 0x00000000, \
1031 0x00000000, \
1032 0x00E014E7, \
1033 0x00000000, \
1034 0x00000000, \
1035 0x00000000, \
1036 0x00141000, \
1037 0x015D6F0D, \
1038 0x00E002C0, \
1039 0x00000000, \
1040 0x00200600, \
1041 0x00E0150D, \
1042 0x00000000, \
1043 0x00000000, \
1044 0x00000000, \
1045 0x00000000, \
1046 0x00000000, \
1047 0x00000000, \
1048 0x00300006, \
1049 0x00E0151A, \
1050 0x00000000, \
1051 0x00000000, \
1052 0x00000000, \
1053 0x00000000, \
1054 0x00000000, \
1055 0x00000000, \
1056 0x00000000, \
1057 0x00000000, \
1058 0x00000000, \
1059 0x00000000, \
1060 0x00000000, \
1061 0x00000000, \
1062 0x00000000, \
1063 0x00000000, \
1064 0x00906E65, \
1065 0x00800E60, \
1066 0x00E00E5D, \
1067 0x00000000, \
1068 0x00000000, \
1069 0x00000000, \
1070 0x00000000, \
1071 0x00000000, \
1072 0x00000000, \
1073 0x00000000, \
1074 0x00000000, \
1075 0x00000000, \
1076 0x00000000, \
1077 0x00000000, \
1078 0x00000000, \
1079 0x00000000, \
1080 0x00000000, \
1081 0x00000000, \
1082 0x00000000, \
1083 0x00000000, \
1084 0x00000000, \
1085 0x00000000, \
1086 0x00000000, \
1087 0x00000000, \
1088 0x00000000, \
1089 0x00000000, \
1090 0x00000000, \
1091 0x00000000, \
1092 0x00000000, \
1093 0x00000000, \
1094 0x00000000, \
1095 0x00000000, \
1096 0x00000000, \
1097 0x00000000, \
1098 0x00000000, \
1099 0x00000000, \
1100 0x00000000, \
1101 0x00000000, \
1102 0x00000000, \
1103 0x00000000, \
1104 0x00000000, \
1105 0x00000000, \
1106 0x00000000, \
1107 0x00000000, \
1108 0x00000000, \
1109 0x00000000, \
1110 0x00000000, \
1111 0x00000000, \
1112 0x00000000, \
1113 0x00000000, \
1114 0x00000000, \
1115 0x00000000, \
1116 0x00000000, \
1117 0x00000000, \
1118 0x00000000, \
1119 0x00000000, \
1120 0x00000000, \
1121 0x00000000, \
1122 0x00000000, \
1123 0x00000000, \
1124 0x00000000, \
1125 0x00000000, \
1126 0x00000000, \
1127 0x00000000, \
1128 }