sys/dev/usb/ehcireg.h

   1 /*      $NetBSD: ehcireg.h,v 1.28 2008/08/02 22:23:18 jmcneill Exp $    */
   2
   3 /*
   4  * Copyright (c) 2001, 2004 The NetBSD Foundation, Inc.
   5  * All rights reserved.
   6  *
   7  * This code is derived from software contributed to The NetBSD Foundation
   8  * by Lennart Augustsson (lennart@augustsson.net).
   9  *
  10  * Redistribution and use in source and binary forms, with or without
  11  * modification, are permitted provided that the following conditions
  12  * are met:
  13  * 1. Redistributions of source code must retain the above copyright
  14  *    notice, this list of conditions and the following disclaimer.
  15  * 2. Redistributions in binary form must reproduce the above copyright
  16  *    notice, this list of conditions and the following disclaimer in the
  17  *    documentation and/or other materials provided with the distribution.
  18  *
  19  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
  20  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  21  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  22  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
  23  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  29  * POSSIBILITY OF SUCH DAMAGE.
  30  */
  31
  32 /*
  33  * The EHCI 0.96 spec can be found at
  34  * http://developer.intel.com/technology/usb/download/ehci-r096.pdf
  35  * and the USB 2.0 spec at
  36  * http://www.usb.org/developers/data/usb_20.zip
  37  */
  38
  39 #ifndef _DEV_PCI_EHCIREG_H_
  40 #define _DEV_PCI_EHCIREG_H_
  41
  42 /*** PCI config registers ***/
  43
  44 #define PCI_CBMEM               0x10    /* configuration base MEM */
  45
  46 #define PCI_INTERFACE_EHCI      0x20
  47
  48 #define PCI_USBREV              0x60    /* RO USB protocol revision */
  49 #define  PCI_USBREV_MASK        0xff
  50 #define  PCI_USBREV_PRE_1_0     0x00
  51 #define  PCI_USBREV_1_0         0x10
  52 #define  PCI_USBREV_1_1         0x11
  53 #define  PCI_USBREV_2_0         0x20
  54
  55 #define PCI_EHCI_FLADJ          0x61    /*RW Frame len adj, SOF=59488+6*fladj */
  56
  57 #define PCI_EHCI_PORTWAKECAP    0x62    /* RW Port wake caps (opt)  */
  58
  59 /* Regs at EECP + offset */
  60 #define PCI_EHCI_USBLEGSUP      0x00
  61 #define  EHCI_LEG_HC_OS_OWNED           0x01000000
  62 #define  EHCI_LEG_HC_BIOS_OWNED         0x00010000
  63 #define PCI_EHCI_USBLEGCTLSTS   0x04
  64 #define  EHCI_LEG_EXT_SMI_BAR           0x80000000
  65 #define  EHCI_LEG_EXT_SMI_PCICMD        0x40000000
  66 #define  EHCI_LEG_EXT_SMI_OS_CHANGE     0x20000000
  67
  68 #define EHCI_CAP_GET_ID(cap) ((cap) & 0xff)
  69 #define EHCI_CAP_GET_NEXT(cap) (((cap) >> 8) & 0xff)
  70 #define EHCI_CAP_ID_LEGACY 1
  71
  72 /*** EHCI capability registers ***/
  73
  74 #define EHCI_CAPLENGTH          0x00    /*RO Capability register length field */
  75 /* reserved                     0x01 */
  76 #define EHCI_HCIVERSION         0x02    /* RO Interface version number */
  77
  78 #define EHCI_HCSPARAMS          0x04    /* RO Structural parameters */
  79 #define  EHCI_HCS_DEBUGPORT(x)  (((x) >> 20) & 0xf)
  80 #define  EHCI_HCS_P_INDICATOR(x) ((x) & 0x10000)
  81 #define  EHCI_HCS_N_CC(x)       (((x) >> 12) & 0xf) /* # of companion ctlrs */
  82 #define  EHCI_HCS_N_PCC(x)      (((x) >> 8) & 0xf) /* # of ports per comp. */
  83 #define  EHCI_HCS_PPC(x)        ((x) & 0x10) /* port power control */
  84 #define  EHCI_HCS_N_PORTS(x)    ((x) & 0xf) /* # of ports */
  85
  86 #define EHCI_HCCPARAMS          0x08    /* RO Capability parameters */
  87 #define  EHCI_HCC_EECP(x)       (((x) >> 8) & 0xff) /* extended ports caps */
  88 #define  EHCI_HCC_IST(x)        (((x) >> 4) & 0xf) /* isoc sched threshold */
  89 #define  EHCI_HCC_ASPC(x)       ((x) & 0x4) /* async sched park cap */
  90 #define  EHCI_HCC_PFLF(x)       ((x) & 0x2) /* prog frame list flag */
  91 #define  EHCI_HCC_64BIT(x)      ((x) & 0x1) /* 64 bit address cap */
  92
  93 #define EHCI_HCSP_PORTROUTE     0x0c    /*RO Companion port route description */
  94
  95 /* EHCI operational registers.  Offset given by EHCI_CAPLENGTH register */
  96 #define EHCI_USBCMD             0x00    /* RO, RW, WO Command register */
  97 #define  EHCI_CMD_ITC_M         0x00ff0000 /* RW interrupt threshold ctrl */
  98 #define   EHCI_CMD_ITC_1        0x00010000
  99 #define   EHCI_CMD_ITC_2        0x00020000
 100 #define   EHCI_CMD_ITC_4        0x00040000
 101 #define   EHCI_CMD_ITC_8        0x00080000
 102 #define   EHCI_CMD_ITC_16       0x00100000
 103 #define   EHCI_CMD_ITC_32       0x00200000
 104 #define   EHCI_CMD_ITC_64       0x00400000
 105 #define  EHCI_CMD_ASPME         0x00000800 /* RW/RO async park enable */
 106 #define  EHCI_CMD_ASPMC         0x00000300 /* RW/RO async park count */
 107 #define  EHCI_CMD_LHCR          0x00000080 /* RW light host ctrl reset */
 108 #define  EHCI_CMD_IAAD          0x00000040 /* RW intr on async adv door bell */
 109 #define  EHCI_CMD_ASE           0x00000020 /* RW async sched enable */
 110 #define  EHCI_CMD_PSE           0x00000010 /* RW periodic sched enable */
 111 #define  EHCI_CMD_FLS_M         0x0000000c /* RW/RO frame list size */
 112 #define  EHCI_CMD_FLS(x)        (((x) >> 2) & 3) /* RW/RO frame list size */
 113 #define  EHCI_CMD_HCRESET       0x00000002 /* RW reset */
 114 #define  EHCI_CMD_RS            0x00000001 /* RW run/stop */
 115
 116 #define EHCI_USBSTS             0x04    /* RO, RW, RWC Status register */
 117 #define  EHCI_STS_ASS           0x00008000 /* RO async sched status */
 118 #define  EHCI_STS_PSS           0x00004000 /* RO periodic sched status */
 119 #define  EHCI_STS_REC           0x00002000 /* RO reclamation */
 120 #define  EHCI_STS_HCH           0x00001000 /* RO host controller halted */
 121 #define  EHCI_STS_IAA           0x00000020 /* RWC interrupt on async adv */
 122 #define  EHCI_STS_HSE           0x00000010 /* RWC host system error */
 123 #define  EHCI_STS_FLR           0x00000008 /* RWC frame list rollover */
 124 #define  EHCI_STS_PCD           0x00000004 /* RWC port change detect */
 125 #define  EHCI_STS_ERRINT        0x00000002 /* RWC error interrupt */
 126 #define  EHCI_STS_INT           0x00000001 /* RWC interrupt */
 127 #define  EHCI_STS_INTRS(x)      ((x) & 0x3f)
 128
 129 #define EHCI_NORMAL_INTRS (EHCI_STS_IAA | EHCI_STS_HSE | EHCI_STS_PCD | EHCI_STS_ERRINT | EHCI_STS_INT)
 130
 131 #define EHCI_USBINTR            0x08    /* RW Interrupt register */
 132 #define EHCI_INTR_IAAE          0x00000020 /* interrupt on async advance ena */
 133 #define EHCI_INTR_HSEE          0x00000010 /* host system error ena */
 134 #define EHCI_INTR_FLRE          0x00000008 /* frame list rollover ena */
 135 #define EHCI_INTR_PCIE          0x00000004 /* port change ena */
 136 #define EHCI_INTR_UEIE          0x00000002 /* USB error intr ena */
 137 #define EHCI_INTR_UIE           0x00000001 /* USB intr ena */
 138
 139 #define EHCI_FRINDEX            0x0c    /* RW Frame Index register */
 140
 141 #define EHCI_CTRLDSSEGMENT      0x10    /* RW Control Data Structure Segment */
 142
 143 #define EHCI_PERIODICLISTBASE   0x14    /* RW Periodic List Base */
 144 #define EHCI_ASYNCLISTADDR      0x18    /* RW Async List Base */
 145
 146 #define EHCI_CONFIGFLAG         0x40    /* RW Configure Flag register */
 147 #define  EHCI_CONF_CF           0x00000001 /* RW configure flag */
 148
 149 #define EHCI_PORTSC(n)          (0x40+4*(n)) /* RO, RW, RWC Port Status reg */
 150 #define  EHCI_PS_WKOC_E         0x00400000 /* RW wake on over current ena */
 151 #define  EHCI_PS_WKDSCNNT_E     0x00200000 /* RW wake on disconnect ena */
 152 #define  EHCI_PS_WKCNNT_E       0x00100000 /* RW wake on connect ena */
 153 #define  EHCI_PS_PTC            0x000f0000 /* RW port test control */
 154 #define  EHCI_PS_PIC            0x0000c000 /* RW port indicator control */
 155 #define  EHCI_PS_PO             0x00002000 /* RW port owner */
 156 #define  EHCI_PS_PP             0x00001000 /* RW,RO port power */
 157 #define  EHCI_PS_LS             0x00000c00 /* RO line status */
 158 #define  EHCI_PS_IS_LOWSPEED(x) (((x) & EHCI_PS_LS) == 0x00000400)
 159 #define  EHCI_PS_PR             0x00000100 /* RW port reset */
 160 #define  EHCI_PS_SUSP           0x00000080 /* RW suspend */
 161 #define  EHCI_PS_FPR            0x00000040 /* RW force port resume */
 162 #define  EHCI_PS_OCC            0x00000020 /* RWC over current change */
 163 #define  EHCI_PS_OCA            0x00000010 /* RO over current active */
 164 #define  EHCI_PS_PEC            0x00000008 /* RWC port enable change */
 165 #define  EHCI_PS_PE             0x00000004 /* RW port enable */
 166 #define  EHCI_PS_CSC            0x00000002 /* RWC connect status change */
 167 #define  EHCI_PS_CS             0x00000001 /* RO connect status */
 168 #define  EHCI_PS_CLEAR          (EHCI_PS_OCC|EHCI_PS_PEC|EHCI_PS_CSC)
 169
 170 #define EHCI_PORT_RESET_COMPLETE 2 /* ms */
 171
 172 #define EHCI_FLALIGN_ALIGN      0x1000
 173 #define EHCI_MAX_PORTS          16 /* only 4 bits available in EHCI_HCS_N_PORTS */
 174
 175 /* No data structure may cross a page boundary. */
 176 #define EHCI_PAGE_SIZE 0x1000
 177 #define EHCI_PAGE(x) ((x) &~ 0xfff)
 178 #define EHCI_PAGE_OFFSET(x) ((x) & 0xfff)
 179
 180 typedef u_int32_t ehci_link_t;
 181 #define EHCI_LINK_TERMINATE     0x00000001
 182 #define EHCI_LINK_TYPE(x)       ((x) & 0x00000006)
 183 #define  EHCI_LINK_ITD          0x0
 184 #define  EHCI_LINK_QH           0x2
 185 #define  EHCI_LINK_SITD         0x4
 186 #define  EHCI_LINK_FSTN         0x6
 187 #define EHCI_LINK_ADDR(x)       ((x) &~ 0x1f)
 188
 189 typedef u_int32_t ehci_physaddr_t;
 190
 191 typedef u_int32_t ehci_isoc_trans_t;
 192 typedef u_int32_t ehci_isoc_bufr_ptr_t;
 193
 194 /* Isochronous Transfer Descriptor */
 195 typedef struct {
 196         volatile ehci_link_t            itd_next;
 197         volatile ehci_isoc_trans_t      itd_ctl[8];
 198 #define EHCI_ITD_GET_STATUS(x) (((x) >> 28) & 0xf)
 199 #define EHCI_ITD_SET_STATUS(x) (((x) & 0xf) << 28)
 200 #define EHCI_ITD_ACTIVE         0x80000000
 201 #define EHCI_ITD_BUF_ERR        0x40000000
 202 #define EHCI_ITD_BABBLE         0x20000000
 203 #define EHCI_ITD_ERROR          0x10000000
 204 #define EHCI_ITD_GET_LEN(x) (((x) >> 16) & 0xfff)
 205 #define EHCI_ITD_SET_LEN(x) (((x) & 0xfff) << 16)
 206 #define EHCI_ITD_IOC            0x8000
 207 #define EHCI_ITD_GET_IOC(x) (((x) >> 15) & 1)
 208 #define EHCI_ITD_SET_IOC(x) (((x) << 15) & EHCI_ITD_IOC)
 209 #define EHCI_ITD_GET_PG(x) (((x) >> 12) & 0x7)
 210 #define EHCI_ITD_SET_PG(x) (((x) & 0x7) << 12)
 211 #define EHCI_ITD_GET_OFFS(x) (((x) >> 0) & 0xfff)
 212 #define EHCI_ITD_SET_OFFS(x) (((x) & 0xfff) << 0)
 213         volatile ehci_isoc_bufr_ptr_t   itd_bufr[7];
 214 #define EHCI_ITD_GET_BPTR(x) ((x) & 0xfffff000)
 215 #define EHCI_ITD_SET_BPTR(x) ((x) & 0xfffff000)
 216 #define EHCI_ITD_GET_EP(x) (((x) >> 8) & 0xf)
 217 #define EHCI_ITD_SET_EP(x) (((x) & 0xf) << 8)
 218 #define EHCI_ITD_GET_DADDR(x) ((x) & 0x7f)
 219 #define EHCI_ITD_SET_DADDR(x) ((x) & 0x7f)
 220 #define EHCI_ITD_GET_DIR(x) (((x) >> 11) & 1)
 221 #define EHCI_ITD_SET_DIR(x) (((x) & 1) << 11)
 222 #define EHCI_ITD_GET_MAXPKT(x) ((x) & 0x7ff)
 223 #define EHCI_ITD_SET_MAXPKT(x) ((x) & 0x7ff)
 224 #define EHCI_ITD_GET_MULTI(x) ((x) & 0x3)
 225 #define EHCI_ITD_SET_MULTI(x) ((x) & 0x3)
 226         volatile ehci_isoc_bufr_ptr_t   itd_bufr_hi[7];
 227 } ehci_itd_t;
 228 #define EHCI_ITD_ALIGN 32
 229
 230 /* Split Transaction Isochronous Transfer Descriptor */
 231 typedef struct {
 232         volatile ehci_link_t    sitd_next;
 233         /* XXX many more */
 234 } ehci_sitd_t;
 235 #define EHCI_SITD_ALIGN 32
 236
 237 /* Queue Element Transfer Descriptor */
 238 #define EHCI_QTD_NBUFFERS 5
 239 typedef struct {
 240         volatile ehci_link_t    qtd_next;
 241         volatile ehci_link_t    qtd_altnext;
 242         volatile u_int32_t      qtd_status;
 243 #define EHCI_QTD_GET_STATUS(x)  (((x) >>  0) & 0xff)
 244 #define EHCI_QTD_SET_STATUS(x)  ((x) <<  0)
 245 #define  EHCI_QTD_ACTIVE        0x80
 246 #define  EHCI_QTD_HALTED        0x40
 247 #define  EHCI_QTD_BUFERR        0x20
 248 #define  EHCI_QTD_BABBLE        0x10
 249 #define  EHCI_QTD_XACTERR       0x08
 250 #define  EHCI_QTD_MISSEDMICRO   0x04
 251 #define  EHCI_QTD_SPLITXSTATE   0x02
 252 #define  EHCI_QTD_PINGSTATE     0x01
 253 #define  EHCI_QTD_STATERRS      0x3c
 254 #define EHCI_QTD_GET_PID(x)     (((x) >>  8) & 0x3)
 255 #define EHCI_QTD_SET_PID(x)     ((x) <<  8)
 256 #define  EHCI_QTD_PID_OUT       0x0
 257 #define  EHCI_QTD_PID_IN        0x1
 258 #define  EHCI_QTD_PID_SETUP     0x2
 259 #define EHCI_QTD_GET_CERR(x)    (((x) >> 10) &  0x3)
 260 #define EHCI_QTD_SET_CERR(x)    ((x) << 10)
 261 #define EHCI_QTD_GET_C_PAGE(x)  (((x) >> 12) &  0x7)
 262 #define EHCI_QTD_SET_C_PAGE(x)  ((x) << 12)
 263 #define EHCI_QTD_GET_IOC(x)     (((x) >> 15) &  0x1)
 264 #define EHCI_QTD_IOC            0x00008000
 265 #define EHCI_QTD_GET_BYTES(x)   (((x) >> 16) &  0x7fff)
 266 #define EHCI_QTD_SET_BYTES(x)   ((x) << 16)
 267 #define EHCI_QTD_GET_TOGGLE(x)  (((x) >> 31) &  0x1)
 268 #define EHCI_QTD_SET_TOGGLE(x)  ((x) << 31)
 269 #define EHCI_QTD_TOGGLE_MASK    0x80000000
 270         volatile ehci_physaddr_t qtd_buffer[EHCI_QTD_NBUFFERS];
 271         volatile ehci_physaddr_t qtd_buffer_hi[EHCI_QTD_NBUFFERS];
 272 } ehci_qtd_t;
 273 #define EHCI_QTD_ALIGN 32
 274
 275 /* Queue Head */
 276 typedef struct {
 277         volatile ehci_link_t    qh_link;
 278         volatile u_int32_t      qh_endp;
 279 #define EHCI_QH_GET_ADDR(x)     (((x) >>  0) & 0x7f) /* endpoint addr */
 280 #define EHCI_QH_SET_ADDR(x)     (x)
 281 #define EHCI_QH_ADDRMASK        0x0000007f
 282 #define EHCI_QH_GET_INACT(x)    (((x) >>  7) & 0x01) /* inactivate on next */
 283 #define EHCI_QH_INACT           0x00000080
 284 #define EHCI_QH_GET_ENDPT(x)    (((x) >>  8) & 0x0f) /* endpoint no */
 285 #define EHCI_QH_SET_ENDPT(x)    ((x) <<  8)
 286 #define EHCI_QH_GET_EPS(x)      (((x) >> 12) & 0x03) /* endpoint speed */
 287 #define EHCI_QH_SET_EPS(x)      ((x) << 12)
 288 #define  EHCI_QH_SPEED_FULL     0x0
 289 #define  EHCI_QH_SPEED_LOW      0x1
 290 #define  EHCI_QH_SPEED_HIGH     0x2
 291 #define EHCI_QH_GET_DTC(x)      (((x) >> 14) & 0x01) /* data toggle control */
 292 #define EHCI_QH_DTC             0x00004000
 293 #define EHCI_QH_GET_HRECL(x)    (((x) >> 15) & 0x01) /* head of reclamation */
 294 #define EHCI_QH_HRECL           0x00008000
 295 #define EHCI_QH_GET_MPL(x)      (((x) >> 16) & 0x7ff) /* max packet len */
 296 #define EHCI_QH_SET_MPL(x)      ((x) << 16)
 297 #define EHCI_QH_MPLMASK         0x07ff0000
 298 #define EHCI_QH_GET_CTL(x)      (((x) >> 27) & 0x01) /* control endpoint */
 299 #define EHCI_QH_CTL             0x08000000
 300 #define EHCI_QH_GET_NRL(x)      (((x) >> 28) & 0x0f) /* NAK reload */
 301 #define EHCI_QH_SET_NRL(x)      ((x) << 28)
 302         volatile u_int32_t      qh_endphub;
 303 #define EHCI_QH_GET_SMASK(x)    (((x) >>  0) & 0xff) /* intr sched mask */
 304 #define EHCI_QH_SET_SMASK(x)    ((x) <<  0)
 305 #define EHCI_QH_GET_CMASK(x)    (((x) >>  8) & 0xff) /* split completion mask */
 306 #define EHCI_QH_SET_CMASK(x)    ((x) <<  8)
 307 #define EHCI_QH_GET_HUBA(x)     (((x) >> 16) & 0x7f) /* hub address */
 308 #define EHCI_QH_SET_HUBA(x)     ((x) << 16)
 309 #define EHCI_QH_GET_PORT(x)     (((x) >> 23) & 0x7f) /* hub port */
 310 #define EHCI_QH_SET_PORT(x)     ((x) << 23)
 311 #define EHCI_QH_GET_MULT(x)     (((x) >> 30) & 0x03) /* pipe multiplier */
 312 #define EHCI_QH_SET_MULT(x)     ((x) << 30)
 313         volatile ehci_link_t    qh_curqtd;
 314         ehci_qtd_t              qh_qtd;
 315 } ehci_qh_t;
 316 #define EHCI_QH_ALIGN 32
 317
 318 /* Periodic Frame Span Traversal Node */
 319 typedef struct {
 320         volatile ehci_link_t    fstn_link;
 321         volatile ehci_link_t    fstn_back;
 322 } ehci_fstn_t;
 323 #define EHCI_FSTN_ALIGN 32
 324
 325 #endif /* _DEV_PCI_EHCIREG_H_ */