sys/dev/usb/if_rumreg.h

   1 /*      $NetBSD: if_rumreg.h$   */
   2 /*      $OpenBSD: if_rumreg.h,v 1.13 2006/11/13 20:06:38 damien Exp $   */
   3
   4 /*-
   5  * Copyright (c) 2005, 2006 Damien Bergamini <damien.bergamini@free.fr>
   6  * Copyright (c) 2006 Niall O'Higgins <niallo@openbsd.org>
   7  *
   8  * Permission to use, copy, modify, and distribute this software for any
   9  * purpose with or without fee is hereby granted, provided that the above
  10  * copyright notice and this permission notice appear in all copies.
  11  *
  12  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  13  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  14  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  15  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  16  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  17  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  18  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  19  */
  20
  21 #define RT2573_TX_DESC_SIZE     (sizeof (struct rum_tx_desc))
  22 #define RT2573_RX_DESC_SIZE     (sizeof (struct rum_rx_desc))
  23
  24 #define RT2573_CONFIG_NO        1
  25 #define RT2573_IFACE_INDEX      0
  26
  27 #define RT2573_MCU_CNTL         0x01
  28 #define RT2573_WRITE_MAC        0x02
  29 #define RT2573_READ_MAC         0x03
  30 #define RT2573_WRITE_MULTI_MAC  0x06
  31 #define RT2573_READ_MULTI_MAC   0x07
  32 #define RT2573_READ_EEPROM      0x09
  33 #define RT2573_WRITE_LED        0x0a
  34
  35 /*
  36  * Control and status registers.
  37  */
  38 #define RT2573_AIFSN_CSR        0x0400
  39 #define RT2573_CWMIN_CSR        0x0404
  40 #define RT2573_CWMAX_CSR        0x0408
  41 #define RT2573_MCU_CODE_BASE    0x0800
  42 #define RT2573_HW_BEACON_BASE0  0x2400
  43 #define RT2573_MAC_CSR0         0x3000
  44 #define RT2573_MAC_CSR1         0x3004
  45 #define RT2573_MAC_CSR2         0x3008
  46 #define RT2573_MAC_CSR3         0x300c
  47 #define RT2573_MAC_CSR4         0x3010
  48 #define RT2573_MAC_CSR5         0x3014
  49 #define RT2573_MAC_CSR6         0x3018
  50 #define RT2573_MAC_CSR7         0x301c
  51 #define RT2573_MAC_CSR8         0x3020
  52 #define RT2573_MAC_CSR9         0x3024
  53 #define RT2573_MAC_CSR10        0x3028
  54 #define RT2573_MAC_CSR11        0x302c
  55 #define RT2573_MAC_CSR12        0x3030
  56 #define RT2573_MAC_CSR13        0x3034
  57 #define RT2573_MAC_CSR14        0x3038
  58 #define RT2573_MAC_CSR15        0x303c
  59 #define RT2573_TXRX_CSR0        0x3040
  60 #define RT2573_TXRX_CSR1        0x3044
  61 #define RT2573_TXRX_CSR2        0x3048
  62 #define RT2573_TXRX_CSR3        0x304c
  63 #define RT2573_TXRX_CSR4        0x3050
  64 #define RT2573_TXRX_CSR5        0x3054
  65 #define RT2573_TXRX_CSR6        0x3058
  66 #define RT2573_TXRX_CSR7        0x305c
  67 #define RT2573_TXRX_CSR8        0x3060
  68 #define RT2573_TXRX_CSR9        0x3064
  69 #define RT2573_TXRX_CSR10       0x3068
  70 #define RT2573_TXRX_CSR11       0x306c
  71 #define RT2573_TXRX_CSR12       0x3070
  72 #define RT2573_TXRX_CSR13       0x3074
  73 #define RT2573_TXRX_CSR14       0x3078
  74 #define RT2573_TXRX_CSR15       0x307c
  75 #define RT2573_PHY_CSR0         0x3080
  76 #define RT2573_PHY_CSR1         0x3084
  77 #define RT2573_PHY_CSR2         0x3088
  78 #define RT2573_PHY_CSR3         0x308c
  79 #define RT2573_PHY_CSR4         0x3090
  80 #define RT2573_PHY_CSR5         0x3094
  81 #define RT2573_PHY_CSR6         0x3098
  82 #define RT2573_PHY_CSR7         0x309c
  83 #define RT2573_SEC_CSR0         0x30a0
  84 #define RT2573_SEC_CSR1         0x30a4
  85 #define RT2573_SEC_CSR2         0x30a8
  86 #define RT2573_SEC_CSR3         0x30ac
  87 #define RT2573_SEC_CSR4         0x30b0
  88 #define RT2573_SEC_CSR5         0x30b4
  89 #define RT2573_STA_CSR0         0x30c0
  90 #define RT2573_STA_CSR1         0x30c4
  91 #define RT2573_STA_CSR2         0x30c8
  92 #define RT2573_STA_CSR3         0x30cc
  93 #define RT2573_STA_CSR4         0x30d0
  94 #define RT2573_STA_CSR5         0x30d4
  95
  96
  97 /* possible flags for register RT2573_MAC_CSR1 */
  98 #define RT2573_RESET_ASIC       (1 << 0)
  99 #define RT2573_RESET_BBP        (1 << 1)
 100 #define RT2573_HOST_READY       (1 << 2)
 101
 102 /* possible flags for register MAC_CSR5 */
 103 #define RT2573_ONE_BSSID        3
 104
 105 /* possible flags for register TXRX_CSR0 */
 106 /* Tx filter flags are in the low 16 bits */
 107 #define RT2573_AUTO_TX_SEQ              (1 << 15)
 108 /* Rx filter flags are in the high 16 bits */
 109 #define RT2573_DISABLE_RX               (1 << 16)
 110 #define RT2573_DROP_CRC_ERROR           (1 << 17)
 111 #define RT2573_DROP_PHY_ERROR           (1 << 18)
 112 #define RT2573_DROP_CTL                 (1 << 19)
 113 #define RT2573_DROP_NOT_TO_ME           (1 << 20)
 114 #define RT2573_DROP_TODS                (1 << 21)
 115 #define RT2573_DROP_VER_ERROR           (1 << 22)
 116 #define RT2573_DROP_MULTICAST           (1 << 23)
 117 #define RT2573_DROP_BROADCAST           (1 << 24)
 118 #define RT2573_DROP_ACKCTS              (1 << 25)
 119
 120 /* possible flags for register TXRX_CSR4 */
 121 #define RT2573_SHORT_PREAMBLE   (1 << 18)
 122 #define RT2573_MRR_ENABLED      (1 << 19)
 123 #define RT2573_MRR_CCK_FALLBACK (1 << 22)
 124
 125 /* possible flags for register TXRX_CSR9 */
 126 #define RT2573_TSF_TICKING      (1 << 16)
 127 #define RT2573_TSF_MODE(x)      (((x) & 0x3) << 17)
 128 /* TBTT stands for Target Beacon Transmission Time */
 129 #define RT2573_ENABLE_TBTT      (1 << 19)
 130 #define RT2573_GENERATE_BEACON  (1 << 20)
 131
 132 /* possible flags for register PHY_CSR0 */
 133 #define RT2573_PA_PE_2GHZ       (1 << 16)
 134 #define RT2573_PA_PE_5GHZ       (1 << 17)
 135
 136 /* possible flags for register PHY_CSR3 */
 137 #define RT2573_BBP_READ (1 << 15)
 138 #define RT2573_BBP_BUSY (1 << 16)
 139 /* possible flags for register PHY_CSR4 */
 140 #define RT2573_RF_20BIT (20 << 24)
 141 #define RT2573_RF_BUSY  (1 << 31)
 142
 143 /* LED values */
 144 #define RT2573_LED_RADIO        (1 << 8)
 145 #define RT2573_LED_G            (1 << 9)
 146 #define RT2573_LED_A            (1 << 10)
 147 #define RT2573_LED_ON           0x1e1e
 148 #define RT2573_LED_OFF          0x0
 149
 150 #define RT2573_MCU_RUN  (1 << 3)
 151
 152 #define RT2573_SMART_MODE       (1 << 0)
 153
 154 #define RT2573_BBPR94_DEFAULT   6
 155
 156 #define RT2573_BBP_WRITE        (1 << 15)
 157
 158 /* dual-band RF */
 159 #define RT2573_RF_5226  1
 160 #define RT2573_RF_5225  3
 161 /* single-band RF */
 162 #define RT2573_RF_2528  2
 163 #define RT2573_RF_2527  4
 164
 165 #define RT2573_BBP_VERSION      0
 166
 167 struct rum_tx_desc {
 168         uint32_t        flags;
 169 #define RT2573_TX_BURST                 (1 << 0)
 170 #define RT2573_TX_VALID                 (1 << 1)
 171 #define RT2573_TX_MORE_FRAG             (1 << 2)
 172 #define RT2573_TX_NEED_ACK              (1 << 3)
 173 #define RT2573_TX_TIMESTAMP             (1 << 4)
 174 #define RT2573_TX_OFDM                  (1 << 5)
 175 #define RT2573_TX_IFS_SIFS              (1 << 6)
 176 #define RT2573_TX_LONG_RETRY            (1 << 7)
 177
 178         uint16_t        wme;
 179 #define RT2573_QID(v)           (v)
 180 #define RT2573_AIFSN(v)         ((v) << 4)
 181 #define RT2573_LOGCWMIN(v)      ((v) << 8)
 182 #define RT2573_LOGCWMAX(v)      ((v) << 12)
 183
 184         uint16_t        xflags;
 185 #define RT2573_TX_HWSEQ         (1 << 12)
 186
 187         uint8_t         plcp_signal;
 188         uint8_t         plcp_service;
 189 #define RT2573_PLCP_LENGEXT     0x80
 190
 191         uint8_t         plcp_length_lo;
 192         uint8_t         plcp_length_hi;
 193
 194         uint32_t        iv;
 195         uint32_t        eiv;
 196
 197         uint8_t         offset;
 198         uint8_t         qid;
 199         uint8_t         txpower;
 200 #define RT2573_DEFAULT_TXPOWER  0
 201
 202         uint8_t         reserved;
 203 } __packed;
 204
 205 struct rum_rx_desc {
 206         uint32_t        flags;
 207 #define RT2573_RX_BUSY          (1 << 0)
 208 #define RT2573_RX_DROP          (1 << 1)
 209 #define RT2573_RX_CRC_ERROR     (1 << 6)
 210 #define RT2573_RX_OFDM          (1 << 7)
 211
 212         uint8_t         rate;
 213         uint8_t         rssi;
 214         uint8_t         reserved1;
 215         uint8_t         offset;
 216         uint32_t        iv;
 217         uint32_t        eiv;
 218         uint32_t        reserved2[2];
 219 } __packed;
 220
 221 #define RT2573_RF1      0
 222 #define RT2573_RF2      2
 223 #define RT2573_RF3      1
 224 #define RT2573_RF4      3
 225
 226 #define RT2573_EEPROM_MACBBP            0x0000
 227 #define RT2573_EEPROM_ADDRESS           0x0004
 228 #define RT2573_EEPROM_ANTENNA           0x0020
 229 #define RT2573_EEPROM_CONFIG2           0x0022
 230 #define RT2573_EEPROM_BBP_BASE          0x0026
 231 #define RT2573_EEPROM_TXPOWER           0x0046
 232 #define RT2573_EEPROM_FREQ_OFFSET       0x005e
 233 #define RT2573_EEPROM_RSSI_2GHZ_OFFSET  0x009a
 234 #define RT2573_EEPROM_RSSI_5GHZ_OFFSET  0x009c
 235
 236 /*
 237  * Default values for MAC registers; values taken from the reference driver.
 238  */
 239 #define RT2573_DEF_MAC                          \
 240         { RT2573_TXRX_CSR0,  0x025fb032 },      \
 241         { RT2573_TXRX_CSR1,  0x9eaa9eaf },      \
 242         { RT2573_TXRX_CSR2,  0x8a8b8c8d },      \
 243         { RT2573_TXRX_CSR3,  0x00858687 },      \
 244         { RT2573_TXRX_CSR7,  0x2e31353b },      \
 245         { RT2573_TXRX_CSR8,  0x2a2a2a2c },      \
 246         { RT2573_TXRX_CSR15, 0x0000000f },      \
 247         { RT2573_MAC_CSR6,   0x00000fff },      \
 248         { RT2573_MAC_CSR8,   0x016c030a },      \
 249         { RT2573_MAC_CSR10,  0x00000718 },      \
 250         { RT2573_MAC_CSR12,  0x00000004 },      \
 251         { RT2573_MAC_CSR13,  0x00007f00 },      \
 252         { RT2573_SEC_CSR0,   0x00000000 },      \
 253         { RT2573_SEC_CSR1,   0x00000000 },      \
 254         { RT2573_SEC_CSR5,   0x00000000 },      \
 255         { RT2573_PHY_CSR1,   0x000023b0 },      \
 256         { RT2573_PHY_CSR5,   0x00040a06 },      \
 257         { RT2573_PHY_CSR6,   0x00080606 },      \
 258         { RT2573_PHY_CSR7,   0x00000408 },      \
 259         { RT2573_AIFSN_CSR,  0x00002273 },      \
 260         { RT2573_CWMIN_CSR,  0x00002344 },      \
 261         { RT2573_CWMAX_CSR,  0x000034aa }
 262
 263 /*
 264  * Default values for BBP registers; values taken from the reference driver.
 265  */
 266 #define RT2573_DEF_BBP  \
 267         {   3, 0x80 },  \
 268         {  15, 0x30 },  \
 269         {  17, 0x20 },  \
 270         {  21, 0xc8 },  \
 271         {  22, 0x38 },  \
 272         {  23, 0x06 },  \
 273         {  24, 0xfe },  \
 274         {  25, 0x0a },  \
 275         {  26, 0x0d },  \
 276         {  32, 0x0b },  \
 277         {  34, 0x12 },  \
 278         {  37, 0x07 },  \
 279         {  39, 0xf8 },  \
 280         {  41, 0x60 },  \
 281         {  53, 0x10 },  \
 282         {  54, 0x18 },  \
 283         {  60, 0x10 },  \
 284         {  61, 0x04 },  \
 285         {  62, 0x04 },  \
 286         {  75, 0xfe },  \
 287         {  86, 0xfe },  \
 288         {  88, 0xfe },  \
 289         {  90, 0x0f },  \
 290         {  99, 0x00 },  \
 291         { 102, 0x16 },  \
 292         { 107, 0x04 }
 293
 294 /*
 295  * Default settings for RF registers; values taken from the reference driver.
 296  */
 297 #define RT2573_RF5226                                   \
 298         {   1, 0x00b03, 0x001e1, 0x1a014, 0x30282 },    \
 299         {   2, 0x00b03, 0x001e1, 0x1a014, 0x30287 },    \
 300         {   3, 0x00b03, 0x001e2, 0x1a014, 0x30282 },    \
 301         {   4, 0x00b03, 0x001e2, 0x1a014, 0x30287 },    \
 302         {   5, 0x00b03, 0x001e3, 0x1a014, 0x30282 },    \
 303         {   6, 0x00b03, 0x001e3, 0x1a014, 0x30287 },    \
 304         {   7, 0x00b03, 0x001e4, 0x1a014, 0x30282 },    \
 305         {   8, 0x00b03, 0x001e4, 0x1a014, 0x30287 },    \
 306         {   9, 0x00b03, 0x001e5, 0x1a014, 0x30282 },    \
 307         {  10, 0x00b03, 0x001e5, 0x1a014, 0x30287 },    \
 308         {  11, 0x00b03, 0x001e6, 0x1a014, 0x30282 },    \
 309         {  12, 0x00b03, 0x001e6, 0x1a014, 0x30287 },    \
 310         {  13, 0x00b03, 0x001e7, 0x1a014, 0x30282 },    \
 311         {  14, 0x00b03, 0x001e8, 0x1a014, 0x30284 },    \
 312                                                         \
 313         {  34, 0x00b03, 0x20266, 0x36014, 0x30282 },    \
 314         {  38, 0x00b03, 0x20267, 0x36014, 0x30284 },    \
 315         {  42, 0x00b03, 0x20268, 0x36014, 0x30286 },    \
 316         {  46, 0x00b03, 0x20269, 0x36014, 0x30288 },    \
 317                                                         \
 318         {  36, 0x00b03, 0x00266, 0x26014, 0x30288 },    \
 319         {  40, 0x00b03, 0x00268, 0x26014, 0x30280 },    \
 320         {  44, 0x00b03, 0x00269, 0x26014, 0x30282 },    \
 321         {  48, 0x00b03, 0x0026a, 0x26014, 0x30284 },    \
 322         {  52, 0x00b03, 0x0026b, 0x26014, 0x30286 },    \
 323         {  56, 0x00b03, 0x0026c, 0x26014, 0x30288 },    \
 324         {  60, 0x00b03, 0x0026e, 0x26014, 0x30280 },    \
 325         {  64, 0x00b03, 0x0026f, 0x26014, 0x30282 },    \
 326                                                         \
 327         { 100, 0x00b03, 0x0028a, 0x2e014, 0x30280 },    \
 328         { 104, 0x00b03, 0x0028b, 0x2e014, 0x30282 },    \
 329         { 108, 0x00b03, 0x0028c, 0x2e014, 0x30284 },    \
 330         { 112, 0x00b03, 0x0028d, 0x2e014, 0x30286 },    \
 331         { 116, 0x00b03, 0x0028e, 0x2e014, 0x30288 },    \
 332         { 120, 0x00b03, 0x002a0, 0x2e014, 0x30280 },    \
 333         { 124, 0x00b03, 0x002a1, 0x2e014, 0x30282 },    \
 334         { 128, 0x00b03, 0x002a2, 0x2e014, 0x30284 },    \
 335         { 132, 0x00b03, 0x002a3, 0x2e014, 0x30286 },    \
 336         { 136, 0x00b03, 0x002a4, 0x2e014, 0x30288 },    \
 337         { 140, 0x00b03, 0x002a6, 0x2e014, 0x30280 },    \
 338                                                         \
 339         { 149, 0x00b03, 0x002a8, 0x2e014, 0x30287 },    \
 340         { 153, 0x00b03, 0x002a9, 0x2e014, 0x30289 },    \
 341         { 157, 0x00b03, 0x002ab, 0x2e014, 0x30281 },    \
 342         { 161, 0x00b03, 0x002ac, 0x2e014, 0x30283 },    \
 343         { 165, 0x00b03, 0x002ad, 0x2e014, 0x30285 }
 344
 345 #define RT2573_RF5225                                   \
 346         {   1, 0x00b33, 0x011e1, 0x1a014, 0x30282 },    \
 347         {   2, 0x00b33, 0x011e1, 0x1a014, 0x30287 },    \
 348         {   3, 0x00b33, 0x011e2, 0x1a014, 0x30282 },    \
 349         {   4, 0x00b33, 0x011e2, 0x1a014, 0x30287 },    \
 350         {   5, 0x00b33, 0x011e3, 0x1a014, 0x30282 },    \
 351         {   6, 0x00b33, 0x011e3, 0x1a014, 0x30287 },    \
 352         {   7, 0x00b33, 0x011e4, 0x1a014, 0x30282 },    \
 353         {   8, 0x00b33, 0x011e4, 0x1a014, 0x30287 },    \
 354         {   9, 0x00b33, 0x011e5, 0x1a014, 0x30282 },    \
 355         {  10, 0x00b33, 0x011e5, 0x1a014, 0x30287 },    \
 356         {  11, 0x00b33, 0x011e6, 0x1a014, 0x30282 },    \
 357         {  12, 0x00b33, 0x011e6, 0x1a014, 0x30287 },    \
 358         {  13, 0x00b33, 0x011e7, 0x1a014, 0x30282 },    \
 359         {  14, 0x00b33, 0x011e8, 0x1a014, 0x30284 },    \
 360                                                         \
 361         {  34, 0x00b33, 0x01266, 0x26014, 0x30282 },    \
 362         {  38, 0x00b33, 0x01267, 0x26014, 0x30284 },    \
 363         {  42, 0x00b33, 0x01268, 0x26014, 0x30286 },    \
 364         {  46, 0x00b33, 0x01269, 0x26014, 0x30288 },    \
 365                                                         \
 366         {  36, 0x00b33, 0x01266, 0x26014, 0x30288 },    \
 367         {  40, 0x00b33, 0x01268, 0x26014, 0x30280 },    \
 368         {  44, 0x00b33, 0x01269, 0x26014, 0x30282 },    \
 369         {  48, 0x00b33, 0x0126a, 0x26014, 0x30284 },    \
 370         {  52, 0x00b33, 0x0126b, 0x26014, 0x30286 },    \
 371         {  56, 0x00b33, 0x0126c, 0x26014, 0x30288 },    \
 372         {  60, 0x00b33, 0x0126e, 0x26014, 0x30280 },    \
 373         {  64, 0x00b33, 0x0126f, 0x26014, 0x30282 },    \
 374                                                         \
 375         { 100, 0x00b33, 0x0128a, 0x2e014, 0x30280 },    \
 376         { 104, 0x00b33, 0x0128b, 0x2e014, 0x30282 },    \
 377         { 108, 0x00b33, 0x0128c, 0x2e014, 0x30284 },    \
 378         { 112, 0x00b33, 0x0128d, 0x2e014, 0x30286 },    \
 379         { 116, 0x00b33, 0x0128e, 0x2e014, 0x30288 },    \
 380         { 120, 0x00b33, 0x012a0, 0x2e014, 0x30280 },    \
 381         { 124, 0x00b33, 0x012a1, 0x2e014, 0x30282 },    \
 382         { 128, 0x00b33, 0x012a2, 0x2e014, 0x30284 },    \
 383         { 132, 0x00b33, 0x012a3, 0x2e014, 0x30286 },    \
 384         { 136, 0x00b33, 0x012a4, 0x2e014, 0x30288 },    \
 385         { 140, 0x00b33, 0x012a6, 0x2e014, 0x30280 },    \
 386                                                         \
 387         { 149, 0x00b33, 0x012a8, 0x2e014, 0x30287 },    \
 388         { 153, 0x00b33, 0x012a9, 0x2e014, 0x30289 },    \
 389         { 157, 0x00b33, 0x012ab, 0x2e014, 0x30281 },    \
 390         { 161, 0x00b33, 0x012ac, 0x2e014, 0x30283 },    \
 391         { 165, 0x00b33, 0x012ad, 0x2e014, 0x30285 }