sys/dev/usb/uhcireg.h

   1 /*      $NetBSD: uhcireg.h,v 1.18 2006/10/08 11:52:48 scw Exp $ */
   2 /*      $FreeBSD: src/sys/dev/usb/uhcireg.h,v 1.12 1999/11/17 22:33:42 n_hibma Exp $ */
   3
   4 /*
   5  * Copyright (c) 1998 The NetBSD Foundation, Inc.
   6  * All rights reserved.
   7  *
   8  * This code is derived from software contributed to The NetBSD Foundation
   9  * by Lennart Augustsson (lennart@augustsson.net) at
  10  * Carlstedt Research & Technology.
  11  *
  12  * Redistribution and use in source and binary forms, with or without
  13  * modification, are permitted provided that the following conditions
  14  * are met:
  15  * 1. Redistributions of source code must retain the above copyright
  16  *    notice, this list of conditions and the following disclaimer.
  17  * 2. Redistributions in binary form must reproduce the above copyright
  18  *    notice, this list of conditions and the following disclaimer in the
  19  *    documentation and/or other materials provided with the distribution.
  20  *
  21  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
  22  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  23  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  24  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
  25  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  26  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  27  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  28  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  29  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  30  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  31  * POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #ifndef _DEV_PCI_UHCIREG_H_
  35 #define _DEV_PCI_UHCIREG_H_
  36
  37 /*** PCI config registers ***/
  38
  39 #define PCI_USBREV              0x60    /* USB protocol revision */
  40 #define  PCI_USBREV_MASK        0xff
  41 #define  PCI_USBREV_PRE_1_0     0x00
  42 #define  PCI_USBREV_1_0         0x10
  43 #define  PCI_USBREV_1_1         0x11
  44
  45 #define PCI_LEGSUP              0xc0    /* Legacy Support register */
  46 #define  PCI_LEGSUP_A20PTS      0x8000  /* End of A20GATE passthru status */
  47 #define  PCI_LEGSUP_USBPIRQDEN  0x2000  /* USB PIRQ D Enable */
  48 #define  PCI_LEGSUP_USBIRQS     0x1000  /* USB IRQ status */
  49 #define  PCI_LEGSUP_TBY64W      0x0800  /* Trap by 64h write status */
  50 #define  PCI_LEGSUP_TBY64R      0x0400  /* Trap by 64h read status */
  51 #define  PCI_LEGSUP_TBY60W      0x0200  /* Trap by 60h write status */
  52 #define  PCI_LEGSUP_TBY60R      0x0100  /* Trap by 60h read status */
  53 #define  PCI_LEGSUP_SMIEPTE     0x0080  /* SMI at end of passthru enable */
  54 #define  PCI_LEGSUP_PSS         0x0040  /* Passthru status */
  55 #define  PCI_LEGSUP_A20PTEN     0x0020  /* A20GATE passthru enable */
  56 #define  PCI_LEGSUP_USBSMIEN    0x0010  /* Enable SMI# generation */
  57
  58 #define PCI_CBIO                0x20    /* configuration base IO */
  59
  60 #define PCI_INTERFACE_UHCI      0x00
  61
  62 /*** UHCI registers ***/
  63
  64 #define UHCI_CMD                0x00
  65 #define  UHCI_CMD_RS            0x0001
  66 #define  UHCI_CMD_HCRESET       0x0002
  67 #define  UHCI_CMD_GRESET        0x0004
  68 #define  UHCI_CMD_EGSM          0x0008
  69 #define  UHCI_CMD_FGR           0x0010
  70 #define  UHCI_CMD_SWDBG         0x0020
  71 #define  UHCI_CMD_CF            0x0040
  72 #define  UHCI_CMD_MAXP          0x0080
  73
  74 #define UHCI_STS                0x02
  75 #define  UHCI_STS_USBINT        0x0001
  76 #define  UHCI_STS_USBEI         0x0002
  77 #define  UHCI_STS_RD            0x0004
  78 #define  UHCI_STS_HSE           0x0008
  79 #define  UHCI_STS_HCPE          0x0010
  80 #define  UHCI_STS_HCH           0x0020
  81 #define  UHCI_STS_ALLINTRS      0x003f
  82
  83 #define UHCI_INTR               0x04
  84 #define  UHCI_INTR_TOCRCIE      0x0001
  85 #define  UHCI_INTR_RIE          0x0002
  86 #define  UHCI_INTR_IOCE         0x0004
  87 #define  UHCI_INTR_SPIE         0x0008
  88
  89 #define UHCI_FRNUM              0x06
  90 #define  UHCI_FRNUM_MASK        0x03ff
  91
  92
  93 #define UHCI_FLBASEADDR         0x08
  94
  95 #define UHCI_SOF                0x0c
  96 #define  UHCI_SOF_MASK          0x7f
  97
  98 #define UHCI_PORTSC1            0x010
  99 #define UHCI_PORTSC2            0x012
 100 #define UHCI_PORTSC_CCS         0x0001
 101 #define UHCI_PORTSC_CSC         0x0002
 102 #define UHCI_PORTSC_PE          0x0004
 103 #define UHCI_PORTSC_POEDC       0x0008
 104 #define UHCI_PORTSC_LS          0x0030
 105 #define UHCI_PORTSC_LS_SHIFT    4
 106 #define UHCI_PORTSC_RD          0x0040
 107 #define UHCI_PORTSC_LSDA        0x0100
 108 #define UHCI_PORTSC_PR          0x0200
 109 #define UHCI_PORTSC_OCI         0x0400
 110 #define UHCI_PORTSC_OCIC        0x0800
 111 #define UHCI_PORTSC_SUSP        0x1000
 112
 113 #define URWMASK(x) \
 114   ((x) & (UHCI_PORTSC_SUSP | UHCI_PORTSC_PR | UHCI_PORTSC_RD | UHCI_PORTSC_PE))
 115
 116 #define UHCI_FRAMELIST_COUNT    1024
 117 #define UHCI_FRAMELIST_ALIGN    4096
 118
 119 #define UHCI_TD_ALIGN           16
 120 #define UHCI_QH_ALIGN           16
 121
 122 typedef u_int32_t uhci_physaddr_t;
 123 #define UHCI_PTR_T              0x00000001
 124 #define UHCI_PTR_TD             0x00000000
 125 #define UHCI_PTR_QH             0x00000002
 126 #define UHCI_PTR_VF             0x00000004
 127
 128 /*
 129  * Wait this long after a QH has been removed.  This gives that HC a
 130  * chance to stop looking at it before it's recycled.
 131  */
 132 #define UHCI_QH_REMOVE_DELAY    5
 133
 134 /*
 135  * The Queue Heads and Transfer Descriptors are accessed
 136  * by both the CPU and the USB controller which run
 137  * concurrently.  This means that they have to be accessed
 138  * with great care.  As long as the data structures are
 139  * not linked into the controller's frame list they cannot
 140  * be accessed by it and anything goes.  As soon as a
 141  * TD is accessible by the controller it "owns" the td_status
 142  * field; it will not be written by the CPU.  Similarly
 143  * the controller "owns" the qh_elink field.
 144  */
 145
 146 typedef struct {
 147         volatile uhci_physaddr_t td_link;
 148         volatile u_int32_t td_status;
 149 #define UHCI_TD_GET_ACTLEN(s)   (((s) + 1) & 0x3ff)
 150 #define UHCI_TD_ZERO_ACTLEN(t)  ((t) | 0x3ff)
 151 #define UHCI_TD_BITSTUFF        0x00020000
 152 #define UHCI_TD_CRCTO           0x00040000
 153 #define UHCI_TD_NAK             0x00080000
 154 #define UHCI_TD_BABBLE          0x00100000
 155 #define UHCI_TD_DBUFFER         0x00200000
 156 #define UHCI_TD_STALLED         0x00400000
 157 #define UHCI_TD_ACTIVE          0x00800000
 158 #define UHCI_TD_IOC             0x01000000
 159 #define UHCI_TD_IOS             0x02000000
 160 #define UHCI_TD_LS              0x04000000
 161 #define UHCI_TD_GET_ERRCNT(s)   (((s) >> 27) & 3)
 162 #define UHCI_TD_SET_ERRCNT(n)   ((n) << 27)
 163 #define UHCI_TD_SPD             0x20000000
 164         volatile u_int32_t td_token;
 165 #define UHCI_TD_PID_IN          0x00000069
 166 #define UHCI_TD_PID_OUT         0x000000e1
 167 #define UHCI_TD_PID_SETUP       0x0000002d
 168 #define UHCI_TD_GET_PID(s)      ((s) & 0xff)
 169 #define UHCI_TD_SET_DEVADDR(a)  ((a) << 8)
 170 #define UHCI_TD_GET_DEVADDR(s)  (((s) >> 8) & 0x7f)
 171 #define UHCI_TD_SET_ENDPT(e)    (((e)&0xf) << 15)
 172 #define UHCI_TD_GET_ENDPT(s)    (((s) >> 15) & 0xf)
 173 #define UHCI_TD_SET_DT(t)       ((t) << 19)
 174 #define UHCI_TD_GET_DT(s)       (((s) >> 19) & 1)
 175 #define UHCI_TD_SET_MAXLEN(l)   (((l)-1) << 21)
 176 #define UHCI_TD_GET_MAXLEN(s)   ((((s) >> 21) + 1) & 0x7ff)
 177 #define UHCI_TD_MAXLEN_MASK     0xffe00000
 178         volatile u_int32_t td_buffer;
 179 } uhci_td_t;
 180
 181 #define UHCI_TD_ERROR (UHCI_TD_BITSTUFF|UHCI_TD_CRCTO|UHCI_TD_BABBLE|UHCI_TD_DBUFFER|UHCI_TD_STALLED)
 182
 183 #define UHCI_TD_SETUP(len, endp, dev) (UHCI_TD_SET_MAXLEN(len) | \
 184      UHCI_TD_SET_ENDPT(endp) | UHCI_TD_SET_DEVADDR(dev) | UHCI_TD_PID_SETUP)
 185 #define UHCI_TD_OUT(len, endp, dev, dt) (UHCI_TD_SET_MAXLEN(len) | \
 186      UHCI_TD_SET_ENDPT(endp) | UHCI_TD_SET_DEVADDR(dev) | \
 187      UHCI_TD_PID_OUT | UHCI_TD_SET_DT(dt))
 188 #define UHCI_TD_IN(len, endp, dev, dt) (UHCI_TD_SET_MAXLEN(len) | \
 189      UHCI_TD_SET_ENDPT(endp) | UHCI_TD_SET_DEVADDR(dev) | UHCI_TD_PID_IN | \
 190      UHCI_TD_SET_DT(dt))
 191
 192 typedef struct {
 193         volatile uhci_physaddr_t qh_hlink;
 194         volatile uhci_physaddr_t qh_elink;
 195 } uhci_qh_t;
 196
 197 #endif /* _DEV_PCI_UHCIREG_H_ */