sys/external/bsd/drm/dist/shared-core/i915_irq.c

   1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #include "drmP.h"
  30 #include "drm.h"
  31 #include "i915_drm.h"
  32 #include "i915_drv.h"
  33
  34 #define MAX_NOPID ((u32)~0)
  35
  36 /**
  37  * Interrupts that are always left unmasked.
  38  *
  39  * Since pipe events are edge-triggered from the PIPESTAT register to IIR,
  40  * we leave them always unmasked in IMR and then control enabling them through
  41  * PIPESTAT alone.
  42  */
  43 #define I915_INTERRUPT_ENABLE_FIX (I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | \
  44                                    I915_DISPLAY_PIPE_B_EVENT_INTERRUPT)
  45
  46 /** Interrupts that we mask and unmask at runtime. */
  47 #define I915_INTERRUPT_ENABLE_VAR (I915_USER_INTERRUPT)
  48
  49 /** These are all of the interrupts used by the driver */
  50 #define I915_INTERRUPT_ENABLE_MASK (I915_INTERRUPT_ENABLE_FIX | \
  51                                     I915_INTERRUPT_ENABLE_VAR)
  52
  53 static inline void
  54 i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask)
  55 {
  56         DRM_DEBUG("irq_enable_reg = 0x%08x, mask = 0x%08x\n",
  57             dev_priv->irq_mask_reg, mask);
  58         mask &= I915_INTERRUPT_ENABLE_VAR;
  59         if ((dev_priv->irq_mask_reg & mask) != 0) {
  60                 dev_priv->irq_mask_reg &= ~mask;
  61                 I915_WRITE(IMR, dev_priv->irq_mask_reg);
  62                 (void) I915_READ(IMR);
  63         }
  64 }
  65
  66 static inline void
  67 i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask)
  68 {
  69         mask &= I915_INTERRUPT_ENABLE_VAR;
  70         if ((dev_priv->irq_mask_reg & mask) != mask) {
  71                 dev_priv->irq_mask_reg |= mask;
  72                 I915_WRITE(IMR, dev_priv->irq_mask_reg);
  73                 (void) I915_READ(IMR);
  74         }
  75 }
  76
  77 static inline u32
  78 i915_pipestat(int pipe)
  79 {
  80         if (pipe == 0)
  81             return PIPEASTAT;
  82         if (pipe == 1)
  83             return PIPEBSTAT;
  84         return -EINVAL;
  85 }
  86
  87 void
  88 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
  89 {
  90         if ((dev_priv->pipestat[pipe] & mask) != mask) {
  91                 u32 reg = i915_pipestat(pipe);
  92
  93                 dev_priv->pipestat[pipe] |= mask;
  94                 /* Enable the interrupt, clear any pending status */
  95                 I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16));
  96                 (void) I915_READ(reg);
  97         }
  98 }
  99
 100 void
 101 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
 102 {
 103         if ((dev_priv->pipestat[pipe] & mask) != 0) {
 104                 u32 reg = i915_pipestat(pipe);
 105
 106                 dev_priv->pipestat[pipe] &= ~mask;
 107                 I915_WRITE(reg, dev_priv->pipestat[pipe]);
 108                 (void) I915_READ(reg);
 109         }
 110 }
 111
 112 /**
 113  * i915_pipe_enabled - check if a pipe is enabled
 114  * @dev: DRM device
 115  * @pipe: pipe to check
 116  *
 117  * Reading certain registers when the pipe is disabled can hang the chip.
 118  * Use this routine to make sure the PLL is running and the pipe is active
 119  * before reading such registers if unsure.
 120  */
 121 static int
 122 i915_pipe_enabled(struct drm_device *dev, int pipe)
 123 {
 124         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 125         unsigned long pipeconf = pipe ? PIPEBCONF : PIPEACONF;
 126
 127         if (I915_READ(pipeconf) & PIPEACONF_ENABLE)
 128                 return 1;
 129
 130         return 0;
 131 }
 132
 133 /* Called from drm generic code, passed a 'crtc', which
 134  * we use as a pipe index
 135  */
 136 u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
 137 {
 138         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 139         unsigned long high_frame;
 140         unsigned long low_frame;
 141         u32 high1, high2, low, count;
 142
 143         high_frame = pipe ? PIPEBFRAMEHIGH : PIPEAFRAMEHIGH;
 144         low_frame = pipe ? PIPEBFRAMEPIXEL : PIPEAFRAMEPIXEL;
 145
 146         if (!i915_pipe_enabled(dev, pipe)) {
 147                 DRM_ERROR("trying to get vblank count for disabled pipe %d\n", pipe);
 148                 return 0;
 149         }
 150
 151         /*
 152          * High & low register fields aren't synchronized, so make sure
 153          * we get a low value that's stable across two reads of the high
 154          * register.
 155          */
 156         do {
 157                 high1 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
 158                          PIPE_FRAME_HIGH_SHIFT);
 159                 low =  ((I915_READ(low_frame) & PIPE_FRAME_LOW_MASK) >>
 160                         PIPE_FRAME_LOW_SHIFT);
 161                 high2 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
 162                          PIPE_FRAME_HIGH_SHIFT);
 163         } while (high1 != high2);
 164
 165         count = (high1 << 8) | low;
 166
 167         return count;
 168 }
 169
 170 u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
 171 {
 172         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 173         int reg = pipe ? PIPEB_FRMCOUNT_GM45 : PIPEA_FRMCOUNT_GM45;
 174
 175         if (!i915_pipe_enabled(dev, pipe)) {
 176                 DRM_ERROR("trying to get vblank count for disabled pipe %d\n", pipe);
 177                 return 0;
 178         }
 179
 180         return I915_READ(reg);
 181 }
 182
 183 irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
 184 {
 185         struct drm_device *dev = (struct drm_device *) arg;
 186         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 187         u32 iir;
 188         u32 pipea_stats, pipeb_stats;
 189
 190         atomic_inc(&dev_priv->irq_received);
 191
 192         iir = I915_READ(IIR);
 193         if (!iir)
 194                 return IRQ_NONE;
 195
 196         pipea_stats = pipeb_stats = 0;
 197
 198         /*
 199          * Clear the PIPE(A|B)STAT regs before the IIR
 200          */
 201         if (iir & I915_DISPLAY_PIPE_A_EVENT_INTERRUPT) {
 202                 DRM_SPINLOCK(&dev_priv->user_irq_lock);
 203                 pipea_stats = I915_READ(PIPEASTAT);
 204                 I915_WRITE(PIPEASTAT, pipea_stats);
 205                 DRM_SPINUNLOCK(&dev_priv->user_irq_lock);
 206         }
 207
 208         if (iir & I915_DISPLAY_PIPE_B_EVENT_INTERRUPT) {
 209                 DRM_SPINLOCK(&dev_priv->user_irq_lock);
 210                 pipeb_stats = I915_READ(PIPEBSTAT);
 211                 I915_WRITE(PIPEBSTAT, pipeb_stats);
 212                 DRM_SPINUNLOCK(&dev_priv->user_irq_lock);
 213         }
 214
 215         I915_WRITE(IIR, iir);
 216
 217         DRM_DEBUG("iir = 0x%08x, pipestats a = 0x%08x, b = 0x%08x\n",
 218             iir, pipea_stats, pipeb_stats);
 219
 220         if (dev_priv->sarea_priv)
 221                 dev_priv->sarea_priv->last_dispatch =
 222                     READ_BREADCRUMB(dev_priv);
 223
 224         if (iir & I915_USER_INTERRUPT) {
 225 #ifdef I915_HAVE_GEM
 226                 dev_priv->mm.irq_gem_seqno = i915_get_gem_seqno(dev);
 227 #endif
 228                 DRM_WAKEUP(&dev_priv->irq_queue);
 229         }
 230
 231         if (pipea_stats & (PIPE_START_VBLANK_INTERRUPT_STATUS |
 232             PIPE_VBLANK_INTERRUPT_STATUS))
 233                 drm_handle_vblank(dev, 0);
 234
 235         if (pipeb_stats & (PIPE_START_VBLANK_INTERRUPT_STATUS |
 236             PIPE_VBLANK_INTERRUPT_STATUS))
 237                 drm_handle_vblank(dev, 1);
 238 #ifdef __linux__
 239         if ((pipeb_stats & I915_LEGACY_BLC_EVENT_STATUS) ||
 240             (iir & I915_ASLE_INTERRUPT))
 241                 opregion_asle_intr(dev);
 242 #endif
 243
 244         return IRQ_HANDLED;
 245 }
 246
 247 static int i915_emit_irq(struct drm_device * dev)
 248 {
 249         drm_i915_private_t *dev_priv = dev->dev_private;
 250         RING_LOCALS;
 251
 252         i915_kernel_lost_context(dev);
 253
 254         DRM_DEBUG("\n");
 255
 256         dev_priv->counter++;
 257         if (dev_priv->counter > 0x7FFFFFFFUL)
 258                 dev_priv->counter = 1;
 259         if (dev_priv->sarea_priv)
 260                 dev_priv->sarea_priv->last_enqueue = dev_priv->counter;
 261
 262         BEGIN_LP_RING(4);
 263         OUT_RING(MI_STORE_DWORD_INDEX);
 264         OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 265         OUT_RING(dev_priv->counter);
 266         OUT_RING(MI_USER_INTERRUPT);
 267         ADVANCE_LP_RING();
 268
 269         return dev_priv->counter;
 270 }
 271
 272 void i915_user_irq_get(struct drm_device *dev)
 273 {
 274         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 275         unsigned long irqflags;
 276
 277         DRM_DEBUG("\n");
 278         DRM_SPINLOCK_IRQSAVE(&dev_priv->user_irq_lock, irqflags);
 279         if (dev->irq_enabled && (++dev_priv->user_irq_refcount == 1))
 280                 i915_enable_irq(dev_priv, I915_USER_INTERRUPT);
 281         DRM_SPINUNLOCK_IRQRESTORE(&dev_priv->user_irq_lock, irqflags);
 282 }
 283
 284 void i915_user_irq_put(struct drm_device *dev)
 285 {
 286         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 287         unsigned long irqflags;
 288
 289         DRM_SPINLOCK_IRQSAVE(&dev_priv->user_irq_lock, irqflags);
 290 #ifdef __linux__
 291         BUG_ON(dev->irq_enabled && dev_priv->user_irq_refcount <= 0);
 292 #endif
 293         if (dev->irq_enabled && (--dev_priv->user_irq_refcount == 0))
 294                 i915_disable_irq(dev_priv, I915_USER_INTERRUPT);
 295         DRM_SPINUNLOCK_IRQRESTORE(&dev_priv->user_irq_lock, irqflags);
 296 }
 297
 298 static int i915_wait_irq(struct drm_device * dev, int irq_nr)
 299 {
 300         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 301         int ret = 0;
 302
 303         DRM_DEBUG("irq_nr=%d breadcrumb=%d\n", irq_nr,
 304                   READ_BREADCRUMB(dev_priv));
 305
 306         if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
 307                 if (dev_priv->sarea_priv) {
 308                         dev_priv->sarea_priv->last_dispatch =
 309                                 READ_BREADCRUMB(dev_priv);
 310                 }
 311                 return 0;
 312         }
 313
 314         if (dev_priv->sarea_priv)
 315                 dev_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
 316
 317         i915_user_irq_get(dev);
 318         DRM_WAIT_ON(ret, dev_priv->irq_queue, 3 * DRM_HZ,
 319                     READ_BREADCRUMB(dev_priv) >= irq_nr);
 320         i915_user_irq_put(dev);
 321
 322         if (ret == -EBUSY) {
 323                 DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
 324                           READ_BREADCRUMB(dev_priv), (int)dev_priv->counter);
 325         }
 326
 327         if (dev_priv->sarea_priv)
 328                 dev_priv->sarea_priv->last_dispatch =
 329                         READ_BREADCRUMB(dev_priv);
 330
 331         return ret;
 332 }
 333
 334 /* Needs the lock as it touches the ring.
 335  */
 336 int i915_irq_emit(struct drm_device *dev, void *data,
 337                          struct drm_file *file_priv)
 338 {
 339         drm_i915_private_t *dev_priv = dev->dev_private;
 340         drm_i915_irq_emit_t *emit = data;
 341         int result;
 342
 343         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 344
 345         if (!dev_priv) {
 346                 DRM_ERROR("called with no initialization\n");
 347                 return -EINVAL;
 348         }
 349
 350         result = i915_emit_irq(dev);
 351
 352         if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) {
 353                 DRM_ERROR("copy_to_user\n");
 354                 return -EFAULT;
 355         }
 356
 357         return 0;
 358 }
 359
 360 /* Doesn't need the hardware lock.
 361  */
 362 int i915_irq_wait(struct drm_device *dev, void *data,
 363                          struct drm_file *file_priv)
 364 {
 365         drm_i915_private_t *dev_priv = dev->dev_private;
 366         drm_i915_irq_wait_t *irqwait = data;
 367
 368         if (!dev_priv) {
 369                 DRM_ERROR("called with no initialization\n");
 370                 return -EINVAL;
 371         }
 372
 373         return i915_wait_irq(dev, irqwait->irq_seq);
 374 }
 375
 376 /* Called from drm generic code, passed 'crtc' which
 377  * we use as a pipe index
 378  */
 379 int i915_enable_vblank(struct drm_device *dev, int pipe)
 380 {
 381         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 382         unsigned long irqflags;
 383         u32 pipestat;
 384
 385         /*
 386          * Older chips didn't have the start vblank interrupt,
 387          * but
 388          */
 389         if (IS_I965G (dev))
 390                 pipestat = PIPE_START_VBLANK_INTERRUPT_ENABLE;
 391         else
 392                 pipestat = PIPE_VBLANK_INTERRUPT_ENABLE;
 393
 394         DRM_SPINLOCK_IRQSAVE(&dev_priv->user_irq_lock, irqflags);
 395         i915_enable_pipestat(dev_priv, pipe, pipestat);
 396         DRM_SPINUNLOCK_IRQRESTORE(&dev_priv->user_irq_lock, irqflags);
 397         return 0;
 398 }
 399
 400 /* Called from drm generic code, passed 'crtc' which
 401  * we use as a pipe index
 402  */
 403 void i915_disable_vblank(struct drm_device *dev, int pipe)
 404 {
 405         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 406         unsigned long irqflags;
 407
 408         DRM_SPINLOCK_IRQSAVE(&dev_priv->user_irq_lock, irqflags);
 409         i915_disable_pipestat(dev_priv, pipe,
 410             PIPE_START_VBLANK_INTERRUPT_ENABLE | PIPE_VBLANK_INTERRUPT_ENABLE);
 411         DRM_SPINUNLOCK_IRQRESTORE(&dev_priv->user_irq_lock, irqflags);
 412 }
 413
 414 /* Set the vblank monitor pipe
 415  */
 416 int i915_vblank_pipe_set(struct drm_device *dev, void *data,
 417                          struct drm_file *file_priv)
 418 {
 419         drm_i915_private_t *dev_priv = dev->dev_private;
 420
 421         if (!dev_priv) {
 422                 DRM_ERROR("called with no initialization\n");
 423                 return -EINVAL;
 424         }
 425
 426         return 0;
 427 }
 428
 429 int i915_vblank_pipe_get(struct drm_device *dev, void *data,
 430                          struct drm_file *file_priv)
 431 {
 432         drm_i915_private_t *dev_priv = dev->dev_private;
 433         drm_i915_vblank_pipe_t *pipe = data;
 434
 435         if (!dev_priv) {
 436                 DRM_ERROR("called with no initialization\n");
 437                 return -EINVAL;
 438         }
 439
 440         pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
 441
 442         return 0;
 443 }
 444
 445 /**
 446  * Schedule buffer swap at given vertical blank.
 447  */
 448 int i915_vblank_swap(struct drm_device *dev, void *data,
 449                      struct drm_file *file_priv)
 450 {
 451         /* The delayed swap mechanism was fundamentally racy, and has been
 452          * removed.  The model was that the client requested a delayed flip/swap
 453          * from the kernel, then waited for vblank before continuing to perform
 454          * rendering.  The problem was that the kernel might wake the client
 455          * up before it dispatched the vblank swap (since the lock has to be
 456          * held while touching the ringbuffer), in which case the client would
 457          * clear and start the next frame before the swap occurred, and
 458          * flicker would occur in addition to likely missing the vblank.
 459          *
 460          * In the absence of this ioctl, userland falls back to a correct path
 461          * of waiting for a vblank, then dispatching the swap on its own.
 462          * Context switching to userland and back is plenty fast enough for
 463          * meeting the requirements of vblank swapping.
 464          */
 465
 466         return -EINVAL;
 467 }
 468
 469 /* drm_dma.h hooks
 470 */
 471 void i915_driver_irq_preinstall(struct drm_device * dev)
 472 {
 473         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 474
 475         I915_WRITE(HWSTAM, 0xeffe);
 476         I915_WRITE(PIPEASTAT, 0);
 477         I915_WRITE(PIPEBSTAT, 0);
 478         I915_WRITE(IMR, 0xffffffff);
 479         I915_WRITE(IER, 0x0);
 480         (void) I915_READ(IER);
 481 }
 482
 483 int i915_driver_irq_postinstall(struct drm_device *dev)
 484 {
 485         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 486
 487         dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
 488
 489         dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
 490
 491         /* Unmask the interrupts that we always want on. */
 492         dev_priv->irq_mask_reg = ~I915_INTERRUPT_ENABLE_FIX;
 493
 494         dev_priv->pipestat[0] = 0;
 495         dev_priv->pipestat[1] = 0;
 496
 497         /* Disable pipe interrupt enables, clear pending pipe status */
 498         I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) & 0x8000ffff);
 499         I915_WRITE(PIPEBSTAT, I915_READ(PIPEBSTAT) & 0x8000ffff);
 500
 501         /* Clear pending interrupt status */
 502         I915_WRITE(IIR, I915_READ(IIR));
 503
 504         I915_WRITE(IER, I915_INTERRUPT_ENABLE_MASK);
 505         I915_WRITE(IMR, dev_priv->irq_mask_reg);
 506         (void) I915_READ(IER);
 507 #ifdef __linux__
 508         opregion_enable_asle(dev);
 509 #endif
 510         DRM_INIT_WAITQUEUE(&dev_priv->irq_queue);
 511
 512         i915_enable_vblank(dev, 0);
 513         i915_enable_vblank(dev, 1);
 514
 515         return 0;
 516 }
 517
 518 void i915_driver_irq_uninstall(struct drm_device * dev)
 519 {
 520         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 521
 522         if (!dev_priv)
 523                 return;
 524
 525         dev_priv->vblank_pipe = 0;
 526
 527         I915_WRITE(HWSTAM, 0xffffffff);
 528         I915_WRITE(PIPEASTAT, 0);
 529         I915_WRITE(PIPEBSTAT, 0);
 530         I915_WRITE(IMR, 0xffffffff);
 531         I915_WRITE(IER, 0x0);
 532
 533         I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) & 0x8000ffff);
 534         I915_WRITE(PIPEBSTAT, I915_READ(PIPEBSTAT) & 0x8000ffff);
 535         I915_WRITE(IIR, I915_READ(IIR));
 536 }