sys/external/bsd/drm/dist/shared-core/nouveau_drm.h

   1 /*
   2  * Copyright 2005 Stephane Marchesin.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  */
  24
  25 #ifndef __NOUVEAU_DRM_H__
  26 #define __NOUVEAU_DRM_H__
  27
  28 #define NOUVEAU_DRM_HEADER_PATCHLEVEL 12
  29
  30 struct drm_nouveau_channel_alloc {
  31         uint32_t     fb_ctxdma_handle;
  32         uint32_t     tt_ctxdma_handle;
  33
  34         int          channel;
  35
  36         /* Notifier memory */
  37         drm_handle_t notifier;
  38         int          notifier_size;
  39
  40         /* DRM-enforced subchannel assignments */
  41         struct {
  42                 uint32_t handle;
  43                 uint32_t grclass;
  44         } subchan[8];
  45         uint32_t nr_subchan;
  46
  47 /* !MM_ENABLED ONLY */
  48         uint32_t     put_base;
  49         /* FIFO control regs */
  50         drm_handle_t ctrl;
  51         int          ctrl_size;
  52         /* DMA command buffer */
  53         drm_handle_t cmdbuf;
  54         int          cmdbuf_size;
  55 };
  56
  57 struct drm_nouveau_channel_free {
  58         int channel;
  59 };
  60
  61 struct drm_nouveau_grobj_alloc {
  62         int      channel;
  63         uint32_t handle;
  64         int      class;
  65 };
  66
  67 #define NOUVEAU_MEM_ACCESS_RO   1
  68 #define NOUVEAU_MEM_ACCESS_WO   2
  69 #define NOUVEAU_MEM_ACCESS_RW   3
  70 struct drm_nouveau_notifierobj_alloc {
  71         int      channel;
  72         uint32_t handle;
  73         int      count;
  74
  75         uint32_t offset;
  76 };
  77
  78 struct drm_nouveau_gpuobj_free {
  79         int      channel;
  80         uint32_t handle;
  81 };
  82
  83 /* This is needed to avoid a race condition.
  84  * Otherwise you may be writing in the fetch area.
  85  * Is this large enough, as it's only 32 bytes, and the maximum fetch size is 256 bytes?
  86  */
  87 #define NOUVEAU_DMA_SKIPS 8
  88
  89 #define NOUVEAU_MEM_FB                  0x00000001
  90 #define NOUVEAU_MEM_AGP                 0x00000002
  91 #define NOUVEAU_MEM_FB_ACCEPTABLE       0x00000004
  92 #define NOUVEAU_MEM_AGP_ACCEPTABLE      0x00000008
  93 #define NOUVEAU_MEM_PCI                 0x00000010
  94 #define NOUVEAU_MEM_PCI_ACCEPTABLE      0x00000020
  95 #define NOUVEAU_MEM_PINNED              0x00000040
  96 #define NOUVEAU_MEM_USER_BACKED         0x00000080
  97 #define NOUVEAU_MEM_MAPPED              0x00000100
  98 #define NOUVEAU_MEM_TILE                0x00000200
  99 #define NOUVEAU_MEM_TILE_ZETA           0x00000400
 100 #define NOUVEAU_MEM_INSTANCE            0x01000000 /* internal */
 101 #define NOUVEAU_MEM_NOTIFIER            0x02000000 /* internal */
 102 #define NOUVEAU_MEM_NOVM                0x04000000 /* internal */
 103 #define NOUVEAU_MEM_USER                0x08000000 /* internal */
 104 #define NOUVEAU_MEM_INTERNAL (NOUVEAU_MEM_INSTANCE | \
 105                               NOUVEAU_MEM_NOTIFIER | \
 106                               NOUVEAU_MEM_NOVM | \
 107                               NOUVEAU_MEM_USER)
 108
 109 struct drm_nouveau_mem_alloc {
 110         int flags;
 111         int alignment;
 112         uint64_t size;  // in bytes
 113         uint64_t offset;
 114         drm_handle_t map_handle;
 115 };
 116
 117 struct drm_nouveau_mem_free {
 118         uint64_t offset;
 119         int flags;
 120 };
 121
 122 struct drm_nouveau_mem_tile {
 123         uint64_t offset;
 124         uint64_t delta;
 125         uint64_t size;
 126         int flags;
 127 };
 128
 129 /* FIXME : maybe unify {GET,SET}PARAMs */
 130 #define NOUVEAU_GETPARAM_PCI_VENDOR      3
 131 #define NOUVEAU_GETPARAM_PCI_DEVICE      4
 132 #define NOUVEAU_GETPARAM_BUS_TYPE        5
 133 #define NOUVEAU_GETPARAM_FB_PHYSICAL     6
 134 #define NOUVEAU_GETPARAM_AGP_PHYSICAL    7
 135 #define NOUVEAU_GETPARAM_FB_SIZE         8
 136 #define NOUVEAU_GETPARAM_AGP_SIZE        9
 137 #define NOUVEAU_GETPARAM_PCI_PHYSICAL    10
 138 #define NOUVEAU_GETPARAM_CHIPSET_ID      11
 139 #define NOUVEAU_GETPARAM_MM_ENABLED      12
 140 #define NOUVEAU_GETPARAM_VM_VRAM_BASE    13
 141 struct drm_nouveau_getparam {
 142         uint64_t param;
 143         uint64_t value;
 144 };
 145
 146 #define NOUVEAU_SETPARAM_CMDBUF_LOCATION 1
 147 #define NOUVEAU_SETPARAM_CMDBUF_SIZE     2
 148 struct drm_nouveau_setparam {
 149         uint64_t param;
 150         uint64_t value;
 151 };
 152
 153 #define NOUVEAU_GEM_DOMAIN_CPU       (1 << 0)
 154 #define NOUVEAU_GEM_DOMAIN_VRAM      (1 << 1)
 155 #define NOUVEAU_GEM_DOMAIN_GART      (1 << 2)
 156 #define NOUVEAU_GEM_DOMAIN_NOMAP     (1 << 3)
 157 #define NOUVEAU_GEM_DOMAIN_TILE      (1 << 30)
 158 #define NOUVEAU_GEM_DOMAIN_TILE_ZETA (1 << 31)
 159
 160 struct drm_nouveau_gem_new {
 161         uint64_t size;
 162         uint32_t channel_hint;
 163         uint32_t align;
 164         uint32_t handle;
 165         uint32_t domain;
 166         uint32_t offset;
 167 };
 168
 169 struct drm_nouveau_gem_pushbuf_bo {
 170         uint64_t user_priv;
 171         uint32_t handle;
 172         uint32_t read_domains;
 173         uint32_t write_domains;
 174         uint32_t valid_domains;
 175         uint32_t presumed_ok;
 176         uint32_t presumed_domain;
 177         uint64_t presumed_offset;
 178 };
 179
 180 #define NOUVEAU_GEM_RELOC_LOW  (1 << 0)
 181 #define NOUVEAU_GEM_RELOC_HIGH (1 << 1)
 182 #define NOUVEAU_GEM_RELOC_OR   (1 << 2)
 183 struct drm_nouveau_gem_pushbuf_reloc {
 184         uint32_t bo_index;
 185         uint32_t reloc_index;
 186         uint32_t flags;
 187         uint32_t data;
 188         uint32_t vor;
 189         uint32_t tor;
 190 };
 191
 192 #define NOUVEAU_GEM_MAX_BUFFERS 1024
 193 #define NOUVEAU_GEM_MAX_RELOCS 1024
 194
 195 struct drm_nouveau_gem_pushbuf {
 196         uint32_t channel;
 197         uint32_t nr_dwords;
 198         uint32_t nr_buffers;
 199         uint32_t nr_relocs;
 200         uint64_t dwords;
 201         uint64_t buffers;
 202         uint64_t relocs;
 203 };
 204
 205 struct drm_nouveau_gem_pushbuf_call {
 206         uint32_t channel;
 207         uint32_t handle;
 208         uint32_t offset;
 209         uint32_t nr_buffers;
 210         uint32_t nr_relocs;
 211         uint32_t pad0;
 212         uint64_t buffers;
 213         uint64_t relocs;
 214 };
 215
 216 struct drm_nouveau_gem_pin {
 217         uint32_t handle;
 218         uint32_t domain;
 219         uint64_t offset;
 220 };
 221
 222 struct drm_nouveau_gem_unpin {
 223         uint32_t handle;
 224 };
 225
 226 struct drm_nouveau_gem_mmap {
 227         uint32_t handle;
 228         uint32_t pad;
 229         uint64_t vaddr;
 230 };
 231
 232 struct drm_nouveau_gem_cpu_prep {
 233         uint32_t handle;
 234 };
 235
 236 struct drm_nouveau_gem_cpu_fini {
 237         uint32_t handle;
 238 };
 239
 240 struct drm_nouveau_gem_tile {
 241         uint32_t handle;
 242         uint32_t delta;
 243         uint32_t size;
 244         uint32_t flags;
 245 };
 246
 247 enum nouveau_card_type {
 248         NV_UNKNOWN =0,
 249         NV_04      =4,
 250         NV_05      =5,
 251         NV_10      =10,
 252         NV_11      =11,
 253         NV_17      =17,
 254         NV_20      =20,
 255         NV_30      =30,
 256         NV_40      =40,
 257         NV_44      =44,
 258         NV_50      =50,
 259         NV_LAST    =0xffff,
 260 };
 261
 262 enum nouveau_bus_type {
 263         NV_AGP     =0,
 264         NV_PCI     =1,
 265         NV_PCIE    =2,
 266 };
 267
 268 #define NOUVEAU_MAX_SAREA_CLIPRECTS 16
 269
 270 struct drm_nouveau_sarea {
 271         /* the cliprects */
 272         struct drm_clip_rect boxes[NOUVEAU_MAX_SAREA_CLIPRECTS];
 273         unsigned int nbox;
 274 };
 275
 276 #define DRM_NOUVEAU_CARD_INIT          0x00
 277 #define DRM_NOUVEAU_GETPARAM           0x01
 278 #define DRM_NOUVEAU_SETPARAM           0x02
 279 #define DRM_NOUVEAU_CHANNEL_ALLOC      0x03
 280 #define DRM_NOUVEAU_CHANNEL_FREE       0x04
 281 #define DRM_NOUVEAU_GROBJ_ALLOC        0x05
 282 #define DRM_NOUVEAU_NOTIFIEROBJ_ALLOC  0x06
 283 #define DRM_NOUVEAU_GPUOBJ_FREE        0x07
 284 #define DRM_NOUVEAU_MEM_ALLOC          0x08
 285 #define DRM_NOUVEAU_MEM_FREE           0x09
 286 #define DRM_NOUVEAU_MEM_TILE           0x0a
 287 #define DRM_NOUVEAU_SUSPEND            0x0b
 288 #define DRM_NOUVEAU_RESUME             0x0c
 289 #define DRM_NOUVEAU_GEM_NEW            0x40
 290 #define DRM_NOUVEAU_GEM_PUSHBUF        0x41
 291 #define DRM_NOUVEAU_GEM_PUSHBUF_CALL   0x42
 292 #define DRM_NOUVEAU_GEM_PIN            0x43
 293 #define DRM_NOUVEAU_GEM_UNPIN          0x44
 294 #define DRM_NOUVEAU_GEM_MMAP           0x45
 295 #define DRM_NOUVEAU_GEM_CPU_PREP       0x46
 296 #define DRM_NOUVEAU_GEM_CPU_FINI       0x47
 297 #define DRM_NOUVEAU_GEM_TILE           0x48
 298
 299 #endif /* __NOUVEAU_DRM_H__ */