sys/external/bsd/drm/dist/shared-core/nv50_graph.c

   1 /*
   2  * Copyright (C) 2007 Ben Skeggs.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining
   6  * a copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sublicense, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the
  14  * next paragraph) shall be included in all copies or substantial
  15  * portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  18  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  19  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  20  * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  21  * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  22  * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  23  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  24  *
  25  */
  26
  27 #include "drmP.h"
  28 #include "drm.h"
  29 #include "nouveau_drv.h"
  30 #include "nv50_grctx.h"
  31
  32 #define IS_G80 ((dev_priv->chipset & 0xf0) == 0x50)
  33
  34 static void
  35 nv50_graph_init_reset(struct drm_device *dev)
  36 {
  37         struct drm_nouveau_private *dev_priv = dev->dev_private;
  38         uint32_t pmc_e = NV_PMC_ENABLE_PGRAPH | (1 << 21);
  39
  40         DRM_DEBUG("\n");
  41
  42         NV_WRITE(NV03_PMC_ENABLE, NV_READ(NV03_PMC_ENABLE) & ~pmc_e);
  43         NV_WRITE(NV03_PMC_ENABLE, NV_READ(NV03_PMC_ENABLE) |  pmc_e);
  44 }
  45
  46 static void
  47 nv50_graph_init_intr(struct drm_device *dev)
  48 {
  49         struct drm_nouveau_private *dev_priv = dev->dev_private;
  50
  51         DRM_DEBUG("\n");
  52         NV_WRITE(NV03_PGRAPH_INTR, 0xffffffff);
  53         NV_WRITE(0x400138, 0xffffffff);
  54         NV_WRITE(NV40_PGRAPH_INTR_EN, 0xffffffff);
  55 }
  56
  57 static void
  58 nv50_graph_init_regs__nv(struct drm_device *dev)
  59 {
  60         struct drm_nouveau_private *dev_priv = dev->dev_private;
  61
  62         DRM_DEBUG("\n");
  63
  64         NV_WRITE(0x400804, 0xc0000000);
  65         NV_WRITE(0x406800, 0xc0000000);
  66         NV_WRITE(0x400c04, 0xc0000000);
  67         NV_WRITE(0x401804, 0xc0000000);
  68         NV_WRITE(0x405018, 0xc0000000);
  69         NV_WRITE(0x402000, 0xc0000000);
  70
  71         NV_WRITE(0x400108, 0xffffffff);
  72
  73         NV_WRITE(0x400824, 0x00004000);
  74         NV_WRITE(0x400500, 0x00010001);
  75 }
  76
  77 static void
  78 nv50_graph_init_regs(struct drm_device *dev)
  79 {
  80         struct drm_nouveau_private *dev_priv = dev->dev_private;
  81
  82         DRM_DEBUG("\n");
  83
  84         NV_WRITE(NV04_PGRAPH_DEBUG_3, (1<<2) /* HW_CONTEXT_SWITCH_ENABLED */);
  85 }
  86
  87 static int
  88 nv50_graph_init_ctxctl(struct drm_device *dev)
  89 {
  90         struct drm_nouveau_private *dev_priv = dev->dev_private;
  91         uint32_t *voodoo = NULL;
  92
  93         DRM_DEBUG("\n");
  94
  95         switch (dev_priv->chipset) {
  96         case 0x50:
  97                 voodoo = nv50_ctxprog;
  98                 break;
  99         case 0x84:
 100                 voodoo = nv84_ctxprog;
 101                 break;
 102         case 0x86:
 103                 voodoo = nv86_ctxprog;
 104                 break;
 105         case 0x92:
 106                 voodoo = nv92_ctxprog;
 107                 break;
 108         case 0x94:
 109         case 0x96:
 110                 voodoo = nv94_ctxprog;
 111                 break;
 112         case 0x98:
 113                 voodoo = nv98_ctxprog;
 114                 break;
 115         case 0xa0:
 116                 voodoo = nva0_ctxprog;
 117                 break;
 118         case 0xaa:
 119                 voodoo = nvaa_ctxprog;
 120                 break;
 121         default:
 122                 DRM_ERROR("no ctxprog for chipset NV%02x\n", dev_priv->chipset);
 123                 return -EINVAL;
 124         }
 125
 126         NV_WRITE(NV40_PGRAPH_CTXCTL_UCODE_INDEX, 0);
 127         while (*voodoo != ~0) {
 128                 NV_WRITE(NV40_PGRAPH_CTXCTL_UCODE_DATA, *voodoo);
 129                 voodoo++;
 130         }
 131
 132         NV_WRITE(0x400320, 4);
 133         NV_WRITE(NV40_PGRAPH_CTXCTL_CUR, 0);
 134         NV_WRITE(NV20_PGRAPH_CHANNEL_CTX_POINTER, 0);
 135
 136         return 0;
 137 }
 138
 139 int
 140 nv50_graph_init(struct drm_device *dev)
 141 {
 142         int ret;
 143
 144         DRM_DEBUG("\n");
 145
 146         nv50_graph_init_reset(dev);
 147         nv50_graph_init_intr(dev);
 148         nv50_graph_init_regs__nv(dev);
 149         nv50_graph_init_regs(dev);
 150
 151         ret = nv50_graph_init_ctxctl(dev);
 152         if (ret)
 153                 return ret;
 154
 155         return 0;
 156 }
 157
 158 void
 159 nv50_graph_takedown(struct drm_device *dev)
 160 {
 161         DRM_DEBUG("\n");
 162 }
 163
 164 int
 165 nv50_graph_create_context(struct nouveau_channel *chan)
 166 {
 167         struct drm_device *dev = chan->dev;
 168         struct drm_nouveau_private *dev_priv = dev->dev_private;
 169         struct nouveau_gpuobj *ramin = chan->ramin->gpuobj;
 170         struct nouveau_gpuobj *ctx;
 171         struct nouveau_engine *engine = &dev_priv->Engine;
 172         uint32_t *ctxvals = NULL;
 173         int grctx_size = 0x70000, hdr;
 174         int ret;
 175
 176         DRM_DEBUG("ch%d\n", chan->id);
 177
 178         ret = nouveau_gpuobj_new_ref(dev, chan, NULL, 0, grctx_size, 0x1000,
 179                                      NVOBJ_FLAG_ZERO_ALLOC |
 180                                      NVOBJ_FLAG_ZERO_FREE, &chan->ramin_grctx);
 181         if (ret)
 182                 return ret;
 183         ctx = chan->ramin_grctx->gpuobj;
 184
 185         hdr = IS_G80 ? 0x200 : 0x20;
 186         INSTANCE_WR(ramin, (hdr + 0x00)/4, 0x00190002);
 187         INSTANCE_WR(ramin, (hdr + 0x04)/4, chan->ramin_grctx->instance +
 188                                            grctx_size - 1);
 189         INSTANCE_WR(ramin, (hdr + 0x08)/4, chan->ramin_grctx->instance);
 190         INSTANCE_WR(ramin, (hdr + 0x0c)/4, 0);
 191         INSTANCE_WR(ramin, (hdr + 0x10)/4, 0);
 192         INSTANCE_WR(ramin, (hdr + 0x14)/4, 0x00010000);
 193
 194         switch (dev_priv->chipset) {
 195         case 0x50:
 196                 ctxvals = nv50_ctxvals;
 197                 break;
 198         case 0x84:
 199                 ctxvals = nv84_ctxvals;
 200                 break;
 201         case 0x86:
 202                 ctxvals = nv86_ctxvals;
 203                 break;
 204         case 0x92:
 205                 ctxvals = nv92_ctxvals;
 206                 break;
 207         case 0x94:
 208                 ctxvals = nv94_ctxvals;
 209                 break;
 210         case 0x96:
 211                 ctxvals = nv96_ctxvals;
 212                 break;
 213         case 0x98:
 214                 ctxvals = nv98_ctxvals;
 215                 break;
 216         case 0xa0:
 217                 ctxvals = nva0_ctxvals;
 218                 break;
 219         case 0xaa:
 220                 ctxvals = nvaa_ctxvals;
 221                 break;
 222         default:
 223                 break;
 224         }
 225
 226         if (ctxvals) {
 227                 int pos = 0;
 228
 229                 while (*ctxvals) {
 230                         int cnt = *ctxvals++;
 231
 232                         while (cnt--)
 233                                 INSTANCE_WR(ctx, pos++, *ctxvals);
 234                         ctxvals++;
 235                 }
 236         } else {
 237                 /* This is complete crack, it accidently used to make at
 238                  * least some G8x cards work partially somehow, though there's
 239                  * no good reason why - and it stopped working as the rest
 240                  * of the code got off the drugs..
 241                  */
 242                 ret = engine->graph.load_context(chan);
 243                 if (ret) {
 244                         DRM_ERROR("Error hacking up context: %d\n", ret);
 245                         return ret;
 246                 }
 247         }
 248
 249         INSTANCE_WR(ctx, 0x00000/4, chan->ramin->instance >> 12);
 250         if ((dev_priv->chipset & 0xf0) == 0xa0)
 251                 INSTANCE_WR(ctx, 0x00004/4, 0x00000002);
 252         else
 253                 INSTANCE_WR(ctx, 0x0011c/4, 0x00000002);
 254
 255         return 0;
 256 }
 257
 258 void
 259 nv50_graph_destroy_context(struct nouveau_channel *chan)
 260 {
 261         struct drm_device *dev = chan->dev;
 262         struct drm_nouveau_private *dev_priv = dev->dev_private;
 263         int i, hdr;
 264
 265         DRM_DEBUG("ch%d\n", chan->id);
 266
 267         hdr = IS_G80 ? 0x200 : 0x20;
 268         for (i=hdr; i<hdr+24; i+=4)
 269                 INSTANCE_WR(chan->ramin->gpuobj, i/4, 0);
 270
 271         nouveau_gpuobj_ref_del(dev, &chan->ramin_grctx);
 272 }
 273
 274 static int
 275 nv50_graph_transfer_context(struct drm_device *dev, uint32_t inst, int save)
 276 {
 277         struct drm_nouveau_private *dev_priv = dev->dev_private;
 278         uint32_t old_cp, tv = 20000;
 279         int i;
 280
 281         DRM_DEBUG("inst=0x%08x, save=%d\n", inst, save);
 282
 283         old_cp = NV_READ(NV20_PGRAPH_CHANNEL_CTX_POINTER);
 284         NV_WRITE(NV20_PGRAPH_CHANNEL_CTX_POINTER, inst);
 285         NV_WRITE(0x400824, NV_READ(0x400824) |
 286                  (save ? NV40_PGRAPH_CTXCTL_0310_XFER_SAVE :
 287                          NV40_PGRAPH_CTXCTL_0310_XFER_LOAD));
 288         NV_WRITE(NV40_PGRAPH_CTXCTL_0304, NV40_PGRAPH_CTXCTL_0304_XFER_CTX);
 289
 290         for (i = 0; i < tv; i++) {
 291                 if (NV_READ(NV40_PGRAPH_CTXCTL_030C) == 0)
 292                         break;
 293         }
 294         NV_WRITE(NV20_PGRAPH_CHANNEL_CTX_POINTER, old_cp);
 295
 296         if (i == tv) {
 297                 DRM_ERROR("failed: inst=0x%08x save=%d\n", inst, save);
 298                 DRM_ERROR("0x40030C = 0x%08x\n",
 299                           NV_READ(NV40_PGRAPH_CTXCTL_030C));
 300                 return -EBUSY;
 301         }
 302
 303         return 0;
 304 }
 305
 306 int
 307 nv50_graph_load_context(struct nouveau_channel *chan)
 308 {
 309         struct drm_device *dev = chan->dev;
 310         struct drm_nouveau_private *dev_priv = dev->dev_private;
 311         uint32_t inst = chan->ramin->instance >> 12;
 312         int ret; (void)ret;
 313
 314         DRM_DEBUG("ch%d\n", chan->id);
 315
 316 #if 0
 317         if ((ret = nv50_graph_transfer_context(dev, inst, 0)))
 318                 return ret;
 319 #endif
 320
 321         NV_WRITE(NV20_PGRAPH_CHANNEL_CTX_POINTER, inst);
 322         NV_WRITE(0x400320, 4);
 323         NV_WRITE(NV40_PGRAPH_CTXCTL_CUR, inst | (1<<31));
 324
 325         return 0;
 326 }
 327
 328 int
 329 nv50_graph_save_context(struct nouveau_channel *chan)
 330 {
 331         struct drm_device *dev = chan->dev;
 332         uint32_t inst = chan->ramin->instance >> 12;
 333
 334         DRM_DEBUG("ch%d\n", chan->id);
 335
 336         return nv50_graph_transfer_context(dev, inst, 1);
 337 }