sys/external/bsd/drm/dist/shared-core/nv50_instmem.c

   1 /*
   2  * Copyright (C) 2007 Ben Skeggs.
   3  *
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining
   7  * a copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sublicense, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial
  16  * portions of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  */
  27
  28 #include "drmP.h"
  29 #include "drm.h"
  30 #include "nouveau_drv.h"
  31
  32 typedef struct {
  33         uint32_t save1700[5]; /* 0x1700->0x1710 */
  34
  35         struct nouveau_gpuobj_ref *pramin_pt;
  36         struct nouveau_gpuobj_ref *pramin_bar;
  37 } nv50_instmem_priv;
  38
  39 #define NV50_INSTMEM_PAGE_SHIFT 12
  40 #define NV50_INSTMEM_PAGE_SIZE  (1 << NV50_INSTMEM_PAGE_SHIFT)
  41 #define NV50_INSTMEM_PT_SIZE(a) (((a) >> 12) << 3)
  42
  43 /*NOTE: - Assumes 0x1700 already covers the correct MiB of PRAMIN
  44  */
  45 #define BAR0_WI32(g,o,v) do {                                     \
  46         uint32_t offset;                                          \
  47         if ((g)->im_backing) {                                    \
  48                 offset = (g)->im_backing->start;                  \
  49         } else {                                                  \
  50                 offset  = chan->ramin->gpuobj->im_backing->start; \
  51                 offset += (g)->im_pramin->start;                  \
  52         }                                                         \
  53         offset += (o);                                            \
  54         NV_WRITE(NV_RAMIN + (offset & 0xfffff), (v));             \
  55 } while(0)
  56
  57 int
  58 nv50_instmem_init(struct drm_device *dev)
  59 {
  60         struct drm_nouveau_private *dev_priv = dev->dev_private;
  61         struct nouveau_channel *chan;
  62         uint32_t c_offset, c_size, c_ramfc, c_vmpd, c_base, pt_size;
  63         nv50_instmem_priv *priv;
  64         int ret, i;
  65         uint32_t v;
  66
  67         priv = drm_calloc(1, sizeof(*priv), DRM_MEM_DRIVER);
  68         if (!priv)
  69                 return -ENOMEM;
  70         dev_priv->Engine.instmem.priv = priv;
  71
  72         /* Save state, will restore at takedown. */
  73         for (i = 0x1700; i <= 0x1710; i+=4)
  74                 priv->save1700[(i-0x1700)/4] = NV_READ(i);
  75
  76         /* Reserve the last MiB of VRAM, we should probably try to avoid
  77          * setting up the below tables over the top of the VBIOS image at
  78          * some point.
  79          */
  80         dev_priv->ramin_rsvd_vram = 1 << 20;
  81         c_offset = nouveau_mem_fb_amount(dev) - dev_priv->ramin_rsvd_vram;
  82         c_size   = 128 << 10;
  83         c_vmpd   = ((dev_priv->chipset & 0xf0) == 0x50) ? 0x1400 : 0x200;
  84         c_ramfc  = ((dev_priv->chipset & 0xf0) == 0x50) ? 0x0 : 0x20;
  85         c_base   = c_vmpd + 0x4000;
  86         pt_size  = NV50_INSTMEM_PT_SIZE(dev_priv->ramin->size);
  87
  88         DRM_DEBUG(" Rsvd VRAM base: 0x%08x\n", c_offset);
  89         DRM_DEBUG("    VBIOS image: 0x%08x\n", (NV_READ(0x619f04)&~0xff)<<8);
  90         DRM_DEBUG("  Aperture size: %d MiB\n",
  91                   (uint32_t)dev_priv->ramin->size >> 20);
  92         DRM_DEBUG("        PT size: %d KiB\n", pt_size >> 10);
  93
  94         NV_WRITE(NV50_PUNK_BAR0_PRAMIN, (c_offset >> 16));
  95
  96         /* Create a fake channel, and use it as our "dummy" channels 0/127.
  97          * The main reason for creating a channel is so we can use the gpuobj
  98          * code.  However, it's probably worth noting that NVIDIA also setup
  99          * their channels 0/127 with the same values they configure here.
 100          * So, there may be some other reason for doing this.
 101          *
 102          * Have to create the entire channel manually, as the real channel
 103          * creation code assumes we have PRAMIN access, and we don't until
 104          * we're done here.
 105          */
 106         chan = drm_calloc(1, sizeof(*chan), DRM_MEM_DRIVER);
 107         if (!chan)
 108                 return -ENOMEM;
 109         chan->id = 0;
 110         chan->dev = dev;
 111         chan->file_priv = (struct drm_file *)-2;
 112         dev_priv->fifos[0] = dev_priv->fifos[127] = chan;
 113
 114         /* Channel's PRAMIN object + heap */
 115         if ((ret = nouveau_gpuobj_new_fake(dev, 0, c_offset, 128<<10, 0,
 116                                            NULL, &chan->ramin)))
 117                 return ret;
 118
 119         if (nouveau_mem_init_heap(&chan->ramin_heap, c_base, c_size - c_base))
 120                 return -ENOMEM;
 121
 122         /* RAMFC + zero channel's PRAMIN up to start of VM pagedir */
 123         if ((ret = nouveau_gpuobj_new_fake(dev, c_ramfc, c_offset + c_ramfc,
 124                                            0x4000, 0, NULL, &chan->ramfc)))
 125                 return ret;
 126
 127         for (i = 0; i < c_vmpd; i += 4)
 128                 BAR0_WI32(chan->ramin->gpuobj, i, 0);
 129
 130         /* VM page directory */
 131         if ((ret = nouveau_gpuobj_new_fake(dev, c_vmpd, c_offset + c_vmpd,
 132                                            0x4000, 0, &chan->vm_pd, NULL)))
 133                 return ret;
 134         for (i = 0; i < 0x4000; i += 8) {
 135                 BAR0_WI32(chan->vm_pd, i + 0x00, 0x00000000);
 136                 BAR0_WI32(chan->vm_pd, i + 0x04, 0x00000000);
 137         }
 138
 139         /* PRAMIN page table, cheat and map into VM at 0x0000000000.
 140          * We map the entire fake channel into the start of the PRAMIN BAR
 141          */
 142         if ((ret = nouveau_gpuobj_new_ref(dev, chan, NULL, 0, pt_size, 0x1000,
 143                                           0, &priv->pramin_pt)))
 144                 return ret;
 145
 146         for (i = 0, v = c_offset; i < pt_size; i+=8, v+=0x1000) {
 147                 if (v < (c_offset + c_size))
 148                         BAR0_WI32(priv->pramin_pt->gpuobj, i + 0, v | 1);
 149                 else
 150                         BAR0_WI32(priv->pramin_pt->gpuobj, i + 0, 0x00000009);
 151                 BAR0_WI32(priv->pramin_pt->gpuobj, i + 4, 0x00000000);
 152         }
 153
 154         BAR0_WI32(chan->vm_pd, 0x00, priv->pramin_pt->instance | 0x63);
 155         BAR0_WI32(chan->vm_pd, 0x04, 0x00000000);
 156
 157         /* DMA object for PRAMIN BAR */
 158         if ((ret = nouveau_gpuobj_new_ref(dev, chan, chan, 0, 6*4, 16, 0,
 159                                           &priv->pramin_bar)))
 160                 return ret;
 161         BAR0_WI32(priv->pramin_bar->gpuobj, 0x00, 0x7fc00000);
 162         BAR0_WI32(priv->pramin_bar->gpuobj, 0x04, dev_priv->ramin->size - 1);
 163         BAR0_WI32(priv->pramin_bar->gpuobj, 0x08, 0x00000000);
 164         BAR0_WI32(priv->pramin_bar->gpuobj, 0x0c, 0x00000000);
 165         BAR0_WI32(priv->pramin_bar->gpuobj, 0x10, 0x00000000);
 166         BAR0_WI32(priv->pramin_bar->gpuobj, 0x14, 0x00000000);
 167
 168         /* Poke the relevant regs, and pray it works :) */
 169         NV_WRITE(NV50_PUNK_BAR_CFG_BASE, (chan->ramin->instance >> 12));
 170         NV_WRITE(NV50_PUNK_UNK1710, 0);
 171         NV_WRITE(NV50_PUNK_BAR_CFG_BASE, (chan->ramin->instance >> 12) |
 172                                          NV50_PUNK_BAR_CFG_BASE_VALID);
 173         NV_WRITE(NV50_PUNK_BAR1_CTXDMA, 0);
 174         NV_WRITE(NV50_PUNK_BAR3_CTXDMA, (priv->pramin_bar->instance >> 4) |
 175                                         NV50_PUNK_BAR3_CTXDMA_VALID);
 176
 177         /* Assume that praying isn't enough, check that we can re-read the
 178          * entire fake channel back from the PRAMIN BAR */
 179         for (i = 0; i < c_size; i+=4) {
 180                 if (NV_READ(NV_RAMIN + i) != NV_RI32(i)) {
 181                         DRM_ERROR("Error reading back PRAMIN at 0x%08x\n", i);
 182                         return -EINVAL;
 183                 }
 184         }
 185
 186         /* Global PRAMIN heap */
 187         if (nouveau_mem_init_heap(&dev_priv->ramin_heap,
 188                                   c_size, dev_priv->ramin->size - c_size)) {
 189                 dev_priv->ramin_heap = NULL;
 190                 DRM_ERROR("Failed to init RAMIN heap\n");
 191         }
 192
 193         /*XXX: incorrect, but needed to make hash func "work" */
 194         dev_priv->ramht_offset = 0x10000;
 195         dev_priv->ramht_bits   = 9;
 196         dev_priv->ramht_size   = (1 << dev_priv->ramht_bits);
 197         return 0;
 198 }
 199
 200 void
 201 nv50_instmem_takedown(struct drm_device *dev)
 202 {
 203         struct drm_nouveau_private *dev_priv = dev->dev_private;
 204         nv50_instmem_priv *priv = dev_priv->Engine.instmem.priv;
 205         struct nouveau_channel *chan = dev_priv->fifos[0];
 206         int i;
 207
 208         DRM_DEBUG("\n");
 209
 210         if (!priv)
 211                 return;
 212
 213         /* Restore state from before init */
 214         for (i = 0x1700; i <= 0x1710; i+=4)
 215                 NV_WRITE(i, priv->save1700[(i-0x1700)/4]);
 216
 217         nouveau_gpuobj_ref_del(dev, &priv->pramin_bar);
 218         nouveau_gpuobj_ref_del(dev, &priv->pramin_pt);
 219
 220         /* Destroy dummy channel */
 221         if (chan) {
 222                 nouveau_gpuobj_del(dev, &chan->vm_pd);
 223                 nouveau_gpuobj_ref_del(dev, &chan->ramfc);
 224                 nouveau_gpuobj_ref_del(dev, &chan->ramin);
 225                 nouveau_mem_takedown(&chan->ramin_heap);
 226
 227                 dev_priv->fifos[0] = dev_priv->fifos[127] = NULL;
 228                 drm_free(chan, sizeof(*chan), DRM_MEM_DRIVER);
 229         }
 230
 231         dev_priv->Engine.instmem.priv = NULL;
 232         drm_free(priv, sizeof(*priv), DRM_MEM_DRIVER);
 233 }
 234
 235 int
 236 nv50_instmem_populate(struct drm_device *dev, struct nouveau_gpuobj *gpuobj, uint32_t *sz)
 237 {
 238         if (gpuobj->im_backing)
 239                 return -EINVAL;
 240
 241         *sz = (*sz + (NV50_INSTMEM_PAGE_SIZE-1)) & ~(NV50_INSTMEM_PAGE_SIZE-1);
 242         if (*sz == 0)
 243                 return -EINVAL;
 244
 245         gpuobj->im_backing = nouveau_mem_alloc(dev, NV50_INSTMEM_PAGE_SIZE,
 246                                                *sz, NOUVEAU_MEM_FB |
 247                                                NOUVEAU_MEM_NOVM,
 248                                                (struct drm_file *)-2);
 249         if (!gpuobj->im_backing) {
 250                 DRM_ERROR("Couldn't allocate vram to back PRAMIN pages\n");
 251                 return -ENOMEM;
 252         }
 253
 254         return 0;
 255 }
 256
 257 void
 258 nv50_instmem_clear(struct drm_device *dev, struct nouveau_gpuobj *gpuobj)
 259 {
 260         struct drm_nouveau_private *dev_priv = dev->dev_private;
 261
 262         if (gpuobj && gpuobj->im_backing) {
 263                 if (gpuobj->im_bound)
 264                         dev_priv->Engine.instmem.unbind(dev, gpuobj);
 265                 nouveau_mem_free(dev, gpuobj->im_backing);
 266                 gpuobj->im_backing = NULL;
 267         }
 268 }
 269
 270 int
 271 nv50_instmem_bind(struct drm_device *dev, struct nouveau_gpuobj *gpuobj)
 272 {
 273         struct drm_nouveau_private *dev_priv = dev->dev_private;
 274         nv50_instmem_priv *priv = dev_priv->Engine.instmem.priv;
 275         uint32_t pte, pte_end, vram;
 276
 277         if (!gpuobj->im_backing || !gpuobj->im_pramin || gpuobj->im_bound)
 278                 return -EINVAL;
 279
 280         DRM_DEBUG("st=0x%0llx sz=0x%0llx\n",
 281                   gpuobj->im_pramin->start, gpuobj->im_pramin->size);
 282
 283         pte     = (gpuobj->im_pramin->start >> 12) << 3;
 284         pte_end = ((gpuobj->im_pramin->size >> 12) << 3) + pte;
 285         vram    = gpuobj->im_backing->start;
 286
 287         DRM_DEBUG("pramin=0x%llx, pte=%d, pte_end=%d\n",
 288                   gpuobj->im_pramin->start, pte, pte_end);
 289         DRM_DEBUG("first vram page: 0x%llx\n",
 290                   gpuobj->im_backing->start);
 291
 292         while (pte < pte_end) {
 293                 INSTANCE_WR(priv->pramin_pt->gpuobj, (pte + 0)/4, vram | 1);
 294                 INSTANCE_WR(priv->pramin_pt->gpuobj, (pte + 4)/4, 0x00000000);
 295
 296                 pte += 8;
 297                 vram += NV50_INSTMEM_PAGE_SIZE;
 298         }
 299
 300         NV_WRITE(0x070000, 0x00000001);
 301         while(NV_READ(0x070000) & 1);
 302         NV_WRITE(0x100c80, 0x00040001);
 303         while(NV_READ(0x100c80) & 1);
 304         NV_WRITE(0x100c80, 0x00060001);
 305         while(NV_READ(0x100c80) & 1);
 306
 307         gpuobj->im_bound = 1;
 308         return 0;
 309 }
 310
 311 int
 312 nv50_instmem_unbind(struct drm_device *dev, struct nouveau_gpuobj *gpuobj)
 313 {
 314         struct drm_nouveau_private *dev_priv = dev->dev_private;
 315         nv50_instmem_priv *priv = dev_priv->Engine.instmem.priv;
 316         uint32_t pte, pte_end;
 317
 318         if (gpuobj->im_bound == 0)
 319                 return -EINVAL;
 320
 321         pte     = (gpuobj->im_pramin->start >> 12) << 3;
 322         pte_end = ((gpuobj->im_pramin->size >> 12) << 3) + pte;
 323         while (pte < pte_end) {
 324                 INSTANCE_WR(priv->pramin_pt->gpuobj, (pte + 0)/4, 0x00000009);
 325                 INSTANCE_WR(priv->pramin_pt->gpuobj, (pte + 4)/4, 0x00000000);
 326                 pte += 8;
 327         }
 328
 329         gpuobj->im_bound = 0;
 330         return 0;
 331 }