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[netbsd-mini2440.git] / sys / external / bsd / drm / dist / shared-core / radeon_cp.c
blobadc0789d1513e74a18c01b366310f4ddf194792b
1 /* radeon_cp.c -- CP support for Radeon -*- linux-c -*- */
2 /*
3 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
5 * Copyright 2007 Advanced Micro Devices, Inc.
6 * All Rights Reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
26 *
27 * Authors:
28 * Kevin E. Martin <martin@valinux.com>
29 * Gareth Hughes <gareth@valinux.com>
30 */
31
32 #include "drmP.h"
33 #include "drm.h"
34 #include "radeon_drm.h"
35 #include "radeon_drv.h"
36 #include "r300_reg.h"
37
38 #include "radeon_microcode.h"
39 #define RADEON_FIFO_DEBUG 0
40
41 static int radeon_do_cleanup_cp(struct drm_device * dev);
42 static void radeon_do_cp_start(drm_radeon_private_t * dev_priv);
43
44 u32 RADEON_READ_MM(drm_radeon_private_t *dev_priv, int addr)
45 {
46 u32 ret;
47
48 if (addr < 0x10000)
49 ret = DRM_READ32( dev_priv->mmio, addr );
50 else {
51 DRM_WRITE32( dev_priv->mmio, RADEON_MM_INDEX, addr );
52 ret = DRM_READ32( dev_priv->mmio, RADEON_MM_DATA );
53 }
54
55 return ret;
56 }
57
58 static u32 R500_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
59 {
60 u32 ret;
61 RADEON_WRITE(R520_MC_IND_INDEX, 0x7f0000 | (addr & 0xff));
62 ret = RADEON_READ(R520_MC_IND_DATA);
63 RADEON_WRITE(R520_MC_IND_INDEX, 0);
64 return ret;
65 }
66
67 static u32 RS480_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
68 {
69 u32 ret;
70 RADEON_WRITE(RS480_NB_MC_INDEX, addr & 0xff);
71 ret = RADEON_READ(RS480_NB_MC_DATA);
72 RADEON_WRITE(RS480_NB_MC_INDEX, 0xff);
73 return ret;
74 }
75
76 static u32 RS690_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
77 {
78 u32 ret;
79 RADEON_WRITE(RS690_MC_INDEX, (addr & RS690_MC_INDEX_MASK));
80 ret = RADEON_READ(RS690_MC_DATA);
81 RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_MASK);
82 return ret;
83 }
84
85 static u32 RS600_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
86 {
87 u32 ret;
88 RADEON_WRITE(RS600_MC_INDEX, ((addr & RS600_MC_ADDR_MASK) |
89 RS600_MC_IND_CITF_ARB0));
90 ret = RADEON_READ(RS600_MC_DATA);
91 return ret;
92 }
93
94 static u32 IGP_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
95 {
96 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
97 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
98 return RS690_READ_MCIND(dev_priv, addr);
99 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
100 return RS600_READ_MCIND(dev_priv, addr);
101 else
102 return RS480_READ_MCIND(dev_priv, addr);
103 }
104
105 u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv)
106 {
107 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)
108 return RADEON_READ(R700_MC_VM_FB_LOCATION);
109 else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
110 return RADEON_READ(R600_MC_VM_FB_LOCATION);
111 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
112 return R500_READ_MCIND(dev_priv, RV515_MC_FB_LOCATION);
113 else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
114 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
115 return RS690_READ_MCIND(dev_priv, RS690_MC_FB_LOCATION);
116 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
117 return RS600_READ_MCIND(dev_priv, RS600_MC_FB_LOCATION);
118 else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
119 return R500_READ_MCIND(dev_priv, R520_MC_FB_LOCATION);
120 else
121 return RADEON_READ(RADEON_MC_FB_LOCATION);
122 }
123
124 void radeon_write_fb_location(drm_radeon_private_t *dev_priv, u32 fb_loc)
125 {
126 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)
127 RADEON_WRITE(R700_MC_VM_FB_LOCATION, fb_loc);
128 else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
129 RADEON_WRITE(R600_MC_VM_FB_LOCATION, fb_loc);
130 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
131 R500_WRITE_MCIND(RV515_MC_FB_LOCATION, fb_loc);
132 else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
133 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
134 RS690_WRITE_MCIND(RS690_MC_FB_LOCATION, fb_loc);
135 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
136 RS600_WRITE_MCIND(RS600_MC_FB_LOCATION, fb_loc);
137 else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
138 R500_WRITE_MCIND(R520_MC_FB_LOCATION, fb_loc);
139 else
140 RADEON_WRITE(RADEON_MC_FB_LOCATION, fb_loc);
141 }
142
143 void radeon_write_agp_location(drm_radeon_private_t *dev_priv, u32 agp_loc)
144 {
145 /*R6xx/R7xx: AGP_TOP and BOT are actually 18 bits each */
146 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770) {
147 RADEON_WRITE(R700_MC_VM_AGP_BOT, agp_loc & 0xffff); /* FIX ME */
148 RADEON_WRITE(R700_MC_VM_AGP_TOP, (agp_loc >> 16) & 0xffff);
149 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) {
150 RADEON_WRITE(R600_MC_VM_AGP_BOT, agp_loc & 0xffff); /* FIX ME */
151 RADEON_WRITE(R600_MC_VM_AGP_TOP, (agp_loc >> 16) & 0xffff);
152 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
153 R500_WRITE_MCIND(RV515_MC_AGP_LOCATION, agp_loc);
154 else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
155 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
156 RS690_WRITE_MCIND(RS690_MC_AGP_LOCATION, agp_loc);
157 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
158 RS600_WRITE_MCIND(RS600_MC_AGP_LOCATION, agp_loc);
159 else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
160 R500_WRITE_MCIND(R520_MC_AGP_LOCATION, agp_loc);
161 else
162 RADEON_WRITE(RADEON_MC_AGP_LOCATION, agp_loc);
163 }
164
165 void radeon_write_agp_base(drm_radeon_private_t *dev_priv, u64 agp_base)
166 {
167 u32 agp_base_hi = upper_32_bits(agp_base);
168 u32 agp_base_lo = agp_base & 0xffffffff;
169 u32 r6xx_agp_base = (agp_base >> 22) & 0x3ffff;
170
171 // R6xx/R7xx must be aligned to a 4MB boundry
172 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)
173 RADEON_WRITE(R700_MC_VM_AGP_BASE, r6xx_agp_base); /* FIX ME */
174 else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
175 RADEON_WRITE(R600_MC_VM_AGP_BASE, r6xx_agp_base); /* FIX ME */
176 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) {
177 R500_WRITE_MCIND(RV515_MC_AGP_BASE, agp_base_lo);
178 R500_WRITE_MCIND(RV515_MC_AGP_BASE_2, agp_base_hi);
179 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
180 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) {
181 RS690_WRITE_MCIND(RS690_MC_AGP_BASE, agp_base_lo);
182 RS690_WRITE_MCIND(RS690_MC_AGP_BASE_2, agp_base_hi);
183 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) {
184 RS690_WRITE_MCIND(RS600_AGP_BASE, agp_base_lo);
185 RS690_WRITE_MCIND(RS600_AGP_BASE_2, agp_base_hi);
186 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) {
187 R500_WRITE_MCIND(R520_MC_AGP_BASE, agp_base_lo);
188 R500_WRITE_MCIND(R520_MC_AGP_BASE_2, agp_base_hi);
189 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) ||
190 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
191 RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo);
192 RADEON_WRITE(RS480_AGP_BASE_2, agp_base_hi);
193 } else {
194 RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo);
195 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R200)
196 RADEON_WRITE(RADEON_AGP_BASE_2, agp_base_hi);
197 }
198 }
199
200 static int RADEON_READ_PLL(struct drm_device * dev, int addr)
201 {
202 drm_radeon_private_t *dev_priv = dev->dev_private;
203
204 RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, addr & 0x1f);
205 return RADEON_READ(RADEON_CLOCK_CNTL_DATA);
206 }
207
208 static u32 RADEON_READ_PCIE(drm_radeon_private_t *dev_priv, int addr)
209 {
210 RADEON_WRITE8(RADEON_PCIE_INDEX, addr & 0xff);
211 return RADEON_READ(RADEON_PCIE_DATA);
212 }
213
214 #if RADEON_FIFO_DEBUG
215 static void radeon_status(drm_radeon_private_t * dev_priv)
216 {
217 printk("%s:\n", __FUNCTION__);
218 printk("RBBM_STATUS = 0x%08x\n",
219 (unsigned int)RADEON_READ(RADEON_RBBM_STATUS));
220 printk("CP_RB_RTPR = 0x%08x\n",
221 (unsigned int)RADEON_READ(RADEON_CP_RB_RPTR));
222 printk("CP_RB_WTPR = 0x%08x\n",
223 (unsigned int)RADEON_READ(RADEON_CP_RB_WPTR));
224 printk("AIC_CNTL = 0x%08x\n",
225 (unsigned int)RADEON_READ(RADEON_AIC_CNTL));
226 printk("AIC_STAT = 0x%08x\n",
227 (unsigned int)RADEON_READ(RADEON_AIC_STAT));
228 printk("AIC_PT_BASE = 0x%08x\n",
229 (unsigned int)RADEON_READ(RADEON_AIC_PT_BASE));
230 printk("TLB_ADDR = 0x%08x\n",
231 (unsigned int)RADEON_READ(RADEON_AIC_TLB_ADDR));
232 printk("TLB_DATA = 0x%08x\n",
233 (unsigned int)RADEON_READ(RADEON_AIC_TLB_DATA));
234 }
235 #endif
236
237 /* ================================================================
238 * Engine, FIFO control
239 */
240
241 static int radeon_do_pixcache_flush(drm_radeon_private_t * dev_priv)
242 {
243 u32 tmp;
244 int i;
245
246 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
247
248 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) {
249 tmp = RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT);
250 tmp |= RADEON_RB3D_DC_FLUSH_ALL;
251 RADEON_WRITE(RADEON_RB3D_DSTCACHE_CTLSTAT, tmp);
252
253 for (i = 0; i < dev_priv->usec_timeout; i++) {
254 if (!(RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT)
255 & RADEON_RB3D_DC_BUSY)) {
256 return 0;
257 }
258 DRM_UDELAY(1);
259 }
260 } else {
261 /* don't flush or purge cache here or lockup */
262 return 0;
263 }
264
265 #if RADEON_FIFO_DEBUG
266 DRM_ERROR("failed!\n");
267 radeon_status(dev_priv);
268 #endif
269 return -EBUSY;
270 }
271
272 static int radeon_do_wait_for_fifo(drm_radeon_private_t * dev_priv, int entries)
273 {
274 int i;
275
276 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
277
278 for (i = 0; i < dev_priv->usec_timeout; i++) {
279 int slots = (RADEON_READ(RADEON_RBBM_STATUS)
280 & RADEON_RBBM_FIFOCNT_MASK);
281 if (slots >= entries)
282 return 0;
283 DRM_UDELAY(1);
284 }
285 DRM_INFO("wait for fifo failed status : 0x%08X 0x%08X\n",
286 RADEON_READ(RADEON_RBBM_STATUS),
287 RADEON_READ(R300_VAP_CNTL_STATUS));
288
289 #if RADEON_FIFO_DEBUG
290 DRM_ERROR("failed!\n");
291 radeon_status(dev_priv);
292 #endif
293 return -EBUSY;
294 }
295
296 static int radeon_do_wait_for_idle(drm_radeon_private_t * dev_priv)
297 {
298 int i, ret;
299
300 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
301
302 ret = radeon_do_wait_for_fifo(dev_priv, 64);
303 if (ret)
304 return ret;
305
306 for (i = 0; i < dev_priv->usec_timeout; i++) {
307 if (!(RADEON_READ(RADEON_RBBM_STATUS)
308 & RADEON_RBBM_ACTIVE)) {
309 radeon_do_pixcache_flush(dev_priv);
310 return 0;
311 }
312 DRM_UDELAY(1);
313 }
314 DRM_INFO("wait idle failed status : 0x%08X 0x%08X\n",
315 RADEON_READ(RADEON_RBBM_STATUS),
316 RADEON_READ(R300_VAP_CNTL_STATUS));
317
318 #if RADEON_FIFO_DEBUG
319 DRM_ERROR("failed!\n");
320 radeon_status(dev_priv);
321 #endif
322 return -EBUSY;
323 }
324
325 static void radeon_init_pipes(drm_radeon_private_t * dev_priv)
326 {
327 uint32_t gb_tile_config, gb_pipe_sel = 0;
328
329 /* RS4xx/RS6xx/R4xx/R5xx */
330 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R420) {
331 gb_pipe_sel = RADEON_READ(R400_GB_PIPE_SELECT);
332 dev_priv->num_gb_pipes = ((gb_pipe_sel >> 12) & 0x3) + 1;
333 } else {
334 /* R3xx */
335 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300) ||
336 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350)) {
337 dev_priv->num_gb_pipes = 2;
338 } else {
339 /* R3Vxx */
340 dev_priv->num_gb_pipes = 1;
341 }
342 }
343 DRM_INFO("Num pipes: %d\n", dev_priv->num_gb_pipes);
344
345 gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16 /*| R300_SUBPIXEL_1_16*/);
346
347 switch(dev_priv->num_gb_pipes) {
348 case 2: gb_tile_config |= R300_PIPE_COUNT_R300; break;
349 case 3: gb_tile_config |= R300_PIPE_COUNT_R420_3P; break;
350 case 4: gb_tile_config |= R300_PIPE_COUNT_R420; break;
351 default:
352 case 1: gb_tile_config |= R300_PIPE_COUNT_RV350; break;
353 }
354
355 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV515) {
356 RADEON_WRITE_PLL(R500_DYN_SCLK_PWMEM_PIPE, (1 | ((gb_pipe_sel >> 8) & 0xf) << 4));
357 RADEON_WRITE(R500_SU_REG_DEST, ((1 << dev_priv->num_gb_pipes) - 1));
358 }
359 RADEON_WRITE(R300_GB_TILE_CONFIG, gb_tile_config);
360 radeon_do_wait_for_idle(dev_priv);
361 RADEON_WRITE(R300_DST_PIPE_CONFIG, RADEON_READ(R300_DST_PIPE_CONFIG) | R300_PIPE_AUTO_CONFIG);
362 RADEON_WRITE(R300_RB2D_DSTCACHE_MODE, (RADEON_READ(R300_RB2D_DSTCACHE_MODE) |
363 R300_DC_AUTOFLUSH_ENABLE |
364 R300_DC_DC_DISABLE_IGNORE_PE));
365
366
367 }
368
369 /* ================================================================
370 * CP control, initialization
371 */
372
373
374 /* Load the microcode for the CP */
375 static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv)
376 {
377 const u32 (*cp)[2];
378 int i;
379 DRM_DEBUG("\n");
380
381 switch (dev_priv->flags & RADEON_FAMILY_MASK) {
382 case CHIP_R100:
383 case CHIP_RV100:
384 case CHIP_RV200:
385 case CHIP_RS100:
386 case CHIP_RS200:
387 DRM_INFO("Loading R100 Microcode\n");
388 cp = R100_cp_microcode;
389 break;
390 case CHIP_R200:
391 case CHIP_RV250:
392 case CHIP_RV280:
393 case CHIP_RS300:
394 DRM_INFO("Loading R200 Microcode\n");
395 cp = R200_cp_microcode;
396 break;
397 case CHIP_R300:
398 case CHIP_R350:
399 case CHIP_RV350:
400 case CHIP_RV380:
401 case CHIP_RS400:
402 case CHIP_RS480:
403 DRM_INFO("Loading R300 Microcode\n");
404 cp = R300_cp_microcode;
405 break;
406 case CHIP_R420:
407 case CHIP_R423:
408 case CHIP_RV410:
409 DRM_INFO("Loading R400 Microcode\n");
410 cp = R420_cp_microcode;
411 break;
412 case CHIP_RS690:
413 case CHIP_RS740:
414 DRM_INFO("Loading RS690/RS740 Microcode\n");
415 cp = RS690_cp_microcode;
416 break;
417 case CHIP_RS600:
418 DRM_INFO("Loading RS600 Microcode\n");
419 cp = RS600_cp_microcode;
420 break;
421 case CHIP_RV515:
422 case CHIP_R520:
423 case CHIP_RV530:
424 case CHIP_R580:
425 case CHIP_RV560:
426 case CHIP_RV570:
427 DRM_INFO("Loading R500 Microcode\n");
428 cp = R520_cp_microcode;
429 break;
430 default:
431 return;
432 }
433
434 radeon_do_wait_for_idle(dev_priv);
435
436 RADEON_WRITE(RADEON_CP_ME_RAM_ADDR, 0);
437
438 for (i = 0; i != 256; i++) {
439 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH, cp[i][1]);
440 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL, cp[i][0]);
441 }
442 }
443
444
445
446
447 /* Flush any pending commands to the CP. This should only be used just
448 * prior to a wait for idle, as it informs the engine that the command
449 * stream is ending.
450 */
451 static void radeon_do_cp_flush(drm_radeon_private_t * dev_priv)
452 {
453 DRM_DEBUG("\n");
454 #if 0
455 u32 tmp;
456
457 tmp = RADEON_READ(RADEON_CP_RB_WPTR) | (1 << 31);
458 RADEON_WRITE(RADEON_CP_RB_WPTR, tmp);
459 #endif
460 }
461
462 /* Wait for the CP to go idle.
463 */
464 int radeon_do_cp_idle(drm_radeon_private_t * dev_priv)
465 {
466 RING_LOCALS;
467 DRM_DEBUG("\n");
468
469 BEGIN_RING(6);
470
471 RADEON_PURGE_CACHE();
472 RADEON_PURGE_ZCACHE();
473 RADEON_WAIT_UNTIL_IDLE();
474
475 ADVANCE_RING();
476 COMMIT_RING();
477
478 return radeon_do_wait_for_idle(dev_priv);
479 }
480
481 /* Start the Command Processor.
482 */
483 static void radeon_do_cp_start(drm_radeon_private_t * dev_priv)
484 {
485 RING_LOCALS;
486 DRM_DEBUG("\n");
487
488 radeon_do_wait_for_idle(dev_priv);
489
490 RADEON_WRITE(RADEON_CP_CSQ_CNTL, dev_priv->cp_mode);
491
492 dev_priv->cp_running = 1;
493
494 BEGIN_RING(8);
495 /* isync can only be written through cp on r5xx write it here */
496 OUT_RING(CP_PACKET0(RADEON_ISYNC_CNTL, 0));
497 OUT_RING(RADEON_ISYNC_ANY2D_IDLE3D |
498 RADEON_ISYNC_ANY3D_IDLE2D |
499 RADEON_ISYNC_WAIT_IDLEGUI |
500 RADEON_ISYNC_CPSCRATCH_IDLEGUI);
501 RADEON_PURGE_CACHE();
502 RADEON_PURGE_ZCACHE();
503 RADEON_WAIT_UNTIL_IDLE();
504 ADVANCE_RING();
505 COMMIT_RING();
506
507 dev_priv->track_flush |= RADEON_FLUSH_EMITED | RADEON_PURGE_EMITED;
508 }
509
510 /* Reset the Command Processor. This will not flush any pending
511 * commands, so you must wait for the CP command stream to complete
512 * before calling this routine.
513 */
514 static void radeon_do_cp_reset(drm_radeon_private_t * dev_priv)
515 {
516 u32 cur_read_ptr;
517 DRM_DEBUG("\n");
518
519 cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
520 RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
521 SET_RING_HEAD(dev_priv, cur_read_ptr);
522 dev_priv->ring.tail = cur_read_ptr;
523 }
524
525 /* Stop the Command Processor. This will not flush any pending
526 * commands, so you must flush the command stream and wait for the CP
527 * to go idle before calling this routine.
528 */
529 static void radeon_do_cp_stop(drm_radeon_private_t * dev_priv)
530 {
531 DRM_DEBUG("\n");
532
533 RADEON_WRITE(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS);
534
535 dev_priv->cp_running = 0;
536 }
537
538 /* Reset the engine. This will stop the CP if it is running.
539 */
540 static int radeon_do_engine_reset(struct drm_device * dev)
541 {
542 drm_radeon_private_t *dev_priv = dev->dev_private;
543 u32 clock_cntl_index = 0, mclk_cntl = 0, rbbm_soft_reset;
544 DRM_DEBUG("\n");
545
546 radeon_do_pixcache_flush(dev_priv);
547
548 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) {
549 /* may need something similar for newer chips */
550 clock_cntl_index = RADEON_READ(RADEON_CLOCK_CNTL_INDEX);
551 mclk_cntl = RADEON_READ_PLL(dev, RADEON_MCLK_CNTL);
552
553 RADEON_WRITE_PLL(RADEON_MCLK_CNTL, (mclk_cntl |
554 RADEON_FORCEON_MCLKA |
555 RADEON_FORCEON_MCLKB |
556 RADEON_FORCEON_YCLKA |
557 RADEON_FORCEON_YCLKB |
558 RADEON_FORCEON_MC |
559 RADEON_FORCEON_AIC));
560 }
561
562 rbbm_soft_reset = RADEON_READ(RADEON_RBBM_SOFT_RESET);
563
564 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset |
565 RADEON_SOFT_RESET_CP |
566 RADEON_SOFT_RESET_HI |
567 RADEON_SOFT_RESET_SE |
568 RADEON_SOFT_RESET_RE |
569 RADEON_SOFT_RESET_PP |
570 RADEON_SOFT_RESET_E2 |
571 RADEON_SOFT_RESET_RB));
572 RADEON_READ(RADEON_RBBM_SOFT_RESET);
573 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset &
574 ~(RADEON_SOFT_RESET_CP |
575 RADEON_SOFT_RESET_HI |
576 RADEON_SOFT_RESET_SE |
577 RADEON_SOFT_RESET_RE |
578 RADEON_SOFT_RESET_PP |
579 RADEON_SOFT_RESET_E2 |
580 RADEON_SOFT_RESET_RB)));
581 RADEON_READ(RADEON_RBBM_SOFT_RESET);
582
583 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) {
584 RADEON_WRITE_PLL(RADEON_MCLK_CNTL, mclk_cntl);
585 RADEON_WRITE(RADEON_CLOCK_CNTL_INDEX, clock_cntl_index);
586 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, rbbm_soft_reset);
587 }
588
589 /* setup the raster pipes */
590 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R300)
591 radeon_init_pipes(dev_priv);
592
593 /* Reset the CP ring */
594 radeon_do_cp_reset(dev_priv);
595
596 /* The CP is no longer running after an engine reset */
597 dev_priv->cp_running = 0;
598
599 /* Reset any pending vertex, indirect buffers */
600 radeon_freelist_reset(dev);
601
602 return 0;
603 }
604
605 static void radeon_cp_init_ring_buffer(struct drm_device * dev,
606 drm_radeon_private_t * dev_priv)
607 {
608 u32 ring_start, cur_read_ptr;
609 u32 tmp;
610
611 /* Initialize the memory controller. With new memory map, the fb location
612 * is not changed, it should have been properly initialized already. Part
613 * of the problem is that the code below is bogus, assuming the GART is
614 * always appended to the fb which is not necessarily the case
615 */
616 if (!dev_priv->new_memmap)
617 radeon_write_fb_location(dev_priv,
618 ((dev_priv->gart_vm_start - 1) & 0xffff0000)
619 | (dev_priv->fb_location >> 16));
620
621 #if __OS_HAS_AGP
622 if (dev_priv->flags & RADEON_IS_AGP) {
623 radeon_write_agp_base(dev_priv, dev->agp->base);
624
625 radeon_write_agp_location(dev_priv,
626 (((dev_priv->gart_vm_start - 1 +
627 dev_priv->gart_size) & 0xffff0000) |
628 (dev_priv->gart_vm_start >> 16)));
629
630 ring_start = (dev_priv->cp_ring->offset
631 - dev->agp->base
632 + dev_priv->gart_vm_start);
633 } else
634 #endif
635 ring_start = (dev_priv->cp_ring->offset
636 - (unsigned long)dev->sg->virtual
637 + dev_priv->gart_vm_start);
638
639 RADEON_WRITE(RADEON_CP_RB_BASE, ring_start);
640
641 /* Set the write pointer delay */
642 RADEON_WRITE(RADEON_CP_RB_WPTR_DELAY, 0);
643
644 /* Initialize the ring buffer's read and write pointers */
645 cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
646 RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
647 SET_RING_HEAD(dev_priv, cur_read_ptr);
648 dev_priv->ring.tail = cur_read_ptr;
649
650 #if __OS_HAS_AGP
651 if (dev_priv->flags & RADEON_IS_AGP) {
652 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR,
653 dev_priv->ring_rptr->offset
654 - dev->agp->base + dev_priv->gart_vm_start);
655 } else
656 #endif
657 {
658 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR,
659 dev_priv->ring_rptr->offset
660 - ((unsigned long) dev->sg->virtual)
661 + dev_priv->gart_vm_start);
662 }
663
664 /* Set ring buffer size */
665 #ifdef __BIG_ENDIAN
666 RADEON_WRITE(RADEON_CP_RB_CNTL,
667 RADEON_BUF_SWAP_32BIT |
668 (dev_priv->ring.fetch_size_l2ow << 18) |
669 (dev_priv->ring.rptr_update_l2qw << 8) |
670 dev_priv->ring.size_l2qw);
671 #else
672 RADEON_WRITE(RADEON_CP_RB_CNTL,
673 (dev_priv->ring.fetch_size_l2ow << 18) |
674 (dev_priv->ring.rptr_update_l2qw << 8) |
675 dev_priv->ring.size_l2qw);
676 #endif
677
678 /* Initialize the scratch register pointer. This will cause
679 * the scratch register values to be written out to memory
680 * whenever they are updated.
681 *
682 * We simply put this behind the ring read pointer, this works
683 * with PCI GART as well as (whatever kind of) AGP GART
684 */
685 RADEON_WRITE(RADEON_SCRATCH_ADDR, RADEON_READ(RADEON_CP_RB_RPTR_ADDR)
686 + RADEON_SCRATCH_REG_OFFSET);
687
688 dev_priv->scratch = ((__volatile__ u32 *)
689 dev_priv->ring_rptr->handle +
690 (RADEON_SCRATCH_REG_OFFSET / sizeof(u32)));
691
692 RADEON_WRITE(RADEON_SCRATCH_UMSK, 0x7);
693
694 /* Turn on bus mastering */
695 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
696 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) {
697 /* rs600/rs690/rs740 */
698 tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS;
699 RADEON_WRITE(RADEON_BUS_CNTL, tmp);
700 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV350) ||
701 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) ||
702 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) ||
703 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
704 /* r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
705 tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
706 RADEON_WRITE(RADEON_BUS_CNTL, tmp);
707 } /* PCIE cards appears to not need this */
708
709 dev_priv->sarea_priv->last_frame = dev_priv->scratch[0] = 0;
710 RADEON_WRITE(RADEON_LAST_FRAME_REG, dev_priv->sarea_priv->last_frame);
711
712 dev_priv->sarea_priv->last_dispatch = dev_priv->scratch[1] = 0;
713 RADEON_WRITE(RADEON_LAST_DISPATCH_REG,
714 dev_priv->sarea_priv->last_dispatch);
715
716 dev_priv->sarea_priv->last_clear = dev_priv->scratch[2] = 0;
717 RADEON_WRITE(RADEON_LAST_CLEAR_REG, dev_priv->sarea_priv->last_clear);
718
719 radeon_do_wait_for_idle(dev_priv);
720
721 /* Sync everything up */
722 RADEON_WRITE(RADEON_ISYNC_CNTL,
723 (RADEON_ISYNC_ANY2D_IDLE3D |
724 RADEON_ISYNC_ANY3D_IDLE2D |
725 RADEON_ISYNC_WAIT_IDLEGUI |
726 RADEON_ISYNC_CPSCRATCH_IDLEGUI));
727
728 }
729
730 static void radeon_test_writeback(drm_radeon_private_t * dev_priv)
731 {
732 u32 tmp;
733
734 /* Writeback doesn't seem to work everywhere, test it here and possibly
735 * enable it if it appears to work
736 */
737 DRM_WRITE32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1), 0);
738 RADEON_WRITE(RADEON_SCRATCH_REG1, 0xdeadbeef);
739
740 for (tmp = 0; tmp < dev_priv->usec_timeout; tmp++) {
741 if (DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1)) ==
742 0xdeadbeef)
743 break;
744 DRM_UDELAY(1);
745 }
746
747 if (tmp < dev_priv->usec_timeout) {
748 dev_priv->writeback_works = 1;
749 DRM_INFO("writeback test succeeded in %d usecs\n", tmp);
750 } else {
751 dev_priv->writeback_works = 0;
752 DRM_INFO("writeback test failed\n");
753 }
754 if (radeon_no_wb == 1) {
755 dev_priv->writeback_works = 0;
756 DRM_INFO("writeback forced off\n");
757 }
758
759 if (!dev_priv->writeback_works) {
760 /* Disable writeback to avoid unnecessary bus master transfers */
761 RADEON_WRITE(RADEON_CP_RB_CNTL, RADEON_READ(RADEON_CP_RB_CNTL) | RADEON_RB_NO_UPDATE);
762 RADEON_WRITE(RADEON_SCRATCH_UMSK, 0);
763 }
764 }
765
766 /* Enable or disable IGP GART on the chip */
767 static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on)
768 {
769 u32 temp;
770
771 if (on) {
772 DRM_DEBUG("programming igp gart %08X %08lX %08X\n",
773 dev_priv->gart_vm_start,
774 (long)dev_priv->gart_info.bus_addr,
775 dev_priv->gart_size);
776
777 temp = IGP_READ_MCIND(dev_priv, RS480_MC_MISC_CNTL);
778
779 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
780 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
781 IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, (RS480_GART_INDEX_REG_EN |
782 RS690_BLOCK_GFX_D3_EN));
783 else
784 IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, RS480_GART_INDEX_REG_EN);
785
786 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN |
787 RS480_VA_SIZE_32MB));
788
789 temp = IGP_READ_MCIND(dev_priv, RS480_GART_FEATURE_ID);
790 IGP_WRITE_MCIND(RS480_GART_FEATURE_ID, (RS480_HANG_EN |
791 RS480_TLB_ENABLE |
792 RS480_GTW_LAC_EN |
793 RS480_1LEVEL_GART));
794
795 temp = dev_priv->gart_info.bus_addr & 0xfffff000;
796 temp |= (upper_32_bits(dev_priv->gart_info.bus_addr) & 0xff) << 4;
797 IGP_WRITE_MCIND(RS480_GART_BASE, temp);
798
799 temp = IGP_READ_MCIND(dev_priv, RS480_AGP_MODE_CNTL);
800 IGP_WRITE_MCIND(RS480_AGP_MODE_CNTL, ((1 << RS480_REQ_TYPE_SNOOP_SHIFT) |
801 RS480_REQ_TYPE_SNOOP_DIS));
802
803 radeon_write_agp_base(dev_priv, dev_priv->gart_vm_start);
804
805 dev_priv->gart_size = 32*1024*1024;
806 temp = (((dev_priv->gart_vm_start - 1 + dev_priv->gart_size) &
807 0xffff0000) | (dev_priv->gart_vm_start >> 16));
808
809 radeon_write_agp_location(dev_priv, temp);
810
811 temp = IGP_READ_MCIND(dev_priv, RS480_AGP_ADDRESS_SPACE_SIZE);
812 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN |
813 RS480_VA_SIZE_32MB));
814
815 do {
816 temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL);
817 if ((temp & RS480_GART_CACHE_INVALIDATE) == 0)
818 break;
819 DRM_UDELAY(1);
820 } while(1);
821
822 IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL,
823 RS480_GART_CACHE_INVALIDATE);
824
825 do {
826 temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL);
827 if ((temp & RS480_GART_CACHE_INVALIDATE) == 0)
828 break;
829 DRM_UDELAY(1);
830 } while(1);
831
832 IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL, 0);
833 } else {
834 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, 0);
835 }
836 }
837
838 /* Enable or disable IGP GART on the chip */
839 static void rs600_set_igpgart(drm_radeon_private_t * dev_priv, int on)
840 {
841 u32 temp;
842 int i;
843
844 if (on) {
845 DRM_DEBUG("programming igp gart %08X %08lX %08X\n",
846 dev_priv->gart_vm_start,
847 (long)dev_priv->gart_info.bus_addr,
848 dev_priv->gart_size);
849
850 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, (RS600_EFFECTIVE_L2_CACHE_SIZE(6) |
851 RS600_EFFECTIVE_L2_QUEUE_SIZE(6)));
852
853 for (i = 0; i < 19; i++)
854 IGP_WRITE_MCIND(RS600_MC_PT0_CLIENT0_CNTL + i,
855 (RS600_ENABLE_TRANSLATION_MODE_OVERRIDE |
856 RS600_SYSTEM_ACCESS_MODE_IN_SYS |
857 RS600_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASSTHROUGH |
858 RS600_EFFECTIVE_L1_CACHE_SIZE(3) |
859 RS600_ENABLE_FRAGMENT_PROCESSING |
860 RS600_EFFECTIVE_L1_QUEUE_SIZE(3)));
861
862 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_CNTL, (RS600_ENABLE_PAGE_TABLE |
863 RS600_PAGE_TABLE_TYPE_FLAT));
864
865 /* disable all other contexts */
866 for (i = 1; i < 8; i++)
867 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_CNTL + i, 0);
868
869 /* setup the page table aperture */
870 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_FLAT_BASE_ADDR,
871 dev_priv->gart_info.bus_addr);
872 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_FLAT_START_ADDR,
873 dev_priv->gart_vm_start);
874 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_FLAT_END_ADDR,
875 (dev_priv->gart_vm_start + dev_priv->gart_size - 1));
876 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR, 0);
877
878 /* setup the system aperture */
879 IGP_WRITE_MCIND(RS600_MC_PT0_SYSTEM_APERTURE_LOW_ADDR,
880 dev_priv->gart_vm_start);
881 IGP_WRITE_MCIND(RS600_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR,
882 (dev_priv->gart_vm_start + dev_priv->gart_size - 1));
883
884 /* enable page tables */
885 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
886 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, (temp | RS600_ENABLE_PT));
887
888 temp = IGP_READ_MCIND(dev_priv, RS600_MC_CNTL1);
889 IGP_WRITE_MCIND(RS600_MC_CNTL1, (temp | RS600_ENABLE_PAGE_TABLES));
890
891 /* invalidate the cache */
892 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
893
894 temp &= ~(RS600_INVALIDATE_ALL_L1_TLBS | RS600_INVALIDATE_L2_CACHE);
895 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, temp);
896 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
897
898 temp |= RS600_INVALIDATE_ALL_L1_TLBS | RS600_INVALIDATE_L2_CACHE;
899 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, temp);
900 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
901
902 temp &= ~(RS600_INVALIDATE_ALL_L1_TLBS | RS600_INVALIDATE_L2_CACHE);
903 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, temp);
904 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
905
906 } else {
907 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, 0);
908 temp = IGP_READ_MCIND(dev_priv, RS600_MC_CNTL1);
909 temp &= ~RS600_ENABLE_PAGE_TABLES;
910 IGP_WRITE_MCIND(RS600_MC_CNTL1, temp);
911 }
912 }
913
914 static void radeon_set_pciegart(drm_radeon_private_t * dev_priv, int on)
915 {
916 u32 tmp = RADEON_READ_PCIE(dev_priv, RADEON_PCIE_TX_GART_CNTL);
917 if (on) {
918
919 DRM_DEBUG("programming pcie %08X %08lX %08X\n",
920 dev_priv->gart_vm_start,
921 (long)dev_priv->gart_info.bus_addr,
922 dev_priv->gart_size);
923 RADEON_WRITE_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO,
924 dev_priv->gart_vm_start);
925 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_BASE,
926 dev_priv->gart_info.bus_addr);
927 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_START_LO,
928 dev_priv->gart_vm_start);
929 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_END_LO,
930 dev_priv->gart_vm_start +
931 dev_priv->gart_size - 1);
932
933 radeon_write_agp_location(dev_priv, 0xffffffc0); /* ?? */
934
935 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
936 RADEON_PCIE_TX_GART_EN);
937 } else {
938 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
939 tmp & ~RADEON_PCIE_TX_GART_EN);
940 }
941 }
942
943 /* Enable or disable PCI GART on the chip */
944 static void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on)
945 {
946 u32 tmp;
947
948 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
949 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740) ||
950 (dev_priv->flags & RADEON_IS_IGPGART)) {
951 radeon_set_igpgart(dev_priv, on);
952 return;
953 }
954
955 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) {
956 rs600_set_igpgart(dev_priv, on);
957 return;
958 }
959
960 if (dev_priv->flags & RADEON_IS_PCIE) {
961 radeon_set_pciegart(dev_priv, on);
962 return;
963 }
964
965 tmp = RADEON_READ(RADEON_AIC_CNTL);
966
967 if (on) {
968 RADEON_WRITE(RADEON_AIC_CNTL,
969 tmp | RADEON_PCIGART_TRANSLATE_EN);
970
971 /* set PCI GART page-table base address
972 */
973 RADEON_WRITE(RADEON_AIC_PT_BASE, dev_priv->gart_info.bus_addr);
974
975 /* set address range for PCI address translate
976 */
977 RADEON_WRITE(RADEON_AIC_LO_ADDR, dev_priv->gart_vm_start);
978 RADEON_WRITE(RADEON_AIC_HI_ADDR, dev_priv->gart_vm_start
979 + dev_priv->gart_size - 1);
980
981 /* Turn off AGP aperture -- is this required for PCI GART?
982 */
983 radeon_write_agp_location(dev_priv, 0xffffffc0);
984 RADEON_WRITE(RADEON_AGP_COMMAND, 0); /* clear AGP_COMMAND */
985 } else {
986 RADEON_WRITE(RADEON_AIC_CNTL,
987 tmp & ~RADEON_PCIGART_TRANSLATE_EN);
988 }
989 }
990
991 static int radeon_do_init_cp(struct drm_device * dev, drm_radeon_init_t * init)
992 {
993 drm_radeon_private_t *dev_priv = dev->dev_private;
994 int ret;
995
996 DRM_DEBUG("\n");
997
998 /* if we require new memory map but we don't have it fail */
999 if ((dev_priv->flags & RADEON_NEW_MEMMAP) && !dev_priv->new_memmap) {
1000 DRM_ERROR("Cannot initialise DRM on this card\nThis card requires a new X.org DDX for 3D\n");
1001 radeon_do_cleanup_cp(dev);
1002 return -EINVAL;
1003 }
1004
1005 if (init->is_pci && (dev_priv->flags & RADEON_IS_AGP))
1006 {
1007 DRM_DEBUG("Forcing AGP card to PCI mode\n");
1008 dev_priv->flags &= ~RADEON_IS_AGP;
1009 }
1010 else if (!(dev_priv->flags & (RADEON_IS_AGP | RADEON_IS_PCI | RADEON_IS_PCIE))
1011 && !init->is_pci)
1012 {
1013 DRM_DEBUG("Restoring AGP flag\n");
1014 dev_priv->flags |= RADEON_IS_AGP;
1015 }
1016
1017 if ((!(dev_priv->flags & RADEON_IS_AGP)) && !dev->sg) {
1018 DRM_ERROR("PCI GART memory not allocated!\n");
1019 radeon_do_cleanup_cp(dev);
1020 return -EINVAL;
1021 }
1022
1023 dev_priv->usec_timeout = init->usec_timeout;
1024 if (dev_priv->usec_timeout < 1 ||
1025 dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT) {
1026 DRM_DEBUG("TIMEOUT problem!\n");
1027 radeon_do_cleanup_cp(dev);
1028 return -EINVAL;
1029 }
1030
1031 /* Enable vblank on CRTC1 for older X servers
1032 */
1033 dev_priv->vblank_crtc = DRM_RADEON_VBLANK_CRTC1;
1034
1035 dev_priv->do_boxes = 0;
1036 dev_priv->cp_mode = init->cp_mode;
1037
1038 /* We don't support anything other than bus-mastering ring mode,
1039 * but the ring can be in either AGP or PCI space for the ring
1040 * read pointer.
1041 */
1042 if ((init->cp_mode != RADEON_CSQ_PRIBM_INDDIS) &&
1043 (init->cp_mode != RADEON_CSQ_PRIBM_INDBM)) {
1044 DRM_DEBUG("BAD cp_mode (%x)!\n", init->cp_mode);
1045 radeon_do_cleanup_cp(dev);
1046 return -EINVAL;
1047 }
1048
1049 switch (init->fb_bpp) {
1050 case 16:
1051 dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565;
1052 break;
1053 case 32:
1054 default:
1055 dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888;
1056 break;
1057 }
1058 dev_priv->front_offset = init->front_offset;
1059 dev_priv->front_pitch = init->front_pitch;
1060 dev_priv->back_offset = init->back_offset;
1061 dev_priv->back_pitch = init->back_pitch;
1062
1063 switch (init->depth_bpp) {
1064 case 16:
1065 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z;
1066 break;
1067 case 32:
1068 default:
1069 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;
1070 break;
1071 }
1072 dev_priv->depth_offset = init->depth_offset;
1073 dev_priv->depth_pitch = init->depth_pitch;
1074
1075 /* Hardware state for depth clears. Remove this if/when we no
1076 * longer clear the depth buffer with a 3D rectangle. Hard-code
1077 * all values to prevent unwanted 3D state from slipping through
1078 * and screwing with the clear operation.
1079 */
1080 dev_priv->depth_clear.rb3d_cntl = (RADEON_PLANE_MASK_ENABLE |
1081 (dev_priv->color_fmt << 10) |
1082 (dev_priv->chip_family < CHIP_R200 ? RADEON_ZBLOCK16 : 0));
1083
1084 dev_priv->depth_clear.rb3d_zstencilcntl =
1085 (dev_priv->depth_fmt |
1086 RADEON_Z_TEST_ALWAYS |
1087 RADEON_STENCIL_TEST_ALWAYS |
1088 RADEON_STENCIL_S_FAIL_REPLACE |
1089 RADEON_STENCIL_ZPASS_REPLACE |
1090 RADEON_STENCIL_ZFAIL_REPLACE | RADEON_Z_WRITE_ENABLE);
1091
1092 dev_priv->depth_clear.se_cntl = (RADEON_FFACE_CULL_CW |
1093 RADEON_BFACE_SOLID |
1094 RADEON_FFACE_SOLID |
1095 RADEON_FLAT_SHADE_VTX_LAST |
1096 RADEON_DIFFUSE_SHADE_FLAT |
1097 RADEON_ALPHA_SHADE_FLAT |
1098 RADEON_SPECULAR_SHADE_FLAT |
1099 RADEON_FOG_SHADE_FLAT |
1100 RADEON_VTX_PIX_CENTER_OGL |
1101 RADEON_ROUND_MODE_TRUNC |
1102 RADEON_ROUND_PREC_8TH_PIX);
1103
1104
1105 dev_priv->ring_offset = init->ring_offset;
1106 dev_priv->ring_rptr_offset = init->ring_rptr_offset;
1107 dev_priv->buffers_offset = init->buffers_offset;
1108 dev_priv->gart_textures_offset = init->gart_textures_offset;
1109
1110 dev_priv->sarea = drm_getsarea(dev);
1111 if (!dev_priv->sarea) {
1112 DRM_ERROR("could not find sarea!\n");
1113 radeon_do_cleanup_cp(dev);
1114 return -EINVAL;
1115 }
1116
1117 dev_priv->cp_ring = drm_core_findmap(dev, init->ring_offset);
1118 if (!dev_priv->cp_ring) {
1119 DRM_ERROR("could not find cp ring region!\n");
1120 radeon_do_cleanup_cp(dev);
1121 return -EINVAL;
1122 }
1123 dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset);
1124 if (!dev_priv->ring_rptr) {
1125 DRM_ERROR("could not find ring read pointer!\n");
1126 radeon_do_cleanup_cp(dev);
1127 return -EINVAL;
1128 }
1129 dev->agp_buffer_token = init->buffers_offset;
1130 dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset);
1131 if (!dev->agp_buffer_map) {
1132 DRM_ERROR("could not find dma buffer region!\n");
1133 radeon_do_cleanup_cp(dev);
1134 return -EINVAL;
1135 }
1136
1137 if (init->gart_textures_offset) {
1138 dev_priv->gart_textures =
1139 drm_core_findmap(dev, init->gart_textures_offset);
1140 if (!dev_priv->gart_textures) {
1141 DRM_ERROR("could not find GART texture region!\n");
1142 radeon_do_cleanup_cp(dev);
1143 return -EINVAL;
1144 }
1145 }
1146
1147 dev_priv->sarea_priv =
1148 (drm_radeon_sarea_t *) ((u8 *) dev_priv->sarea->handle +
1149 init->sarea_priv_offset);
1150
1151 #if __OS_HAS_AGP
1152 if (dev_priv->flags & RADEON_IS_AGP) {
1153 drm_core_ioremap_wc(dev_priv->cp_ring, dev);
1154 drm_core_ioremap_wc(dev_priv->ring_rptr, dev);
1155 drm_core_ioremap_wc(dev->agp_buffer_map, dev);
1156 if (!dev_priv->cp_ring->handle ||
1157 !dev_priv->ring_rptr->handle ||
1158 !dev->agp_buffer_map->handle) {
1159 DRM_ERROR("could not find ioremap agp regions!\n");
1160 radeon_do_cleanup_cp(dev);
1161 return -EINVAL;
1162 }
1163 } else
1164 #endif
1165 {
1166 dev_priv->cp_ring->handle = (void *)dev_priv->cp_ring->offset;
1167 dev_priv->ring_rptr->handle =
1168 (void *)dev_priv->ring_rptr->offset;
1169 dev->agp_buffer_map->handle =
1170 (void *)dev->agp_buffer_map->offset;
1171
1172 DRM_DEBUG("dev_priv->cp_ring->handle %p\n",
1173 dev_priv->cp_ring->handle);
1174 DRM_DEBUG("dev_priv->ring_rptr->handle %p\n",
1175 dev_priv->ring_rptr->handle);
1176 DRM_DEBUG("dev->agp_buffer_map->handle %p\n",
1177 dev->agp_buffer_map->handle);
1178 }
1179
1180 dev_priv->fb_location = (radeon_read_fb_location(dev_priv) & 0xffff) << 16;
1181 dev_priv->fb_size =
1182 ((radeon_read_fb_location(dev_priv) & 0xffff0000u) + 0x10000)
1183 - dev_priv->fb_location;
1184
1185 dev_priv->front_pitch_offset = (((dev_priv->front_pitch / 64) << 22) |
1186 ((dev_priv->front_offset
1187 + dev_priv->fb_location) >> 10));
1188
1189 dev_priv->back_pitch_offset = (((dev_priv->back_pitch / 64) << 22) |
1190 ((dev_priv->back_offset
1191 + dev_priv->fb_location) >> 10));
1192
1193 dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch / 64) << 22) |
1194 ((dev_priv->depth_offset
1195 + dev_priv->fb_location) >> 10));
1196
1197 dev_priv->gart_size = init->gart_size;
1198
1199 /* New let's set the memory map ... */
1200 if (dev_priv->new_memmap) {
1201 u32 base = 0;
1202
1203 DRM_INFO("Setting GART location based on new memory map\n");
1204
1205 /* If using AGP, try to locate the AGP aperture at the same
1206 * location in the card and on the bus, though we have to
1207 * align it down.
1208 */
1209 #if __OS_HAS_AGP
1210 if (dev_priv->flags & RADEON_IS_AGP) {
1211 base = dev->agp->base;
1212 /* Check if valid */
1213 if ((base + dev_priv->gart_size - 1) >= dev_priv->fb_location &&
1214 base < (dev_priv->fb_location + dev_priv->fb_size - 1)) {
1215 DRM_INFO("Can't use AGP base @0x%08lx, won't fit\n",
1216 dev->agp->base);
1217 base = 0;
1218 }
1219 }
1220 #endif
1221 /* If not or if AGP is at 0 (Macs), try to put it elsewhere */
1222 if (base == 0) {
1223 base = dev_priv->fb_location + dev_priv->fb_size;
1224 if (base < dev_priv->fb_location ||
1225 ((base + dev_priv->gart_size) & 0xfffffffful) < base)
1226 base = dev_priv->fb_location
1227 - dev_priv->gart_size;
1228 }
1229 dev_priv->gart_vm_start = base & 0xffc00000u;
1230 if (dev_priv->gart_vm_start != base)
1231 DRM_INFO("GART aligned down from 0x%08x to 0x%08x\n",
1232 base, dev_priv->gart_vm_start);
1233 } else {
1234 DRM_INFO("Setting GART location based on old memory map\n");
1235 dev_priv->gart_vm_start = dev_priv->fb_location +
1236 RADEON_READ(RADEON_CONFIG_APER_SIZE);
1237 }
1238
1239 #if __OS_HAS_AGP
1240 if (dev_priv->flags & RADEON_IS_AGP)
1241 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1242 - dev->agp->base
1243 + dev_priv->gart_vm_start);
1244 else
1245 #endif
1246 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1247 - (unsigned long)dev->sg->virtual
1248 + dev_priv->gart_vm_start);
1249
1250 DRM_DEBUG("dev_priv->gart_size %d\n", dev_priv->gart_size);
1251 DRM_DEBUG("dev_priv->gart_vm_start 0x%x\n",
1252 (unsigned int) dev_priv->gart_vm_start);
1253 DRM_DEBUG("dev_priv->gart_buffers_offset 0x%lx\n",
1254 dev_priv->gart_buffers_offset);
1255
1256 dev_priv->ring.start = (u32 *) dev_priv->cp_ring->handle;
1257 dev_priv->ring.end = ((u32 *) dev_priv->cp_ring->handle
1258 + init->ring_size / sizeof(u32));
1259 dev_priv->ring.size = init->ring_size;
1260 dev_priv->ring.size_l2qw = drm_order(init->ring_size / 8);
1261
1262 dev_priv->ring.rptr_update = /* init->rptr_update */ 4096;
1263 dev_priv->ring.rptr_update_l2qw = drm_order( /* init->rptr_update */ 4096 / 8);
1264
1265 dev_priv->ring.fetch_size = /* init->fetch_size */ 32;
1266 dev_priv->ring.fetch_size_l2ow = drm_order( /* init->fetch_size */ 32 / 16);
1267
1268 dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1;
1269
1270 dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK;
1271
1272 #if __OS_HAS_AGP
1273 if (dev_priv->flags & RADEON_IS_AGP) {
1274 /* Turn off PCI GART */
1275 radeon_set_pcigart(dev_priv, 0);
1276 } else
1277 #endif
1278 {
1279 dev_priv->gart_info.table_mask = DMA_BIT_MASK(32);
1280 /* if we have an offset set from userspace */
1281 if (dev_priv->pcigart_offset_set) {
1282 dev_priv->gart_info.bus_addr =
1283 dev_priv->pcigart_offset + dev_priv->fb_location;
1284 dev_priv->gart_info.mapping.offset =
1285 dev_priv->pcigart_offset + dev_priv->fb_aper_offset;
1286 dev_priv->gart_info.mapping.size =
1287 dev_priv->gart_info.table_size;
1288
1289 drm_core_ioremap_wc(&dev_priv->gart_info.mapping, dev);
1290 if (!dev_priv->gart_info.mapping.handle) {
1291 DRM_ERROR("ioremap failed.\n");
1292 radeon_do_cleanup_cp(dev);
1293 return -EINVAL;
1294 }
1295
1296 dev_priv->gart_info.addr =
1297 dev_priv->gart_info.mapping.handle;
1298
1299 if (dev_priv->flags & RADEON_IS_PCIE)
1300 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCIE;
1301 else
1302 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
1303 dev_priv->gart_info.gart_table_location =
1304 DRM_ATI_GART_FB;
1305
1306 DRM_DEBUG("Setting phys_pci_gart to %p %08lX\n",
1307 dev_priv->gart_info.addr,
1308 dev_priv->pcigart_offset);
1309
1310 } else {
1311 if (dev_priv->flags & RADEON_IS_IGPGART)
1312 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_IGP;
1313 else
1314 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
1315 dev_priv->gart_info.gart_table_location =
1316 DRM_ATI_GART_MAIN;
1317 dev_priv->gart_info.addr = NULL;
1318 dev_priv->gart_info.bus_addr = 0;
1319 if (dev_priv->flags & RADEON_IS_PCIE) {
1320 DRM_ERROR
1321 ("Cannot use PCI Express without GART in FB memory\n");
1322 radeon_do_cleanup_cp(dev);
1323 return -EINVAL;
1324 }
1325 }
1326
1327 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
1328 ret = r600_page_table_init(dev);
1329 else
1330 ret = drm_ati_pcigart_init(dev, &dev_priv->gart_info);
1331
1332 if (!ret) {
1333 DRM_ERROR("failed to init PCI GART!\n");
1334 radeon_do_cleanup_cp(dev);
1335 return -ENOMEM;
1336 }
1337
1338 /* Turn on PCI GART */
1339 radeon_set_pcigart(dev_priv, 1);
1340 }
1341
1342 /* Start with assuming that writeback doesn't work */
1343 dev_priv->writeback_works = 0;
1344
1345 radeon_cp_load_microcode(dev_priv);
1346 radeon_cp_init_ring_buffer(dev, dev_priv);
1347
1348 dev_priv->last_buf = 0;
1349
1350 radeon_do_engine_reset(dev);
1351 radeon_test_writeback(dev_priv);
1352
1353 return 0;
1354 }
1355
1356 static int radeon_do_cleanup_cp(struct drm_device * dev)
1357 {
1358 drm_radeon_private_t *dev_priv = dev->dev_private;
1359 DRM_DEBUG("\n");
1360
1361 /* Make sure interrupts are disabled here because the uninstall ioctl
1362 * may not have been called from userspace and after dev_private
1363 * is freed, it's too late.
1364 */
1365 if (dev->irq_enabled)
1366 drm_irq_uninstall(dev);
1367
1368 #if __OS_HAS_AGP
1369 if (dev_priv->flags & RADEON_IS_AGP) {
1370 if (dev_priv->cp_ring != NULL) {
1371 drm_core_ioremapfree(dev_priv->cp_ring, dev);
1372 dev_priv->cp_ring = NULL;
1373 }
1374 if (dev_priv->ring_rptr != NULL) {
1375 drm_core_ioremapfree(dev_priv->ring_rptr, dev);
1376 dev_priv->ring_rptr = NULL;
1377 }
1378 if (dev->agp_buffer_map != NULL) {
1379 drm_core_ioremapfree(dev->agp_buffer_map, dev);
1380 dev->agp_buffer_map = NULL;
1381 }
1382 } else
1383 #endif
1384 {
1385
1386 if (dev_priv->gart_info.bus_addr) {
1387 /* Turn off PCI GART */
1388 radeon_set_pcigart(dev_priv, 0);
1389
1390 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
1391 r600_page_table_cleanup(dev, &dev_priv->gart_info);
1392 else {
1393 if (!drm_ati_pcigart_cleanup(dev, &dev_priv->gart_info))
1394 DRM_ERROR("failed to cleanup PCI GART!\n");
1395 }
1396 }
1397
1398 if (dev_priv->gart_info.gart_table_location == DRM_ATI_GART_FB)
1399 {
1400 drm_core_ioremapfree(&dev_priv->gart_info.mapping, dev);
1401 dev_priv->gart_info.addr = 0;
1402 }
1403 }
1404
1405 if (dev_priv->mmio)
1406 drm_rmmap(dev, dev_priv->mmio);
1407 if (dev_priv->fb_map)
1408 drm_rmmap(dev, dev_priv->fb_map);
1409
1410 /* only clear to the start of flags */
1411 memset(dev_priv, 0, offsetof(drm_radeon_private_t, flags));
1412
1413 return 0;
1414 }
1415
1416 /* This code will reinit the Radeon CP hardware after a resume from disc.
1417 * AFAIK, it would be very difficult to pickle the state at suspend time, so
1418 * here we make sure that all Radeon hardware initialisation is re-done without
1419 * affecting running applications.
1420 *
1421 * Charl P. Botha <http://cpbotha.net>
1422 */
1423 static int radeon_do_resume_cp(struct drm_device * dev)
1424 {
1425 drm_radeon_private_t *dev_priv = dev->dev_private;
1426
1427 if (!dev_priv) {
1428 DRM_ERROR("Called with no initialization\n");
1429 return -EINVAL;
1430 }
1431
1432 DRM_DEBUG("Starting radeon_do_resume_cp()\n");
1433
1434 #if __OS_HAS_AGP
1435 if (dev_priv->flags & RADEON_IS_AGP) {
1436 /* Turn off PCI GART */
1437 radeon_set_pcigart(dev_priv, 0);
1438 } else
1439 #endif
1440 {
1441 /* Turn on PCI GART */
1442 radeon_set_pcigart(dev_priv, 1);
1443 }
1444
1445 radeon_cp_load_microcode(dev_priv);
1446 radeon_cp_init_ring_buffer(dev, dev_priv);
1447
1448 radeon_do_engine_reset(dev);
1449 radeon_irq_set_state(dev, RADEON_SW_INT_ENABLE, 1);
1450
1451 DRM_DEBUG("radeon_do_resume_cp() complete\n");
1452
1453 return 0;
1454 }
1455
1456 int radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_priv)
1457 {
1458 drm_radeon_private_t *dev_priv = dev->dev_private;
1459 drm_radeon_init_t *init = data;
1460
1461 LOCK_TEST_WITH_RETURN(dev, file_priv);
1462
1463 if (init->func == RADEON_INIT_R300_CP)
1464 r300_init_reg_flags(dev);
1465
1466 switch (init->func) {
1467 case RADEON_INIT_CP:
1468 case RADEON_INIT_R200_CP:
1469 case RADEON_INIT_R300_CP:
1470 return radeon_do_init_cp(dev, init);
1471 case RADEON_INIT_R600_CP:
1472 return r600_do_init_cp(dev, init);
1473 case RADEON_CLEANUP_CP:
1474 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1475 return r600_do_cleanup_cp(dev);
1476 else
1477 return radeon_do_cleanup_cp(dev);
1478 }
1479
1480 return -EINVAL;
1481 }
1482
1483 int radeon_cp_start(struct drm_device *dev, void *data, struct drm_file *file_priv)
1484 {
1485 drm_radeon_private_t *dev_priv = dev->dev_private;
1486 DRM_DEBUG("\n");
1487
1488 LOCK_TEST_WITH_RETURN(dev, file_priv);
1489
1490 if (dev_priv->cp_running) {
1491 DRM_DEBUG("while CP running\n");
1492 return 0;
1493 }
1494 if (dev_priv->cp_mode == RADEON_CSQ_PRIDIS_INDDIS) {
1495 DRM_DEBUG("called with bogus CP mode (%d)\n",
1496 dev_priv->cp_mode);
1497 return 0;
1498 }
1499
1500 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1501 r600_do_cp_start(dev_priv);
1502 else
1503 radeon_do_cp_start(dev_priv);
1504
1505 return 0;
1506 }
1507
1508 /* Stop the CP. The engine must have been idled before calling this
1509 * routine.
1510 */
1511 int radeon_cp_stop(struct drm_device *dev, void *data, struct drm_file *file_priv)
1512 {
1513 drm_radeon_private_t *dev_priv = dev->dev_private;
1514 drm_radeon_cp_stop_t *stop = data;
1515 int ret;
1516 DRM_DEBUG("\n");
1517
1518 LOCK_TEST_WITH_RETURN(dev, file_priv);
1519
1520 if (!dev_priv->cp_running)
1521 return 0;
1522
1523 /* Flush any pending CP commands. This ensures any outstanding
1524 * commands are exectuted by the engine before we turn it off.
1525 */
1526 if (stop->flush) {
1527 radeon_do_cp_flush(dev_priv);
1528 }
1529
1530 /* If we fail to make the engine go idle, we return an error
1531 * code so that the DRM ioctl wrapper can try again.
1532 */
1533 if (stop->idle) {
1534 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1535 ret = r600_do_cp_idle(dev_priv);
1536 else
1537 ret = radeon_do_cp_idle(dev_priv);
1538 if (ret)
1539 return ret;
1540 }
1541
1542 /* Finally, we can turn off the CP. If the engine isn't idle,
1543 * we will get some dropped triangles as they won't be fully
1544 * rendered before the CP is shut down.
1545 */
1546 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1547 r600_do_cp_stop(dev_priv);
1548 else
1549 radeon_do_cp_stop(dev_priv);
1550
1551 /* Reset the engine */
1552 if ((dev_priv->flags & RADEON_FAMILY_MASK) < CHIP_R600)
1553 radeon_do_engine_reset(dev);
1554 else
1555 r600_do_engine_reset(dev);
1556
1557 return 0;
1558 }
1559
1560 void radeon_do_release(struct drm_device * dev)
1561 {
1562 drm_radeon_private_t *dev_priv = dev->dev_private;
1563 int i, ret;
1564
1565 if (dev_priv) {
1566 if (dev_priv->cp_running) {
1567 /* Stop the cp */
1568 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) {
1569 while ((ret = r600_do_cp_idle(dev_priv)) != 0) {
1570 DRM_DEBUG("r600_do_cp_idle %d\n", ret);
1571 #ifdef __linux__
1572 schedule();
1573 #else
1574 #if defined(__FreeBSD__) && __FreeBSD_version > 500000
1575 mtx_sleep(&ret, &dev->dev_lock, PZERO, "rdnrel",
1576 1);
1577 #elif defined(__NetBSD__)
1578 mtsleep(&ret, 0, "rdnrel", 1,
1579 &dev->dev_lock);
1580 #else
1581 tsleep(&ret, PZERO, "rdnrel", 1);
1582 #endif
1583 #endif
1584 }
1585 r600_do_cp_stop(dev_priv);
1586 r600_do_engine_reset(dev);
1587 } else {
1588 while ((ret = radeon_do_cp_idle(dev_priv)) != 0) {
1589 DRM_DEBUG("radeon_do_cp_idle %d\n", ret);
1590 #ifdef __linux__
1591 schedule();
1592 #else
1593 #if defined(__FreeBSD__) && __FreeBSD_version > 500000
1594 mtx_sleep(&ret, &dev->dev_lock, PZERO, "rdnrel",
1595 1);
1596 #elif defined(__NetBSD__)
1597 mtsleep(&ret, 0, "rdnrel", 1,
1598 &dev->dev_lock);
1599 #else
1600 tsleep(&ret, PZERO, "rdnrel", 1);
1601 #endif
1602 #endif
1603 }
1604 radeon_do_cp_stop(dev_priv);
1605 radeon_do_engine_reset(dev);
1606 }
1607 }
1608
1609 if ((dev_priv->flags & RADEON_FAMILY_MASK) < CHIP_R600) {
1610 /* Disable *all* interrupts */
1611 if (dev_priv->mmio) /* remove this after permanent addmaps */
1612 RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
1613
1614 if (dev_priv->mmio) { /* remove all surfaces */
1615 for (i = 0; i < RADEON_MAX_SURFACES; i++) {
1616 RADEON_WRITE(RADEON_SURFACE0_INFO + 16 * i, 0);
1617 RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND +
1618 16 * i, 0);
1619 RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND +
1620 16 * i, 0);
1621 }
1622 }
1623 }
1624
1625 /* Free memory heap structures */
1626 radeon_mem_takedown(&(dev_priv->gart_heap));
1627 radeon_mem_takedown(&(dev_priv->fb_heap));
1628
1629 /* deallocate kernel resources */
1630 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1631 r600_do_cleanup_cp(dev);
1632 else
1633 radeon_do_cleanup_cp(dev);
1634 }
1635 }
1636
1637 /* Just reset the CP ring. Called as part of an X Server engine reset.
1638 */
1639 int radeon_cp_reset(struct drm_device *dev, void *data, struct drm_file *file_priv)
1640 {
1641 drm_radeon_private_t *dev_priv = dev->dev_private;
1642 DRM_DEBUG("\n");
1643
1644 LOCK_TEST_WITH_RETURN(dev, file_priv);
1645
1646 if (!dev_priv) {
1647 DRM_DEBUG("called before init done\n");
1648 return -EINVAL;
1649 }
1650
1651 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1652 r600_do_cp_reset(dev_priv);
1653 else
1654 radeon_do_cp_reset(dev_priv);
1655
1656 /* The CP is no longer running after an engine reset */
1657 dev_priv->cp_running = 0;
1658
1659 return 0;
1660 }
1661
1662 int radeon_cp_idle(struct drm_device *dev, void *data, struct drm_file *file_priv)
1663 {
1664 drm_radeon_private_t *dev_priv = dev->dev_private;
1665 DRM_DEBUG("\n");
1666
1667 LOCK_TEST_WITH_RETURN(dev, file_priv);
1668
1669 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1670 return r600_do_cp_idle(dev_priv);
1671 else
1672 return radeon_do_cp_idle(dev_priv);
1673 }
1674
1675 /* Added by Charl P. Botha to call radeon_do_resume_cp().
1676 */
1677 int radeon_cp_resume(struct drm_device *dev, void *data, struct drm_file *file_priv)
1678 {
1679 drm_radeon_private_t *dev_priv = dev->dev_private;
1680
1681 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1682 return r600_do_resume_cp(dev);
1683 else
1684 return radeon_do_resume_cp(dev);
1685 }
1686
1687 int radeon_engine_reset(struct drm_device *dev, void *data, struct drm_file *file_priv)
1688 {
1689 drm_radeon_private_t *dev_priv = dev->dev_private;
1690 DRM_DEBUG("\n");
1691
1692 LOCK_TEST_WITH_RETURN(dev, file_priv);
1693
1694 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1695 return r600_do_engine_reset(dev);
1696 else
1697 return radeon_do_engine_reset(dev);
1698 }
1699
1700 /* ================================================================
1701 * Fullscreen mode
1702 */
1703
1704 /* KW: Deprecated to say the least:
1705 */
1706 int radeon_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv)
1707 {
1708 return 0;
1709 }
1710
1711 /* ================================================================
1712 * Freelist management
1713 */
1714
1715 /* Original comment: FIXME: ROTATE_BUFS is a hack to cycle through
1716 * bufs until freelist code is used. Note this hides a problem with
1717 * the scratch register * (used to keep track of last buffer
1718 * completed) being written to before * the last buffer has actually
1719 * completed rendering.
1720 *
1721 * KW: It's also a good way to find free buffers quickly.
1722 *
1723 * KW: Ideally this loop wouldn't exist, and freelist_get wouldn't
1724 * sleep. However, bugs in older versions of radeon_accel.c mean that
1725 * we essentially have to do this, else old clients will break.
1726 *
1727 * However, it does leave open a potential deadlock where all the
1728 * buffers are held by other clients, which can't release them because
1729 * they can't get the lock.
1730 */
1731
1732 struct drm_buf *radeon_freelist_get(struct drm_device * dev)
1733 {
1734 struct drm_device_dma *dma = dev->dma;
1735 drm_radeon_private_t *dev_priv = dev->dev_private;
1736 drm_radeon_buf_priv_t *buf_priv;
1737 struct drm_buf *buf;
1738 int i, t;
1739 int start;
1740
1741 if (++dev_priv->last_buf >= dma->buf_count)
1742 dev_priv->last_buf = 0;
1743
1744 start = dev_priv->last_buf;
1745
1746 for (t = 0; t < dev_priv->usec_timeout; t++) {
1747 u32 done_age;
1748 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1749 done_age = GET_R600_SCRATCH(1);
1750 else
1751 done_age = GET_SCRATCH(1);
1752 DRM_DEBUG("done_age = %d\n", done_age);
1753 for (i = start; i < dma->buf_count; i++) {
1754 buf = dma->buflist[i];
1755 buf_priv = buf->dev_private;
1756 if (buf->file_priv == NULL || (buf->pending &&
1757 buf_priv->age <=
1758 done_age)) {
1759 dev_priv->stats.requested_bufs++;
1760 buf->pending = 0;
1761 return buf;
1762 }
1763 start = 0;
1764 }
1765
1766 if (t) {
1767 DRM_UDELAY(1);
1768 dev_priv->stats.freelist_loops++;
1769 }
1770 }
1771
1772 DRM_DEBUG("returning NULL!\n");
1773 return NULL;
1774 }
1775
1776 #if 0
1777 struct drm_buf *radeon_freelist_get(struct drm_device * dev)
1778 {
1779 struct drm_device_dma *dma = dev->dma;
1780 drm_radeon_private_t *dev_priv = dev->dev_private;
1781 drm_radeon_buf_priv_t *buf_priv;
1782 struct drm_buf *buf;
1783 int i, t;
1784 int start;
1785 u32 done_age = DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1));
1786
1787 if (++dev_priv->last_buf >= dma->buf_count)
1788 dev_priv->last_buf = 0;
1789
1790 start = dev_priv->last_buf;
1791 dev_priv->stats.freelist_loops++;
1792
1793 for (t = 0; t < 2; t++) {
1794 for (i = start; i < dma->buf_count; i++) {
1795 buf = dma->buflist[i];
1796 buf_priv = buf->dev_private;
1797 if (buf->file_priv == 0 || (buf->pending &&
1798 buf_priv->age <=
1799 done_age)) {
1800 dev_priv->stats.requested_bufs++;
1801 buf->pending = 0;
1802 return buf;
1803 }
1804 }
1805 start = 0;
1806 }
1807
1808 return NULL;
1809 }
1810 #endif
1811
1812 void radeon_freelist_reset(struct drm_device * dev)
1813 {
1814 struct drm_device_dma *dma = dev->dma;
1815 drm_radeon_private_t *dev_priv = dev->dev_private;
1816 int i;
1817
1818 dev_priv->last_buf = 0;
1819 for (i = 0; i < dma->buf_count; i++) {
1820 struct drm_buf *buf = dma->buflist[i];
1821 drm_radeon_buf_priv_t *buf_priv = buf->dev_private;
1822 buf_priv->age = 0;
1823 }
1824 }
1825
1826 /* ================================================================
1827 * CP command submission
1828 */
1829
1830 int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n)
1831 {
1832 drm_radeon_ring_buffer_t *ring = &dev_priv->ring;
1833 int i;
1834 u32 last_head;
1835
1836 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1837 last_head = R600_GET_RING_HEAD(dev_priv);
1838 else
1839 last_head = GET_RING_HEAD(dev_priv);
1840
1841 for (i = 0; i < dev_priv->usec_timeout; i++) {
1842 u32 head;
1843
1844 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1845 head = R600_GET_RING_HEAD(dev_priv);
1846 else
1847 head = GET_RING_HEAD(dev_priv);
1848
1849 ring->space = (head - ring->tail) * sizeof(u32);
1850 if (ring->space <= 0)
1851 ring->space += ring->size;
1852 if (ring->space > n)
1853 return 0;
1854
1855 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
1856
1857 if (head != last_head)
1858 i = 0;
1859 last_head = head;
1860
1861 DRM_UDELAY(1);
1862 }
1863
1864 /* FIXME: This return value is ignored in the BEGIN_RING macro! */
1865 #if RADEON_FIFO_DEBUG
1866 radeon_status(dev_priv);
1867 DRM_ERROR("failed!\n");
1868 #endif
1869 return -EBUSY;
1870 }
1871
1872 static int radeon_cp_get_buffers(struct drm_device *dev,
1873 struct drm_file *file_priv,
1874 struct drm_dma * d)
1875 {
1876 int i;
1877 struct drm_buf *buf;
1878
1879 for (i = d->granted_count; i < d->request_count; i++) {
1880 buf = radeon_freelist_get(dev);
1881 if (!buf)
1882 return -EBUSY; /* NOTE: broken client */
1883
1884 buf->file_priv = file_priv;
1885
1886 if (DRM_COPY_TO_USER(&d->request_indices[i], &buf->idx,
1887 sizeof(buf->idx)))
1888 return -EFAULT;
1889 if (DRM_COPY_TO_USER(&d->request_sizes[i], &buf->total,
1890 sizeof(buf->total)))
1891 return -EFAULT;
1892
1893 d->granted_count++;
1894 }
1895 return 0;
1896 }
1897
1898 int radeon_cp_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv)
1899 {
1900 struct drm_device_dma *dma = dev->dma;
1901 int ret = 0;
1902 struct drm_dma *d = data;
1903
1904 LOCK_TEST_WITH_RETURN(dev, file_priv);
1905
1906 /* Please don't send us buffers.
1907 */
1908 if (d->send_count != 0) {
1909 DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n",
1910 DRM_CURRENTPID, d->send_count);
1911 return -EINVAL;
1912 }
1913
1914 /* We'll send you buffers.
1915 */
1916 if (d->request_count < 0 || d->request_count > dma->buf_count) {
1917 DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n",
1918 DRM_CURRENTPID, d->request_count, dma->buf_count);
1919 return -EINVAL;
1920 }
1921
1922 d->granted_count = 0;
1923
1924 if (d->request_count) {
1925 ret = radeon_cp_get_buffers(dev, file_priv, d);
1926 }
1927
1928 return ret;
1929 }
1930
1931 void radeon_commit_ring(drm_radeon_private_t *dev_priv)
1932 {
1933 int i;
1934 u32 *ring;
1935 int tail_aligned;
1936
1937 /* check if the ring is padded out to 16-dword alignment */
1938
1939 tail_aligned = dev_priv->ring.tail & 0xf;
1940 if (tail_aligned) {
1941 int num_p2 = 16 - tail_aligned;
1942
1943 ring = dev_priv->ring.start;
1944 /* pad with some CP_PACKET2 */
1945 for (i = 0; i < num_p2; i++)
1946 ring[dev_priv->ring.tail + i] = CP_PACKET2();
1947
1948 dev_priv->ring.tail += i;
1949
1950 dev_priv->ring.space -= num_p2 * sizeof(u32);
1951 }
1952
1953 dev_priv->ring.tail &= dev_priv->ring.tail_mask;
1954
1955 DRM_MEMORYBARRIER();
1956 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1957 R600_GET_RING_HEAD( dev_priv );
1958 else
1959 GET_RING_HEAD( dev_priv );
1960
1961 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) {
1962 RADEON_WRITE(R600_CP_RB_WPTR, dev_priv->ring.tail);
1963 /* read from PCI bus to ensure correct posting */
1964 RADEON_READ(R600_CP_RB_RPTR);
1965 } else {
1966 RADEON_WRITE(RADEON_CP_RB_WPTR, dev_priv->ring.tail);
1967 /* read from PCI bus to ensure correct posting */
1968 RADEON_READ(RADEON_CP_RB_RPTR);
1969 }
1970 }
1971
1972 int radeon_driver_load(struct drm_device *dev, unsigned long flags)
1973 {
1974 drm_radeon_private_t *dev_priv;
1975 int ret = 0;
1976
1977 dev_priv = drm_alloc(sizeof(drm_radeon_private_t), DRM_MEM_DRIVER);
1978 if (dev_priv == NULL)
1979 return -ENOMEM;
1980
1981 memset(dev_priv, 0, sizeof(drm_radeon_private_t));
1982 dev->dev_private = (void *)dev_priv;
1983 dev_priv->flags = flags;
1984
1985 switch (flags & RADEON_FAMILY_MASK) {
1986 case CHIP_R100:
1987 case CHIP_RV200:
1988 case CHIP_R200:
1989 case CHIP_R300:
1990 case CHIP_R350:
1991 case CHIP_R420:
1992 case CHIP_R423:
1993 case CHIP_RV410:
1994 case CHIP_RV515:
1995 case CHIP_R520:
1996 case CHIP_RV570:
1997 case CHIP_R580:
1998 dev_priv->flags |= RADEON_HAS_HIERZ;
1999 break;
2000 default:
2001 /* all other chips have no hierarchical z buffer */
2002 break;
2003 }
2004
2005 dev_priv->chip_family = flags & RADEON_FAMILY_MASK;
2006 if (drm_device_is_agp(dev))
2007 dev_priv->flags |= RADEON_IS_AGP;
2008 else if (drm_device_is_pcie(dev))
2009 dev_priv->flags |= RADEON_IS_PCIE;
2010 else
2011 dev_priv->flags |= RADEON_IS_PCI;
2012
2013 ret = drm_vblank_init(dev, 2);
2014 if (ret) {
2015 radeon_driver_unload(dev);
2016 return ret;
2017 }
2018
2019 DRM_DEBUG("%s card detected\n",
2020 ((dev_priv->flags & RADEON_IS_AGP) ? "AGP" : (((dev_priv->flags & RADEON_IS_PCIE) ? "PCIE" : "PCI"))));
2021 return ret;
2022 }
2023
2024 /* Create mappings for registers and framebuffer so userland doesn't necessarily
2025 * have to find them.
2026 */
2027 int radeon_driver_firstopen(struct drm_device *dev)
2028 {
2029 int ret;
2030 drm_radeon_private_t *dev_priv = dev->dev_private;
2031
2032 dev_priv->gart_info.table_size = RADEON_PCIGART_TABLE_SIZE;
2033
2034 ret = drm_addmap(dev, drm_get_resource_start(dev, 2),
2035 drm_get_resource_len(dev, 2), _DRM_REGISTERS,
2036 _DRM_READ_ONLY, &dev_priv->mmio);
2037 if (ret != 0)
2038 return ret;
2039
2040 dev_priv->fb_aper_offset = drm_get_resource_start(dev, 0);
2041 ret = drm_addmap(dev, dev_priv->fb_aper_offset,
2042 drm_get_resource_len(dev, 0), _DRM_FRAME_BUFFER,
2043 _DRM_WRITE_COMBINING, &dev_priv->fb_map);
2044 if (ret != 0)
2045 return ret;
2046
2047 return 0;
2048 }
2049
2050 int radeon_driver_unload(struct drm_device *dev)
2051 {
2052 drm_radeon_private_t *dev_priv = dev->dev_private;
2053
2054 DRM_DEBUG("\n");
2055 drm_free(dev_priv, sizeof(*dev_priv), DRM_MEM_DRIVER);
2056
2057 dev->dev_private = NULL;
2058 return 0;
2059 }
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