sys/external/bsd/drm/dist/shared-core/via_drv.h

   1 /*
   2  * Copyright 1998-2003 VIA Technologies, Inc. All Rights Reserved.
   3  * Copyright 2001-2003 S3 Graphics, Inc. All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sub license,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the
  13  * next paragraph) shall be included in all copies or substantial portions
  14  * of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  19  * VIA, S3 GRAPHICS, AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  */
  24 #ifndef _VIA_DRV_H_
  25 #define _VIA_DRV_H_
  26
  27 #ifdef VIA_HAVE_CORE_MM
  28 #include "drm_sman.h"
  29 #endif
  30 #define DRIVER_AUTHOR   "Various"
  31
  32 #define DRIVER_NAME             "via"
  33 #define DRIVER_DESC             "VIA Unichrome / Pro"
  34
  35 #include "via_verifier.h"
  36
  37 /*
  38  * Registers go here.
  39  */
  40
  41
  42 #define CMDBUF_ALIGNMENT_SIZE   (0x100)
  43 #define CMDBUF_ALIGNMENT_MASK   (0x0ff)
  44
  45 /* defines for VIA 3D registers */
  46 #define VIA_REG_STATUS          0x400
  47 #define VIA_REG_TRANSET         0x43C
  48 #define VIA_REG_TRANSPACE       0x440
  49
  50 /* VIA_REG_STATUS(0x400): Engine Status */
  51 #define VIA_CMD_RGTR_BUSY       0x00000080      /* Command Regulator is busy */
  52 #define VIA_2D_ENG_BUSY         0x00000001      /* 2D Engine is busy */
  53 #define VIA_3D_ENG_BUSY         0x00000002      /* 3D Engine is busy */
  54 #define VIA_VR_QUEUE_BUSY       0x00020000      /* Virtual Queue is busy */
  55
  56 #if defined(__NetBSD__)
  57 /*
  58  *  PCI DMA Registers
  59  *  Channels 2 & 3 don't seem to be implemented in hardware.
  60  */
  61
  62 #define VIA_PCI_DMA_MAR0            0xE40   /* Memory Address Register of Channel 0 */
  63 #define VIA_PCI_DMA_DAR0            0xE44   /* Device Address Register of Channel 0 */
  64 #define VIA_PCI_DMA_BCR0            0xE48   /* Byte Count Register of Channel 0 */
  65 #define VIA_PCI_DMA_DPR0            0xE4C   /* Descriptor Pointer Register of Channel 0 */
  66
  67 #define VIA_PCI_DMA_MAR1            0xE50   /* Memory Address Register of Channel 1 */
  68 #define VIA_PCI_DMA_DAR1            0xE54   /* Device Address Register of Channel 1 */
  69 #define VIA_PCI_DMA_BCR1            0xE58   /* Byte Count Register of Channel 1 */
  70 #define VIA_PCI_DMA_DPR1            0xE5C   /* Descriptor Pointer Register of Channel 1 */
  71
  72 #define VIA_PCI_DMA_MAR2            0xE60   /* Memory Address Register of Channel 2 */
  73 #define VIA_PCI_DMA_DAR2            0xE64   /* Device Address Register of Channel 2 */
  74 #define VIA_PCI_DMA_BCR2            0xE68   /* Byte Count Register of Channel 2 */
  75 #define VIA_PCI_DMA_DPR2            0xE6C   /* Descriptor Pointer Register of Channel 2 */
  76
  77 #define VIA_PCI_DMA_MAR3            0xE70   /* Memory Address Register of Channel 3 */
  78 #define VIA_PCI_DMA_DAR3            0xE74   /* Device Address Register of Channel 3 */
  79 #define VIA_PCI_DMA_BCR3            0xE78   /* Byte Count Register of Channel 3 */
  80 #define VIA_PCI_DMA_DPR3            0xE7C   /* Descriptor Pointer Register of Channel 3 */
  81
  82 #define VIA_PCI_DMA_MR0             0xE80   /* Mode Register of Channel 0 */
  83 #define VIA_PCI_DMA_MR1             0xE84   /* Mode Register of Channel 1 */
  84 #define VIA_PCI_DMA_MR2             0xE88   /* Mode Register of Channel 2 */
  85 #define VIA_PCI_DMA_MR3             0xE8C   /* Mode Register of Channel 3 */
  86
  87 #define VIA_PCI_DMA_CSR0            0xE90   /* Command/Status Register of Channel 0 */
  88 #define VIA_PCI_DMA_CSR1            0xE94   /* Command/Status Register of Channel 1 */
  89 #define VIA_PCI_DMA_CSR2            0xE98   /* Command/Status Register of Channel 2 */
  90 #define VIA_PCI_DMA_CSR3            0xE9C   /* Command/Status Register of Channel 3 */
  91
  92 #define VIA_PCI_DMA_PTR             0xEA0   /* Priority Type Register */
  93
  94 /* Define for DMA engine */
  95 /* DPR */
  96 #define VIA_DMA_DPR_EC          (1<<1)  /* end of chain */
  97 #define VIA_DMA_DPR_DDIE        (1<<2)  /* descriptor done interrupt enable */
  98 #define VIA_DMA_DPR_DT          (1<<3)  /* direction of transfer (RO) */
  99
 100 /* MR */
 101 #define VIA_DMA_MR_CM           (1<<0)  /* chaining mode */
 102 #define VIA_DMA_MR_TDIE         (1<<1)  /* transfer done interrupt enable */
 103 #define VIA_DMA_MR_HENDMACMD            (1<<7) /* ? */
 104
 105 /* CSR */
 106 #define VIA_DMA_CSR_DE          (1<<0)  /* DMA enable */
 107 #define VIA_DMA_CSR_TS          (1<<1)  /* transfer start */
 108 #define VIA_DMA_CSR_TA          (1<<2)  /* transfer abort */
 109 #define VIA_DMA_CSR_TD          (1<<3)  /* transfer done */
 110 #define VIA_DMA_CSR_DD          (1<<4)  /* descriptor done */
 111 #define VIA_DMA_DPR_EC          (1<<1)  /* end of chain */
 112 #endif
 113
 114 #if defined(__linux__)
 115 #include "via_dmablit.h"
 116
 117 /*
 118  * This define and all its references can be removed when
 119  * the DMA blit code has been implemented for FreeBSD.
 120  */
 121 #define VIA_HAVE_DMABLIT 1
 122 #define VIA_HAVE_CORE_MM 1
 123 #define VIA_HAVE_FENCE   1
 124 #define VIA_HAVE_BUFFER  1
 125 #endif
 126
 127 #define VIA_PCI_BUF_SIZE 60000
 128 #define VIA_FIRE_BUF_SIZE  1024
 129 #define VIA_NUM_IRQS 4
 130
 131 typedef struct drm_via_ring_buffer {
 132         drm_local_map_t map;
 133         char *virtual_start;
 134 } drm_via_ring_buffer_t;
 135
 136 typedef uint32_t maskarray_t[5];
 137
 138 typedef struct drm_via_irq {
 139         atomic_t irq_received;
 140         uint32_t pending_mask;
 141         uint32_t enable_mask;
 142         wait_queue_head_t irq_queue;
 143 } drm_via_irq_t;
 144
 145 typedef struct drm_via_private {
 146         drm_via_sarea_t *sarea_priv;
 147         drm_local_map_t *sarea;
 148         drm_local_map_t *fb;
 149         drm_local_map_t *mmio;
 150         unsigned long agpAddr;
 151         wait_queue_head_t decoder_queue[VIA_NR_XVMC_LOCKS];
 152         char *dma_ptr;
 153         unsigned int dma_low;
 154         unsigned int dma_high;
 155         unsigned int dma_offset;
 156         uint32_t dma_wrap;
 157         volatile uint32_t *last_pause_ptr;
 158         volatile uint32_t *hw_addr_ptr;
 159         drm_via_ring_buffer_t ring;
 160         struct timeval last_vblank;
 161         int last_vblank_valid;
 162         unsigned usec_per_vblank;
 163         atomic_t vbl_received;
 164         drm_via_state_t hc_state;
 165         char pci_buf[VIA_PCI_BUF_SIZE];
 166         const uint32_t *fire_offsets[VIA_FIRE_BUF_SIZE];
 167         uint32_t num_fire_offsets;
 168         int chipset;
 169         drm_via_irq_t via_irqs[VIA_NUM_IRQS];
 170         unsigned num_irqs;
 171         maskarray_t *irq_masks;
 172         uint32_t irq_enable_mask;
 173         uint32_t irq_pending_mask;
 174         int *irq_map;
 175         /* Memory manager stuff */
 176 #ifdef VIA_HAVE_CORE_MM
 177         unsigned int idle_fault;
 178         struct drm_sman sman;
 179         int vram_initialized;
 180         int agp_initialized;
 181         unsigned long vram_offset;
 182         unsigned long agp_offset;
 183 #endif
 184 #ifdef VIA_HAVE_DMABLIT
 185         drm_via_blitq_t blit_queues[VIA_NUM_BLIT_ENGINES];
 186 #endif
 187         uint32_t dma_diff;
 188 #ifdef VIA_HAVE_FENCE
 189         spinlock_t fence_lock;
 190         uint32_t emit_0_sequence;
 191         int have_idlelock;
 192         struct timer_list fence_timer;
 193 #endif
 194 } drm_via_private_t;
 195
 196 enum via_family {
 197   VIA_OTHER = 0,     /* Baseline */
 198   VIA_PRO_GROUP_A,   /* Another video engine and DMA commands */
 199   VIA_DX9_0          /* Same video as pro_group_a, but 3D is unsupported */
 200 };
 201
 202 /* VIA MMIO register access */
 203 #define VIA_BASE ((dev_priv->mmio))
 204
 205 #define VIA_READ(reg)           DRM_READ32(VIA_BASE, reg)
 206 #define VIA_WRITE(reg,val)      DRM_WRITE32(VIA_BASE, reg, val)
 207 #define VIA_READ8(reg)          DRM_READ8(VIA_BASE, reg)
 208 #define VIA_WRITE8(reg,val)     DRM_WRITE8(VIA_BASE, reg, val)
 209
 210 extern struct drm_ioctl_desc via_ioctls[];
 211 extern int via_max_ioctl;
 212
 213 extern int via_fb_init(struct drm_device *dev, void *data, struct drm_file *file_priv);
 214 extern int via_mem_alloc(struct drm_device *dev, void *data, struct drm_file *file_priv);
 215 extern int via_mem_free(struct drm_device *dev, void *data, struct drm_file *file_priv);
 216 extern int via_agp_init(struct drm_device *dev, void *data, struct drm_file *file_priv);
 217 extern int via_map_init(struct drm_device *dev, void *data, struct drm_file *file_priv);
 218 extern int via_decoder_futex(struct drm_device *dev, void *data, struct drm_file *file_priv);
 219 extern int via_wait_irq(struct drm_device *dev, void *data, struct drm_file *file_priv);
 220 extern int via_dma_blit_sync( struct drm_device *dev, void *data, struct drm_file *file_priv );
 221 extern int via_dma_blit( struct drm_device *dev, void *data, struct drm_file *file_priv );
 222
 223 extern int via_driver_load(struct drm_device *dev, unsigned long chipset);
 224 extern int via_driver_unload(struct drm_device *dev);
 225 extern int via_final_context(struct drm_device * dev, int context);
 226
 227 extern int via_do_cleanup_map(struct drm_device * dev);
 228 extern u32 via_get_vblank_counter(struct drm_device *dev, int crtc);
 229 extern int via_enable_vblank(struct drm_device *dev, int crtc);
 230 extern void via_disable_vblank(struct drm_device *dev, int crtc);
 231
 232 extern irqreturn_t via_driver_irq_handler(DRM_IRQ_ARGS);
 233 extern void via_driver_irq_preinstall(struct drm_device * dev);
 234 extern int via_driver_irq_postinstall(struct drm_device * dev);
 235 extern void via_driver_irq_uninstall(struct drm_device * dev);
 236
 237 extern int via_dma_cleanup(struct drm_device * dev);
 238 extern void via_init_command_verifier(void);
 239 extern int via_driver_dma_quiescent(struct drm_device * dev);
 240 extern void via_init_futex(drm_via_private_t *dev_priv);
 241 extern void via_cleanup_futex(drm_via_private_t *dev_priv);
 242 extern void via_release_futex(drm_via_private_t *dev_priv, int context);
 243
 244 #ifdef VIA_HAVE_CORE_MM
 245 extern void via_reclaim_buffers_locked(struct drm_device *dev,
 246                                        struct drm_file *file_priv);
 247 extern void via_lastclose(struct drm_device *dev);
 248 #else
 249 extern int via_init_context(struct drm_device * dev, int context);
 250 #endif
 251
 252 #ifdef VIA_HAVE_DMABLIT
 253 extern void via_dmablit_handler(struct drm_device *dev, int engine, int from_irq);
 254 extern void via_init_dmablit(struct drm_device *dev);
 255 #endif
 256
 257 #ifdef VIA_HAVE_BUFFER
 258 extern struct drm_ttm_backend *via_create_ttm_backend_entry(struct drm_device *dev);
 259 extern int via_fence_types(struct drm_buffer_object *bo, uint32_t *fclass,
 260                            uint32_t *type);
 261 extern int via_invalidate_caches(struct drm_device *dev, uint64_t buffer_flags);
 262 extern int via_init_mem_type(struct drm_device *dev, uint32_t type,
 263                                struct drm_mem_type_manager *man);
 264 extern uint64_t via_evict_flags(struct drm_buffer_object *bo);
 265 extern int via_move(struct drm_buffer_object *bo, int evict,
 266                 int no_wait, struct drm_bo_mem_reg *new_mem);
 267 #endif
 268
 269 #endif