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[netbsd-mini2440.git] / sys / external / isc / atheros_hal / dist / ah.h
blob96002ed4088a991f57c3fabd58faaaafce6d7945
1 /*
2 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
3 * Copyright (c) 2002-2008 Atheros Communications, Inc.
4 *
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 *
17 * $Id: ah.h,v 1.1.1.1 2008/12/11 04:46:23 alc Exp $
18 */
19
20 #ifndef _ATH_AH_H_
21 #define _ATH_AH_H_
22 /*
23 * Atheros Hardware Access Layer
24 *
25 * Clients of the HAL call ath_hal_attach to obtain a reference to an ath_hal
26 * structure for use with the device. Hardware-related operations that
27 * follow must call back into the HAL through interface, supplying the
28 * reference as the first parameter.
29 */
30
31 #include "ah_osdep.h"
32
33 /*
34 * __ahdecl is analogous to _cdecl; it defines the calling
35 * convention used within the HAL. For most systems this
36 * can just default to be empty and the compiler will (should)
37 * use _cdecl. For systems where _cdecl is not compatible this
38 * must be defined. See linux/ah_osdep.h for an example.
39 */
40 #ifndef __ahdecl
41 #define __ahdecl
42 #endif
43
44 /*
45 * Status codes that may be returned by the HAL. Note that
46 * interfaces that return a status code set it only when an
47 * error occurs--i.e. you cannot check it for success.
48 */
49 typedef enum {
50 HAL_OK = 0, /* No error */
51 HAL_ENXIO = 1, /* No hardware present */
52 HAL_ENOMEM = 2, /* Memory allocation failed */
53 HAL_EIO = 3, /* Hardware didn't respond as expected */
54 HAL_EEMAGIC = 4, /* EEPROM magic number invalid */
55 HAL_EEVERSION = 5, /* EEPROM version invalid */
56 HAL_EELOCKED = 6, /* EEPROM unreadable */
57 HAL_EEBADSUM = 7, /* EEPROM checksum invalid */
58 HAL_EEREAD = 8, /* EEPROM read problem */
59 HAL_EEBADMAC = 9, /* EEPROM mac address invalid */
60 HAL_EESIZE = 10, /* EEPROM size not supported */
61 HAL_EEWRITE = 11, /* Attempt to change write-locked EEPROM */
62 HAL_EINVAL = 12, /* Invalid parameter to function */
63 HAL_ENOTSUPP = 13, /* Hardware revision not supported */
64 HAL_ESELFTEST = 14, /* Hardware self-test failed */
65 HAL_EINPROGRESS = 15, /* Operation incomplete */
66 } HAL_STATUS;
67
68 typedef enum {
69 AH_FALSE = 0, /* NB: lots of code assumes false is zero */
70 AH_TRUE = 1,
71 } HAL_BOOL;
72
73 typedef enum {
74 HAL_CAP_REG_DMN = 0, /* current regulatory domain */
75 HAL_CAP_CIPHER = 1, /* hardware supports cipher */
76 HAL_CAP_TKIP_MIC = 2, /* handle TKIP MIC in hardware */
77 HAL_CAP_TKIP_SPLIT = 3, /* hardware TKIP uses split keys */
78 HAL_CAP_PHYCOUNTERS = 4, /* hardware PHY error counters */
79 HAL_CAP_DIVERSITY = 5, /* hardware supports fast diversity */
80 HAL_CAP_KEYCACHE_SIZE = 6, /* number of entries in key cache */
81 HAL_CAP_NUM_TXQUEUES = 7, /* number of hardware xmit queues */
82 HAL_CAP_VEOL = 9, /* hardware supports virtual EOL */
83 HAL_CAP_PSPOLL = 10, /* hardware has working PS-Poll support */
84 HAL_CAP_DIAG = 11, /* hardware diagnostic support */
85 HAL_CAP_COMPRESSION = 12, /* hardware supports compression */
86 HAL_CAP_BURST = 13, /* hardware supports packet bursting */
87 HAL_CAP_FASTFRAME = 14, /* hardware supoprts fast frames */
88 HAL_CAP_TXPOW = 15, /* global tx power limit */
89 HAL_CAP_TPC = 16, /* per-packet tx power control */
90 HAL_CAP_PHYDIAG = 17, /* hardware phy error diagnostic */
91 HAL_CAP_BSSIDMASK = 18, /* hardware supports bssid mask */
92 HAL_CAP_MCAST_KEYSRCH = 19, /* hardware has multicast key search */
93 HAL_CAP_TSF_ADJUST = 20, /* hardware has beacon tsf adjust */
94 /* 21 was HAL_CAP_XR */
95 HAL_CAP_WME_TKIPMIC = 22, /* hardware can support TKIP MIC when WMM is turned on */
96 /* 23 was HAL_CAP_CHAN_HALFRATE */
97 /* 24 was HAL_CAP_CHAN_QUARTERRATE */
98 HAL_CAP_RFSILENT = 25, /* hardware has rfsilent support */
99 HAL_CAP_TPC_ACK = 26, /* ack txpower with per-packet tpc */
100 HAL_CAP_TPC_CTS = 27, /* cts txpower with per-packet tpc */
101 HAL_CAP_11D = 28, /* 11d beacon support for changing cc */
102 HAL_CAP_INTMIT = 29, /* interference mitigation */
103 HAL_CAP_RXORN_FATAL = 30, /* HAL_INT_RXORN treated as fatal */
104 HAL_CAP_HT = 31, /* hardware can support HT */
105 HAL_CAP_TX_CHAINMASK = 32, /* mask of TX chains supported */
106 HAL_CAP_RX_CHAINMASK = 33, /* mask of RX chains supported */
107 HAL_CAP_RXTSTAMP_PREC = 34, /* rx desc tstamp precision (bits) */
108 HAL_CAP_BB_HANG = 35, /* can baseband hang */
109 HAL_CAP_MAC_HANG = 36, /* can MAC hang */
110 } HAL_CAPABILITY_TYPE;
111
112 /*
113 * "States" for setting the LED. These correspond to
114 * the possible 802.11 operational states and there may
115 * be a many-to-one mapping between these states and the
116 * actual hardware state for the LED's (i.e. the hardware
117 * may have fewer states).
118 */
119 typedef enum {
120 HAL_LED_INIT = 0,
121 HAL_LED_SCAN = 1,
122 HAL_LED_AUTH = 2,
123 HAL_LED_ASSOC = 3,
124 HAL_LED_RUN = 4
125 } HAL_LED_STATE;
126
127 /*
128 * Transmit queue types/numbers. These are used to tag
129 * each transmit queue in the hardware and to identify a set
130 * of transmit queues for operations such as start/stop dma.
131 */
132 typedef enum {
133 HAL_TX_QUEUE_INACTIVE = 0, /* queue is inactive/unused */
134 HAL_TX_QUEUE_DATA = 1, /* data xmit q's */
135 HAL_TX_QUEUE_BEACON = 2, /* beacon xmit q */
136 HAL_TX_QUEUE_CAB = 3, /* "crap after beacon" xmit q */
137 HAL_TX_QUEUE_UAPSD = 4, /* u-apsd power save xmit q */
138 } HAL_TX_QUEUE;
139
140 #define HAL_NUM_TX_QUEUES 10 /* max possible # of queues */
141
142 /*
143 * Transmit queue subtype. These map directly to
144 * WME Access Categories (except for UPSD). Refer
145 * to Table 5 of the WME spec.
146 */
147 typedef enum {
148 HAL_WME_AC_BK = 0, /* background access category */
149 HAL_WME_AC_BE = 1, /* best effort access category*/
150 HAL_WME_AC_VI = 2, /* video access category */
151 HAL_WME_AC_VO = 3, /* voice access category */
152 HAL_WME_UPSD = 4, /* uplink power save */
153 } HAL_TX_QUEUE_SUBTYPE;
154
155 /*
156 * Transmit queue flags that control various
157 * operational parameters.
158 */
159 typedef enum {
160 /*
161 * Per queue interrupt enables. When set the associated
162 * interrupt may be delivered for packets sent through
163 * the queue. Without these enabled no interrupts will
164 * be delivered for transmits through the queue.
165 */
166 HAL_TXQ_TXOKINT_ENABLE = 0x0001, /* enable TXOK interrupt */
167 HAL_TXQ_TXERRINT_ENABLE = 0x0001, /* enable TXERR interrupt */
168 HAL_TXQ_TXDESCINT_ENABLE = 0x0002, /* enable TXDESC interrupt */
169 HAL_TXQ_TXEOLINT_ENABLE = 0x0004, /* enable TXEOL interrupt */
170 HAL_TXQ_TXURNINT_ENABLE = 0x0008, /* enable TXURN interrupt */
171 /*
172 * Enable hardware compression for packets sent through
173 * the queue. The compression buffer must be setup and
174 * packets must have a key entry marked in the tx descriptor.
175 */
176 HAL_TXQ_COMPRESSION_ENABLE = 0x0010, /* enable h/w compression */
177 /*
178 * Disable queue when veol is hit or ready time expires.
179 * By default the queue is disabled only on reaching the
180 * physical end of queue (i.e. a null link ptr in the
181 * descriptor chain).
182 */
183 HAL_TXQ_RDYTIME_EXP_POLICY_ENABLE = 0x0020,
184 /*
185 * Schedule frames on delivery of a DBA (DMA Beacon Alert)
186 * event. Frames will be transmitted only when this timer
187 * fires, e.g to transmit a beacon in ap or adhoc modes.
188 */
189 HAL_TXQ_DBA_GATED = 0x0040, /* schedule based on DBA */
190 /*
191 * Each transmit queue has a counter that is incremented
192 * each time the queue is enabled and decremented when
193 * the list of frames to transmit is traversed (or when
194 * the ready time for the queue expires). This counter
195 * must be non-zero for frames to be scheduled for
196 * transmission. The following controls disable bumping
197 * this counter under certain conditions. Typically this
198 * is used to gate frames based on the contents of another
199 * queue (e.g. CAB traffic may only follow a beacon frame).
200 * These are meaningful only when frames are scheduled
201 * with a non-ASAP policy (e.g. DBA-gated).
202 */
203 HAL_TXQ_CBR_DIS_QEMPTY = 0x0080, /* disable on this q empty */
204 HAL_TXQ_CBR_DIS_BEMPTY = 0x0100, /* disable on beacon q empty */
205
206 /*
207 * Fragment burst backoff policy. Normally the no backoff
208 * is done after a successful transmission, the next fragment
209 * is sent at SIFS. If this flag is set backoff is done
210 * after each fragment, regardless whether it was ack'd or
211 * not, after the backoff count reaches zero a normal channel
212 * access procedure is done before the next transmit (i.e.
213 * wait AIFS instead of SIFS).
214 */
215 HAL_TXQ_FRAG_BURST_BACKOFF_ENABLE = 0x00800000,
216 /*
217 * Disable post-tx backoff following each frame.
218 */
219 HAL_TXQ_BACKOFF_DISABLE = 0x00010000, /* disable post backoff */
220 /*
221 * DCU arbiter lockout control. This controls how
222 * lower priority tx queues are handled with respect to
223 * to a specific queue when multiple queues have frames
224 * to send. No lockout means lower priority queues arbitrate
225 * concurrently with this queue. Intra-frame lockout
226 * means lower priority queues are locked out until the
227 * current frame transmits (e.g. including backoffs and bursting).
228 * Global lockout means nothing lower can arbitrary so
229 * long as there is traffic activity on this queue (frames,
230 * backoff, etc).
231 */
232 HAL_TXQ_ARB_LOCKOUT_INTRA = 0x00020000, /* intra-frame lockout */
233 HAL_TXQ_ARB_LOCKOUT_GLOBAL = 0x00040000, /* full lockout s */
234
235 HAL_TXQ_IGNORE_VIRTCOL = 0x00080000, /* ignore virt collisions */
236 HAL_TXQ_SEQNUM_INC_DIS = 0x00100000, /* disable seqnum increment */
237 } HAL_TX_QUEUE_FLAGS;
238
239 typedef struct {
240 uint32_t tqi_ver; /* hal TXQ version */
241 HAL_TX_QUEUE_SUBTYPE tqi_subtype; /* subtype if applicable */
242 HAL_TX_QUEUE_FLAGS tqi_qflags; /* flags (see above) */
243 uint32_t tqi_priority; /* (not used) */
244 uint32_t tqi_aifs; /* aifs */
245 uint32_t tqi_cwmin; /* cwMin */
246 uint32_t tqi_cwmax; /* cwMax */
247 uint16_t tqi_shretry; /* rts retry limit */
248 uint16_t tqi_lgretry; /* long retry limit (not used)*/
249 uint32_t tqi_cbrPeriod; /* CBR period (us) */
250 uint32_t tqi_cbrOverflowLimit; /* threshold for CBROVF int */
251 uint32_t tqi_burstTime; /* max burst duration (us) */
252 uint32_t tqi_readyTime; /* frame schedule time (us) */
253 uint32_t tqi_compBuf; /* comp buffer phys addr */
254 } HAL_TXQ_INFO;
255
256 #define HAL_TQI_NONVAL 0xffff
257
258 /* token to use for aifs, cwmin, cwmax */
259 #define HAL_TXQ_USEDEFAULT ((uint32_t) -1)
260
261 /* compression definitions */
262 #define HAL_COMP_BUF_MAX_SIZE 9216 /* 9K */
263 #define HAL_COMP_BUF_ALIGN_SIZE 512
264
265 /*
266 * Transmit packet types. This belongs in ah_desc.h, but
267 * is here so we can give a proper type to various parameters
268 * (and not require everyone include the file).
269 *
270 * NB: These values are intentionally assigned for
271 * direct use when setting up h/w descriptors.
272 */
273 typedef enum {
274 HAL_PKT_TYPE_NORMAL = 0,
275 HAL_PKT_TYPE_ATIM = 1,
276 HAL_PKT_TYPE_PSPOLL = 2,
277 HAL_PKT_TYPE_BEACON = 3,
278 HAL_PKT_TYPE_PROBE_RESP = 4,
279 HAL_PKT_TYPE_CHIRP = 5,
280 HAL_PKT_TYPE_GRP_POLL = 6,
281 HAL_PKT_TYPE_AMPDU = 7,
282 } HAL_PKT_TYPE;
283
284 /* Rx Filter Frame Types */
285 typedef enum {
286 HAL_RX_FILTER_UCAST = 0x00000001, /* Allow unicast frames */
287 HAL_RX_FILTER_MCAST = 0x00000002, /* Allow multicast frames */
288 HAL_RX_FILTER_BCAST = 0x00000004, /* Allow broadcast frames */
289 HAL_RX_FILTER_CONTROL = 0x00000008, /* Allow control frames */
290 HAL_RX_FILTER_BEACON = 0x00000010, /* Allow beacon frames */
291 HAL_RX_FILTER_PROM = 0x00000020, /* Promiscuous mode */
292 HAL_RX_FILTER_PROBEREQ = 0x00000080, /* Allow probe request frames */
293 HAL_RX_FILTER_PHYERR = 0x00000100, /* Allow phy errors */
294 HAL_RX_FILTER_PHYRADAR = 0x00000200, /* Allow phy radar errors */
295 HAL_RX_FILTER_COMPBAR = 0x00000400, /* Allow compressed BAR */
296 } HAL_RX_FILTER;
297
298 typedef enum {
299 HAL_PM_AWAKE = 0,
300 HAL_PM_FULL_SLEEP = 1,
301 HAL_PM_NETWORK_SLEEP = 2,
302 HAL_PM_UNDEFINED = 3
303 } HAL_POWER_MODE;
304
305 /*
306 * NOTE WELL:
307 * These are mapped to take advantage of the common locations for many of
308 * the bits on all of the currently supported MAC chips. This is to make
309 * the ISR as efficient as possible, while still abstracting HW differences.
310 * When new hardware breaks this commonality this enumerated type, as well
311 * as the HAL functions using it, must be modified. All values are directly
312 * mapped unless commented otherwise.
313 */
314 typedef enum {
315 HAL_INT_RX = 0x00000001, /* Non-common mapping */
316 HAL_INT_RXDESC = 0x00000002,
317 HAL_INT_RXNOFRM = 0x00000008,
318 HAL_INT_RXEOL = 0x00000010,
319 HAL_INT_RXORN = 0x00000020,
320 HAL_INT_TX = 0x00000040, /* Non-common mapping */
321 HAL_INT_TXDESC = 0x00000080,
322 HAL_INT_TXURN = 0x00000800,
323 HAL_INT_MIB = 0x00001000,
324 HAL_INT_RXPHY = 0x00004000,
325 HAL_INT_RXKCM = 0x00008000,
326 HAL_INT_SWBA = 0x00010000,
327 HAL_INT_BMISS = 0x00040000,
328 HAL_INT_BNR = 0x00100000, /* Non-common mapping */
329 HAL_INT_TIM = 0x00200000, /* Non-common mapping */
330 HAL_INT_DTIM = 0x00400000, /* Non-common mapping */
331 HAL_INT_DTIMSYNC= 0x00800000, /* Non-common mapping */
332 HAL_INT_GPIO = 0x01000000,
333 HAL_INT_CABEND = 0x02000000, /* Non-common mapping */
334 HAL_INT_TSFOOR = 0x04000000, /* Non-common mapping */
335 HAL_INT_CST = 0x10000000, /* Non-common mapping */
336 HAL_INT_GTT = 0x20000000, /* Non-common mapping */
337 HAL_INT_FATAL = 0x40000000, /* Non-common mapping */
338 #define HAL_INT_GLOBAL 0x80000000 /* Set/clear IER */
339 HAL_INT_BMISC = HAL_INT_TIM
340 | HAL_INT_DTIM
341 | HAL_INT_DTIMSYNC
342 | HAL_INT_CABEND,
343
344 /* Interrupt bits that map directly to ISR/IMR bits */
345 HAL_INT_COMMON = HAL_INT_RXNOFRM
346 | HAL_INT_RXDESC
347 | HAL_INT_RXEOL
348 | HAL_INT_RXORN
349 | HAL_INT_TXURN
350 | HAL_INT_TXDESC
351 | HAL_INT_MIB
352 | HAL_INT_RXPHY
353 | HAL_INT_RXKCM
354 | HAL_INT_SWBA
355 | HAL_INT_BMISS
356 | HAL_INT_GPIO,
357 } HAL_INT;
358
359 typedef enum {
360 HAL_RFGAIN_INACTIVE = 0,
361 HAL_RFGAIN_READ_REQUESTED = 1,
362 HAL_RFGAIN_NEED_CHANGE = 2
363 } HAL_RFGAIN;
364
365 /*
366 * Channels are specified by frequency.
367 */
368 typedef struct {
369 uint32_t channelFlags; /* see below */
370 uint16_t channel; /* setting in Mhz */
371 uint8_t privFlags;
372 int8_t maxRegTxPower; /* max regulatory tx power in dBm */
373 int8_t maxTxPower; /* max true tx power in 0.5 dBm */
374 int8_t minTxPower; /* min true tx power in 0.5 dBm */
375 } HAL_CHANNEL;
376
377 /* channelFlags */
378 #define CHANNEL_CW_INT 0x00002 /* CW interference detected on channel */
379 #define CHANNEL_TURBO 0x00010 /* Turbo Channel */
380 #define CHANNEL_CCK 0x00020 /* CCK channel */
381 #define CHANNEL_OFDM 0x00040 /* OFDM channel */
382 #define CHANNEL_2GHZ 0x00080 /* 2 GHz spectrum channel */
383 #define CHANNEL_5GHZ 0x00100 /* 5 GHz spectrum channel */
384 #define CHANNEL_PASSIVE 0x00200 /* Only passive scan allowed in the channel */
385 #define CHANNEL_DYN 0x00400 /* dynamic CCK-OFDM channel */
386 #define CHANNEL_STURBO 0x02000 /* Static turbo, no 11a-only usage */
387 #define CHANNEL_HALF 0x04000 /* Half rate channel */
388 #define CHANNEL_QUARTER 0x08000 /* Quarter rate channel */
389 #define CHANNEL_HT20 0x10000 /* 11n 20MHZ channel */
390 #define CHANNEL_HT40PLUS 0x20000 /* 11n 40MHZ channel w/ ext chan above */
391 #define CHANNEL_HT40MINUS 0x40000 /* 11n 40MHZ channel w/ ext chan below */
392
393 /* privFlags */
394 #define CHANNEL_INTERFERENCE 0x01 /* Software use: channel interference
395 used for as AR as well as RADAR
396 interference detection */
397 #define CHANNEL_DFS 0x02 /* DFS required on channel */
398 #define CHANNEL_4MS_LIMIT 0x04 /* 4msec packet limit on this channel */
399 #define CHANNEL_DFS_CLEAR 0x08 /* if channel has been checked for DFS */
400
401 #define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM)
402 #define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK)
403 #define CHANNEL_PUREG (CHANNEL_2GHZ|CHANNEL_OFDM)
404 #ifdef notdef
405 #define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_DYN)
406 #else
407 #define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM)
408 #endif
409 #define CHANNEL_T (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_TURBO)
410 #define CHANNEL_ST (CHANNEL_T|CHANNEL_STURBO)
411 #define CHANNEL_108G (CHANNEL_2GHZ|CHANNEL_OFDM|CHANNEL_TURBO)
412 #define CHANNEL_108A CHANNEL_T
413 #define CHANNEL_G_HT20 (CHANNEL_G|CHANNEL_HT20)
414 #define CHANNEL_A_HT20 (CHANNEL_A|CHANNEL_HT20)
415 #define CHANNEL_G_HT40PLUS (CHANNEL_G|CHANNEL_HT40PLUS)
416 #define CHANNEL_G_HT40MINUS (CHANNEL_G|CHANNEL_HT40MINUS)
417 #define CHANNEL_A_HT40PLUS (CHANNEL_A|CHANNEL_HT40PLUS)
418 #define CHANNEL_A_HT40MINUS (CHANNEL_A|CHANNEL_HT40MINUS)
419 #define CHANNEL_ALL \
420 (CHANNEL_OFDM | CHANNEL_CCK| CHANNEL_2GHZ | CHANNEL_5GHZ | \
421 CHANNEL_TURBO | CHANNEL_HT20 | CHANNEL_HT40PLUS | CHANNEL_HT40MINUS)
422 #define CHANNEL_ALL_NOTURBO (CHANNEL_ALL &~ CHANNEL_TURBO)
423
424 #define HAL_ANTENNA_MIN_MODE 0
425 #define HAL_ANTENNA_FIXED_A 1
426 #define HAL_ANTENNA_FIXED_B 2
427 #define HAL_ANTENNA_MAX_MODE 3
428
429 typedef struct {
430 uint32_t ackrcv_bad;
431 uint32_t rts_bad;
432 uint32_t rts_good;
433 uint32_t fcs_bad;
434 uint32_t beacons;
435 } HAL_MIB_STATS;
436
437 typedef uint16_t HAL_CTRY_CODE; /* country code */
438 typedef uint16_t HAL_REG_DOMAIN; /* regulatory domain code */
439
440 enum {
441 CTRY_DEBUG = 0x1ff, /* debug country code */
442 CTRY_DEFAULT = 0 /* default country code */
443 };
444
445 enum {
446 HAL_MODE_11A = 0x001, /* 11a channels */
447 HAL_MODE_TURBO = 0x002, /* 11a turbo-only channels */
448 HAL_MODE_11B = 0x004, /* 11b channels */
449 HAL_MODE_PUREG = 0x008, /* 11g channels (OFDM only) */
450 #ifdef notdef
451 HAL_MODE_11G = 0x010, /* 11g channels (OFDM/CCK) */
452 #else
453 HAL_MODE_11G = 0x008, /* XXX historical */
454 #endif
455 HAL_MODE_108G = 0x020, /* 11g+Turbo channels */
456 HAL_MODE_108A = 0x040, /* 11a+Turbo channels */
457 HAL_MODE_11A_HALF_RATE = 0x200, /* 11a half width channels */
458 HAL_MODE_11A_QUARTER_RATE = 0x400, /* 11a quarter width channels */
459 HAL_MODE_11G_HALF_RATE = 0x800, /* 11g half width channels */
460 HAL_MODE_11G_QUARTER_RATE = 0x1000, /* 11g quarter width channels */
461 HAL_MODE_11NG_HT20 = 0x008000,
462 HAL_MODE_11NA_HT20 = 0x010000,
463 HAL_MODE_11NG_HT40PLUS = 0x020000,
464 HAL_MODE_11NG_HT40MINUS = 0x040000,
465 HAL_MODE_11NA_HT40PLUS = 0x080000,
466 HAL_MODE_11NA_HT40MINUS = 0x100000,
467 HAL_MODE_ALL = 0xffffff
468 };
469
470 typedef struct {
471 int rateCount; /* NB: for proper padding */
472 uint8_t rateCodeToIndex[144]; /* back mapping */
473 struct {
474 uint8_t valid; /* valid for rate control use */
475 uint8_t phy; /* CCK/OFDM/XR */
476 uint32_t rateKbps; /* transfer rate in kbs */
477 uint8_t rateCode; /* rate for h/w descriptors */
478 uint8_t shortPreamble; /* mask for enabling short
479 * preamble in CCK rate code */
480 uint8_t dot11Rate; /* value for supported rates
481 * info element of MLME */
482 uint8_t controlRate; /* index of next lower basic
483 * rate; used for dur. calcs */
484 uint16_t lpAckDuration; /* long preamble ACK duration */
485 uint16_t spAckDuration; /* short preamble ACK duration*/
486 } info[32];
487 } HAL_RATE_TABLE;
488
489 typedef struct {
490 u_int rs_count; /* number of valid entries */
491 uint8_t rs_rates[32]; /* rates */
492 } HAL_RATE_SET;
493
494 /*
495 * 802.11n specific structures and enums
496 */
497 typedef enum {
498 HAL_CHAINTYPE_TX = 1, /* Tx chain type */
499 HAL_CHAINTYPE_RX = 2, /* RX chain type */
500 } HAL_CHAIN_TYPE;
501
502 typedef struct {
503 u_int Tries;
504 u_int Rate;
505 u_int PktDuration;
506 u_int ChSel;
507 u_int RateFlags;
508 #define HAL_RATESERIES_RTS_CTS 0x0001 /* use rts/cts w/this series */
509 #define HAL_RATESERIES_2040 0x0002 /* use ext channel for series */
510 #define HAL_RATESERIES_HALFGI 0x0004 /* use half-gi for series */
511 } HAL_11N_RATE_SERIES;
512
513 typedef enum {
514 HAL_HT_MACMODE_20 = 0, /* 20 MHz operation */
515 HAL_HT_MACMODE_2040 = 1, /* 20/40 MHz operation */
516 } HAL_HT_MACMODE;
517
518 typedef enum {
519 HAL_HT_PHYMODE_20 = 0, /* 20 MHz operation */
520 HAL_HT_PHYMODE_2040 = 1, /* 20/40 MHz operation */
521 } HAL_HT_PHYMODE;
522
523 typedef enum {
524 HAL_HT_EXTPROTSPACING_20 = 0, /* 20 MHz spacing */
525 HAL_HT_EXTPROTSPACING_25 = 1, /* 25 MHz spacing */
526 } HAL_HT_EXTPROTSPACING;
527
528
529 typedef enum {
530 HAL_RX_CLEAR_CTL_LOW = 0x1, /* force control channel to appear busy */
531 HAL_RX_CLEAR_EXT_LOW = 0x2, /* force extension channel to appear busy */
532 } HAL_HT_RXCLEAR;
533
534 /*
535 * Antenna switch control. By default antenna selection
536 * enables multiple (2) antenna use. To force use of the
537 * A or B antenna only specify a fixed setting. Fixing
538 * the antenna will also disable any diversity support.
539 */
540 typedef enum {
541 HAL_ANT_VARIABLE = 0, /* variable by programming */
542 HAL_ANT_FIXED_A = 1, /* fixed antenna A */
543 HAL_ANT_FIXED_B = 2, /* fixed antenna B */
544 } HAL_ANT_SETTING;
545
546 typedef enum {
547 HAL_M_STA = 1, /* infrastructure station */
548 HAL_M_IBSS = 0, /* IBSS (adhoc) station */
549 HAL_M_HOSTAP = 6, /* Software Access Point */
550 HAL_M_MONITOR = 8 /* Monitor mode */
551 } HAL_OPMODE;
552
553 typedef struct {
554 uint8_t kv_type; /* one of HAL_CIPHER */
555 uint8_t kv_pad;
556 uint16_t kv_len; /* length in bits */
557 uint8_t kv_val[16]; /* enough for 128-bit keys */
558 uint8_t kv_mic[8]; /* TKIP MIC key */
559 uint8_t kv_txmic[8]; /* TKIP TX MIC key (optional) */
560 } HAL_KEYVAL;
561
562 typedef enum {
563 HAL_CIPHER_WEP = 0,
564 HAL_CIPHER_AES_OCB = 1,
565 HAL_CIPHER_AES_CCM = 2,
566 HAL_CIPHER_CKIP = 3,
567 HAL_CIPHER_TKIP = 4,
568 HAL_CIPHER_CLR = 5, /* no encryption */
569
570 HAL_CIPHER_MIC = 127 /* TKIP-MIC, not a cipher */
571 } HAL_CIPHER;
572
573 enum {
574 HAL_SLOT_TIME_6 = 6, /* NB: for turbo mode */
575 HAL_SLOT_TIME_9 = 9,
576 HAL_SLOT_TIME_20 = 20,
577 };
578
579 /*
580 * Per-station beacon timer state. Note that the specified
581 * beacon interval (given in TU's) can also include flags
582 * to force a TSF reset and to enable the beacon xmit logic.
583 * If bs_cfpmaxduration is non-zero the hardware is setup to
584 * coexist with a PCF-capable AP.
585 */
586 typedef struct {
587 uint32_t bs_nexttbtt; /* next beacon in TU */
588 uint32_t bs_nextdtim; /* next DTIM in TU */
589 uint32_t bs_intval; /* beacon interval+flags */
590 #define HAL_BEACON_PERIOD 0x0000ffff /* beacon interval period */
591 #define HAL_BEACON_ENA 0x00800000 /* beacon xmit enable */
592 #define HAL_BEACON_RESET_TSF 0x01000000 /* clear TSF */
593 uint32_t bs_dtimperiod;
594 uint16_t bs_cfpperiod; /* CFP period in TU */
595 uint16_t bs_cfpmaxduration; /* max CFP duration in TU */
596 uint32_t bs_cfpnext; /* next CFP in TU */
597 uint16_t bs_timoffset; /* byte offset to TIM bitmap */
598 uint16_t bs_bmissthreshold; /* beacon miss threshold */
599 uint32_t bs_sleepduration; /* max sleep duration */
600 } HAL_BEACON_STATE;
601
602 /*
603 * Like HAL_BEACON_STATE but for non-station mode setup.
604 * NB: see above flag definitions for bt_intval.
605 */
606 typedef struct {
607 uint32_t bt_intval; /* beacon interval+flags */
608 uint32_t bt_nexttbtt; /* next beacon in TU */
609 uint32_t bt_nextatim; /* next ATIM in TU */
610 uint32_t bt_nextdba; /* next DBA in 1/8th TU */
611 uint32_t bt_nextswba; /* next SWBA in 1/8th TU */
612 uint32_t bt_flags; /* timer enables */
613 #define HAL_BEACON_TBTT_EN 0x00000001
614 #define HAL_BEACON_DBA_EN 0x00000002
615 #define HAL_BEACON_SWBA_EN 0x00000004
616 } HAL_BEACON_TIMERS;
617
618 /*
619 * Per-node statistics maintained by the driver for use in
620 * optimizing signal quality and other operational aspects.
621 */
622 typedef struct {
623 uint32_t ns_avgbrssi; /* average beacon rssi */
624 uint32_t ns_avgrssi; /* average data rssi */
625 uint32_t ns_avgtxrssi; /* average tx rssi */
626 } HAL_NODE_STATS;
627
628 #define HAL_RSSI_EP_MULTIPLIER (1<<7) /* pow2 to optimize out * and / */
629
630 struct ath_desc;
631 struct ath_tx_status;
632 struct ath_rx_status;
633
634 /*
635 * Hardware Access Layer (HAL) API.
636 *
637 * Clients of the HAL call ath_hal_attach to obtain a reference to an
638 * ath_hal structure for use with the device. Hardware-related operations
639 * that follow must call back into the HAL through interface, supplying
640 * the reference as the first parameter. Note that before using the
641 * reference returned by ath_hal_attach the caller should verify the
642 * ABI version number.
643 */
644 struct ath_hal {
645 uint32_t ah_magic; /* consistency check magic number */
646 uint32_t ah_abi; /* HAL ABI version */
647 #define HAL_ABI_VERSION 0x08112800 /* YYMMDDnn */
648 uint16_t ah_devid; /* PCI device ID */
649 uint16_t ah_subvendorid; /* PCI subvendor ID */
650 HAL_SOFTC ah_sc; /* back pointer to driver/os state */
651 HAL_BUS_TAG ah_st; /* params for register r+w */
652 HAL_BUS_HANDLE ah_sh;
653 HAL_CTRY_CODE ah_countryCode;
654
655 uint32_t ah_macVersion; /* MAC version id */
656 uint16_t ah_macRev; /* MAC revision */
657 uint16_t ah_phyRev; /* PHY revision */
658 /* NB: when only one radio is present the rev is in 5Ghz */
659 uint16_t ah_analog5GhzRev;/* 5GHz radio revision */
660 uint16_t ah_analog2GhzRev;/* 2GHz radio revision */
661
662 const HAL_RATE_TABLE *__ahdecl(*ah_getRateTable)(struct ath_hal *,
663 u_int mode);
664 void __ahdecl(*ah_detach)(struct ath_hal*);
665
666 /* Reset functions */
667 HAL_BOOL __ahdecl(*ah_reset)(struct ath_hal *, HAL_OPMODE,
668 HAL_CHANNEL *, HAL_BOOL bChannelChange,
669 HAL_STATUS *status);
670 HAL_BOOL __ahdecl(*ah_phyDisable)(struct ath_hal *);
671 HAL_BOOL __ahdecl(*ah_disable)(struct ath_hal *);
672 void __ahdecl(*ah_setPCUConfig)(struct ath_hal *);
673 HAL_BOOL __ahdecl(*ah_perCalibration)(struct ath_hal*, HAL_CHANNEL *,
674 HAL_BOOL *);
675 HAL_BOOL __ahdecl(*ah_perCalibrationN)(struct ath_hal *, HAL_CHANNEL *,
676 u_int chainMask, HAL_BOOL longCal, HAL_BOOL *isCalDone);
677 HAL_BOOL __ahdecl(*ah_resetCalValid)(struct ath_hal *, HAL_CHANNEL *);
678 HAL_BOOL __ahdecl(*ah_setTxPowerLimit)(struct ath_hal *, uint32_t);
679
680 /* Transmit functions */
681 HAL_BOOL __ahdecl(*ah_updateTxTrigLevel)(struct ath_hal*,
682 HAL_BOOL incTrigLevel);
683 int __ahdecl(*ah_setupTxQueue)(struct ath_hal *, HAL_TX_QUEUE,
684 const HAL_TXQ_INFO *qInfo);
685 HAL_BOOL __ahdecl(*ah_setTxQueueProps)(struct ath_hal *, int q,
686 const HAL_TXQ_INFO *qInfo);
687 HAL_BOOL __ahdecl(*ah_getTxQueueProps)(struct ath_hal *, int q,
688 HAL_TXQ_INFO *qInfo);
689 HAL_BOOL __ahdecl(*ah_releaseTxQueue)(struct ath_hal *ah, u_int q);
690 HAL_BOOL __ahdecl(*ah_resetTxQueue)(struct ath_hal *ah, u_int q);
691 uint32_t __ahdecl(*ah_getTxDP)(struct ath_hal*, u_int);
692 HAL_BOOL __ahdecl(*ah_setTxDP)(struct ath_hal*, u_int, uint32_t txdp);
693 uint32_t __ahdecl(*ah_numTxPending)(struct ath_hal *, u_int q);
694 HAL_BOOL __ahdecl(*ah_startTxDma)(struct ath_hal*, u_int);
695 HAL_BOOL __ahdecl(*ah_stopTxDma)(struct ath_hal*, u_int);
696 HAL_BOOL __ahdecl(*ah_setupTxDesc)(struct ath_hal *, struct ath_desc *,
697 u_int pktLen, u_int hdrLen,
698 HAL_PKT_TYPE type, u_int txPower,
699 u_int txRate0, u_int txTries0,
700 u_int keyIx, u_int antMode, u_int flags,
701 u_int rtsctsRate, u_int rtsctsDuration,
702 u_int compicvLen, u_int compivLen,
703 u_int comp);
704 HAL_BOOL __ahdecl(*ah_setupXTxDesc)(struct ath_hal *, struct ath_desc*,
705 u_int txRate1, u_int txTries1,
706 u_int txRate2, u_int txTries2,
707 u_int txRate3, u_int txTries3);
708 HAL_BOOL __ahdecl(*ah_fillTxDesc)(struct ath_hal *, struct ath_desc *,
709 u_int segLen, HAL_BOOL firstSeg,
710 HAL_BOOL lastSeg, const struct ath_desc *);
711 HAL_STATUS __ahdecl(*ah_procTxDesc)(struct ath_hal *,
712 struct ath_desc *, struct ath_tx_status *);
713 void __ahdecl(*ah_getTxIntrQueue)(struct ath_hal *, uint32_t *);
714 void __ahdecl(*ah_reqTxIntrDesc)(struct ath_hal *, struct ath_desc*);
715
716 /* Receive Functions */
717 uint32_t __ahdecl(*ah_getRxDP)(struct ath_hal*);
718 void __ahdecl(*ah_setRxDP)(struct ath_hal*, uint32_t rxdp);
719 void __ahdecl(*ah_enableReceive)(struct ath_hal*);
720 HAL_BOOL __ahdecl(*ah_stopDmaReceive)(struct ath_hal*);
721 void __ahdecl(*ah_startPcuReceive)(struct ath_hal*);
722 void __ahdecl(*ah_stopPcuReceive)(struct ath_hal*);
723 void __ahdecl(*ah_setMulticastFilter)(struct ath_hal*,
724 uint32_t filter0, uint32_t filter1);
725 HAL_BOOL __ahdecl(*ah_setMulticastFilterIndex)(struct ath_hal*,
726 uint32_t index);
727 HAL_BOOL __ahdecl(*ah_clrMulticastFilterIndex)(struct ath_hal*,
728 uint32_t index);
729 uint32_t __ahdecl(*ah_getRxFilter)(struct ath_hal*);
730 void __ahdecl(*ah_setRxFilter)(struct ath_hal*, uint32_t);
731 HAL_BOOL __ahdecl(*ah_setupRxDesc)(struct ath_hal *, struct ath_desc *,
732 uint32_t size, u_int flags);
733 HAL_STATUS __ahdecl(*ah_procRxDesc)(struct ath_hal *,
734 struct ath_desc *, uint32_t phyAddr,
735 struct ath_desc *next, uint64_t tsf,
736 struct ath_rx_status *);
737 void __ahdecl(*ah_rxMonitor)(struct ath_hal *,
738 const HAL_NODE_STATS *, HAL_CHANNEL *);
739 void __ahdecl(*ah_procMibEvent)(struct ath_hal *,
740 const HAL_NODE_STATS *);
741
742 /* Misc Functions */
743 HAL_STATUS __ahdecl(*ah_getCapability)(struct ath_hal *,
744 HAL_CAPABILITY_TYPE, uint32_t capability,
745 uint32_t *result);
746 HAL_BOOL __ahdecl(*ah_setCapability)(struct ath_hal *,
747 HAL_CAPABILITY_TYPE, uint32_t capability,
748 uint32_t setting, HAL_STATUS *);
749 HAL_BOOL __ahdecl(*ah_getDiagState)(struct ath_hal *, int request,
750 const void *args, uint32_t argsize,
751 void **result, uint32_t *resultsize);
752 void __ahdecl(*ah_getMacAddress)(struct ath_hal *, uint8_t *);
753 HAL_BOOL __ahdecl(*ah_setMacAddress)(struct ath_hal *, const uint8_t*);
754 void __ahdecl(*ah_getBssIdMask)(struct ath_hal *, uint8_t *);
755 HAL_BOOL __ahdecl(*ah_setBssIdMask)(struct ath_hal *, const uint8_t*);
756 HAL_BOOL __ahdecl(*ah_setRegulatoryDomain)(struct ath_hal*,
757 uint16_t, HAL_STATUS *);
758 void __ahdecl(*ah_setLedState)(struct ath_hal*, HAL_LED_STATE);
759 void __ahdecl(*ah_writeAssocid)(struct ath_hal*,
760 const uint8_t *bssid, uint16_t assocId);
761 HAL_BOOL __ahdecl(*ah_gpioCfgOutput)(struct ath_hal *, uint32_t gpio);
762 HAL_BOOL __ahdecl(*ah_gpioCfgInput)(struct ath_hal *, uint32_t gpio);
763 uint32_t __ahdecl(*ah_gpioGet)(struct ath_hal *, uint32_t gpio);
764 HAL_BOOL __ahdecl(*ah_gpioSet)(struct ath_hal *,
765 uint32_t gpio, uint32_t val);
766 void __ahdecl(*ah_gpioSetIntr)(struct ath_hal*, u_int, uint32_t);
767 uint32_t __ahdecl(*ah_getTsf32)(struct ath_hal*);
768 uint64_t __ahdecl(*ah_getTsf64)(struct ath_hal*);
769 void __ahdecl(*ah_resetTsf)(struct ath_hal*);
770 HAL_BOOL __ahdecl(*ah_detectCardPresent)(struct ath_hal*);
771 void __ahdecl(*ah_updateMibCounters)(struct ath_hal*,
772 HAL_MIB_STATS*);
773 HAL_RFGAIN __ahdecl(*ah_getRfGain)(struct ath_hal*);
774 u_int __ahdecl(*ah_getDefAntenna)(struct ath_hal*);
775 void __ahdecl(*ah_setDefAntenna)(struct ath_hal*, u_int);
776 HAL_ANT_SETTING __ahdecl(*ah_getAntennaSwitch)(struct ath_hal*);
777 HAL_BOOL __ahdecl(*ah_setAntennaSwitch)(struct ath_hal*,
778 HAL_ANT_SETTING);
779 HAL_BOOL __ahdecl(*ah_setSifsTime)(struct ath_hal*, u_int);
780 u_int __ahdecl(*ah_getSifsTime)(struct ath_hal*);
781 HAL_BOOL __ahdecl(*ah_setSlotTime)(struct ath_hal*, u_int);
782 u_int __ahdecl(*ah_getSlotTime)(struct ath_hal*);
783 HAL_BOOL __ahdecl(*ah_setAckTimeout)(struct ath_hal*, u_int);
784 u_int __ahdecl(*ah_getAckTimeout)(struct ath_hal*);
785 HAL_BOOL __ahdecl(*ah_setAckCTSRate)(struct ath_hal*, u_int);
786 u_int __ahdecl(*ah_getAckCTSRate)(struct ath_hal*);
787 HAL_BOOL __ahdecl(*ah_setCTSTimeout)(struct ath_hal*, u_int);
788 u_int __ahdecl(*ah_getCTSTimeout)(struct ath_hal*);
789 HAL_BOOL __ahdecl(*ah_setDecompMask)(struct ath_hal*, uint16_t, int);
790 void __ahdecl(*ah_setCoverageClass)(struct ath_hal*, uint8_t, int);
791
792 /* Key Cache Functions */
793 uint32_t __ahdecl(*ah_getKeyCacheSize)(struct ath_hal*);
794 HAL_BOOL __ahdecl(*ah_resetKeyCacheEntry)(struct ath_hal*, uint16_t);
795 HAL_BOOL __ahdecl(*ah_isKeyCacheEntryValid)(struct ath_hal *,
796 uint16_t);
797 HAL_BOOL __ahdecl(*ah_setKeyCacheEntry)(struct ath_hal*,
798 uint16_t, const HAL_KEYVAL *,
799 const uint8_t *, int);
800 HAL_BOOL __ahdecl(*ah_setKeyCacheEntryMac)(struct ath_hal*,
801 uint16_t, const uint8_t *);
802
803 /* Power Management Functions */
804 HAL_BOOL __ahdecl(*ah_setPowerMode)(struct ath_hal*,
805 HAL_POWER_MODE mode, int setChip);
806 HAL_POWER_MODE __ahdecl(*ah_getPowerMode)(struct ath_hal*);
807 int16_t __ahdecl(*ah_getChanNoise)(struct ath_hal *, HAL_CHANNEL *);
808
809 /* Beacon Management Functions */
810 void __ahdecl(*ah_setBeaconTimers)(struct ath_hal*,
811 const HAL_BEACON_TIMERS *);
812 /* NB: deprecated, use ah_setBeaconTimers instead */
813 void __ahdecl(*ah_beaconInit)(struct ath_hal *,
814 uint32_t nexttbtt, uint32_t intval);
815 void __ahdecl(*ah_setStationBeaconTimers)(struct ath_hal*,
816 const HAL_BEACON_STATE *);
817 void __ahdecl(*ah_resetStationBeaconTimers)(struct ath_hal*);
818
819 /* Interrupt functions */
820 HAL_BOOL __ahdecl(*ah_isInterruptPending)(struct ath_hal*);
821 HAL_BOOL __ahdecl(*ah_getPendingInterrupts)(struct ath_hal*, HAL_INT*);
822 HAL_INT __ahdecl(*ah_getInterrupts)(struct ath_hal*);
823 HAL_INT __ahdecl(*ah_setInterrupts)(struct ath_hal*, HAL_INT);
824 };
825
826 /*
827 * Check the PCI vendor ID and device ID against Atheros' values
828 * and return a printable description for any Atheros hardware.
829 * AH_NULL is returned if the ID's do not describe Atheros hardware.
830 */
831 extern const char *__ahdecl ath_hal_probe(uint16_t vendorid, uint16_t devid);
832
833 /*
834 * Attach the HAL for use with the specified device. The device is
835 * defined by the PCI device ID. The caller provides an opaque pointer
836 * to an upper-layer data structure (HAL_SOFTC) that is stored in the
837 * HAL state block for later use. Hardware register accesses are done
838 * using the specified bus tag and handle. On successful return a
839 * reference to a state block is returned that must be supplied in all
840 * subsequent HAL calls. Storage associated with this reference is
841 * dynamically allocated and must be freed by calling the ah_detach
842 * method when the client is done. If the attach operation fails a
843 * null (AH_NULL) reference will be returned and a status code will
844 * be returned if the status parameter is non-zero.
845 */
846 extern struct ath_hal * __ahdecl ath_hal_attach(uint16_t devid, HAL_SOFTC,
847 HAL_BUS_TAG, HAL_BUS_HANDLE, HAL_STATUS* status);
848
849 /*
850 * Return a list of channels available for use with the hardware.
851 * The list is based on what the hardware is capable of, the specified
852 * country code, the modeSelect mask, and whether or not outdoor
853 * channels are to be permitted.
854 *
855 * The channel list is returned in the supplied array. maxchans
856 * defines the maximum size of this array. nchans contains the actual
857 * number of channels returned. If a problem occurred or there were
858 * no channels that met the criteria then AH_FALSE is returned.
859 */
860 extern HAL_BOOL __ahdecl ath_hal_init_channels(struct ath_hal *,
861 HAL_CHANNEL *chans, u_int maxchans, u_int *nchans,
862 uint8_t *regclassids, u_int maxregids, u_int *nregids,
863 HAL_CTRY_CODE cc, u_int modeSelect,
864 HAL_BOOL enableOutdoor, HAL_BOOL enableExtendedChannels);
865
866 /*
867 * Calibrate noise floor data following a channel scan or similar.
868 * This must be called prior retrieving noise floor data.
869 */
870 extern void __ahdecl ath_hal_process_noisefloor(struct ath_hal *ah);
871
872 /*
873 * Return bit mask of wireless modes supported by the hardware.
874 */
875 extern u_int __ahdecl ath_hal_getwirelessmodes(struct ath_hal*, HAL_CTRY_CODE);
876
877 /*
878 * Calculate the transmit duration of a frame.
879 */
880 extern uint16_t __ahdecl ath_hal_computetxtime(struct ath_hal *,
881 const HAL_RATE_TABLE *rates, uint32_t frameLen,
882 uint16_t rateix, HAL_BOOL shortPreamble);
883
884 /*
885 * Return if device is public safety.
886 */
887 extern HAL_BOOL __ahdecl ath_hal_ispublicsafetysku(struct ath_hal *);
888
889 /*
890 * Return if device is operating in 900 MHz band.
891 */
892 extern HAL_BOOL ath_hal_isgsmsku(struct ath_hal *);
893
894 /*
895 * Convert between IEEE channel number and channel frequency
896 * using the specified channel flags; e.g. CHANNEL_2GHZ.
897 */
898 extern int __ahdecl ath_hal_mhz2ieee(struct ath_hal *, u_int mhz, u_int flags);
899 #endif /* _ATH_AH_H_ */
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