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[netbsd-mini2440.git] / sys / external / isc / atheros_hal / dist / ah_internal.h
blob09b3b749d15f870d182d6951dac50641b03fe386
1 /*
2 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
3 * Copyright (c) 2002-2008 Atheros Communications, Inc.
4 *
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 *
17 * $Id: ah_internal.h,v 1.3 2009/05/14 09:07:49 reinoud Exp $
18 */
19 #ifndef _ATH_AH_INTERAL_H_
20 #define _ATH_AH_INTERAL_H_
21 /*
22 * Atheros Device Hardware Access Layer (HAL).
23 *
24 * Internal definitions.
25 */
26 #define AH_NULL 0
27 #define AH_MIN(a,b) ((a)<(b)?(a):(b))
28 #define AH_MAX(a,b) ((a)>(b)?(a):(b))
29
30 #ifndef NBBY
31 #define NBBY 8 /* number of bits/byte */
32 #endif
33
34 #ifndef roundup
35 #define roundup(x, y) ((((x)+((y)-1))/(y))*(y)) /* to any y */
36 #endif
37 #ifndef howmany
38 #define howmany(x, y) (((x)+((y)-1))/(y))
39 #endif
40
41 #ifndef offsetof
42 #define offsetof(type, field) ((size_t)(&((type *)0)->field))
43 #endif
44
45 /*
46 * Remove const in a way that keeps the compiler happy.
47 * This works for gcc but may require other magic for
48 * other compilers (not sure where this should reside).
49 * Note that uintptr_t is C99.
50 */
51 #ifndef __DECONST
52 #define __DECONST(type, var) ((type)(unsigned long)(const void *)(var))
53 #endif
54
55 typedef struct {
56 uint16_t start; /* first register */
57 uint16_t end; /* ending register or zero */
58 } HAL_REGRANGE;
59
60 /*
61 * Transmit power scale factor.
62 *
63 * NB: This is not public because we want to discourage the use of
64 * scaling; folks should use the tx power limit interface.
65 */
66 typedef enum {
67 HAL_TP_SCALE_MAX = 0, /* no scaling (default) */
68 HAL_TP_SCALE_50 = 1, /* 50% of max (-3 dBm) */
69 HAL_TP_SCALE_25 = 2, /* 25% of max (-6 dBm) */
70 HAL_TP_SCALE_12 = 3, /* 12% of max (-9 dBm) */
71 HAL_TP_SCALE_MIN = 4, /* min, but still on */
72 } HAL_TP_SCALE;
73
74 typedef enum {
75 HAL_CAP_RADAR = 0, /* Radar capability */
76 HAL_CAP_AR = 1, /* AR capability */
77 } HAL_PHYDIAG_CAPS;
78
79 /*
80 * Each chip or class of chips registers to offer support.
81 */
82 struct ath_hal_chip {
83 const char *name;
84 const char *(*probe)(uint16_t vendorid, uint16_t devid);
85 struct ath_hal *(*attach)(uint16_t devid, HAL_SOFTC,
86 HAL_BUS_TAG, HAL_BUS_HANDLE, HAL_STATUS *error);
87 };
88 #ifndef AH_CHIP
89 #define AH_CHIP(_name, _probe, _attach) \
90 static struct ath_hal_chip name##_chip = { \
91 .name = #_name, \
92 .probe = _probe, \
93 .attach = _attach \
94 }; \
95 OS_DATA_SET(ah_chips, name##_chip)
96 #endif
97
98 /*
99 * Each RF backend registers to offer support; this is mostly
100 * used by multi-chip 5212 solutions. Single-chip solutions
101 * have a fixed idea about which RF to use.
102 */
103 struct ath_hal_rf {
104 const char *name;
105 HAL_BOOL (*probe)(struct ath_hal *ah);
106 HAL_BOOL (*attach)(struct ath_hal *ah, HAL_STATUS *ecode);
107 };
108 #ifndef AH_RF
109 #define AH_RF(_name, _probe, _attach) \
110 static struct ath_hal_rf _name##_rf = { \
111 .name = __STRING(_name), \
112 .probe = _probe, \
113 .attach = _attach \
114 }; \
115 OS_DATA_SET(ah_rfs, _name##_rf)
116 #endif
117
118 struct ath_hal_rf *ath_hal_rfprobe(struct ath_hal *ah, HAL_STATUS *ecode);
119
120 /*
121 * Internal form of a HAL_CHANNEL. Note that the structure
122 * must be defined such that you can cast references to a
123 * HAL_CHANNEL so don't shuffle the first two members.
124 */
125 typedef struct {
126 uint32_t channelFlags;
127 uint16_t channel; /* NB: must be first for casting */
128 uint8_t privFlags;
129 int8_t maxRegTxPower;
130 int8_t maxTxPower;
131 int8_t minTxPower; /* as above... */
132
133 HAL_BOOL bssSendHere;
134 uint8_t gainI;
135 HAL_BOOL iqCalValid;
136 uint8_t calValid; /* bitmask of cal types */
137 int8_t iCoff;
138 int8_t qCoff;
139 int16_t rawNoiseFloor;
140 int16_t noiseFloorAdjust;
141 int8_t antennaMax;
142 uint32_t regDmnFlags; /* Flags for channel use in reg */
143 uint32_t conformanceTestLimit; /* conformance test limit from reg domain */
144 uint16_t mainSpur; /* cached spur value for this cahnnel */
145 } HAL_CHANNEL_INTERNAL;
146
147 typedef struct {
148 uint32_t halChanSpreadSupport : 1,
149 halSleepAfterBeaconBroken : 1,
150 halCompressSupport : 1,
151 halBurstSupport : 1,
152 halFastFramesSupport : 1,
153 halChapTuningSupport : 1,
154 halTurboGSupport : 1,
155 halTurboPrimeSupport : 1,
156 halMicAesCcmSupport : 1,
157 halMicCkipSupport : 1,
158 halMicTkipSupport : 1,
159 halTkipMicTxRxKeySupport : 1,
160 halCipherAesCcmSupport : 1,
161 halCipherCkipSupport : 1,
162 halCipherTkipSupport : 1,
163 halPSPollBroken : 1,
164 halVEOLSupport : 1,
165 halBssIdMaskSupport : 1,
166 halMcastKeySrchSupport : 1,
167 halTsfAddSupport : 1,
168 halChanHalfRate : 1,
169 halChanQuarterRate : 1,
170 halHTSupport : 1,
171 halRfSilentSupport : 1,
172 halHwPhyCounterSupport : 1,
173 halWowSupport : 1,
174 halWowMatchPatternExact : 1,
175 halAutoSleepSupport : 1,
176 halFastCCSupport : 1,
177 halBtCoexSupport : 1;
178 uint32_t halRxStbcSupport : 1,
179 halTxStbcSupport : 1,
180 halGTTSupport : 1,
181 halCSTSupport : 1,
182 halRifsRxSupport : 1,
183 halRifsTxSupport : 1,
184 halExtChanDfsSupport : 1,
185 halForcePpmSupport : 1,
186 halEnhancedPmSupport : 1,
187 halMbssidAggrSupport : 1;
188 uint32_t halWirelessModes;
189 uint16_t halTotalQueues;
190 uint16_t halKeyCacheSize;
191 uint16_t halLow5GhzChan, halHigh5GhzChan;
192 uint16_t halLow2GhzChan, halHigh2GhzChan;
193 int halTstampPrecision;
194 int halRtsAggrLimit;
195 uint8_t halTxChainMask;
196 uint8_t halRxChainMask;
197 uint8_t halNumGpioPins;
198 uint8_t halNumAntCfg2GHz;
199 uint8_t halNumAntCfg5GHz;
200 } HAL_CAPABILITIES;
201
202 /*
203 * The ``private area'' follows immediately after the ``public area''
204 * in the data structure returned by ath_hal_attach. Private data are
205 * used by device-independent code such as the regulatory domain support.
206 * In general, code within the HAL should never depend on data in the
207 * public area. Instead any public data needed internally should be
208 * shadowed here.
209 *
210 * When declaring a device-specific ath_hal data structure this structure
211 * is assumed to at the front; e.g.
212 *
213 * struct ath_hal_5212 {
214 * struct ath_hal_private ah_priv;
215 * ...
216 * };
217 *
218 * It might be better to manage the method pointers in this structure
219 * using an indirect pointer to a read-only data structure but this would
220 * disallow class-style method overriding.
221 */
222 struct ath_hal_private {
223 struct ath_hal h; /* public area */
224
225 /* NB: all methods go first to simplify initialization */
226 HAL_BOOL (*ah_getChannelEdges)(struct ath_hal*,
227 uint16_t channelFlags,
228 uint16_t *lowChannel, uint16_t *highChannel);
229 u_int (*ah_getWirelessModes)(struct ath_hal*);
230 HAL_BOOL (*ah_eepromRead)(struct ath_hal *, u_int off,
231 uint16_t *data);
232 HAL_BOOL (*ah_eepromWrite)(struct ath_hal *, u_int off,
233 uint16_t data);
234 HAL_BOOL (*ah_gpioCfgOutput)(struct ath_hal *, uint32_t gpio);
235 HAL_BOOL (*ah_gpioCfgInput)(struct ath_hal *, uint32_t gpio);
236 uint32_t (*ah_gpioGet)(struct ath_hal *, uint32_t gpio);
237 HAL_BOOL (*ah_gpioSet)(struct ath_hal *,
238 uint32_t gpio, uint32_t val);
239 void (*ah_gpioSetIntr)(struct ath_hal*, u_int, uint32_t);
240 HAL_BOOL (*ah_getChipPowerLimits)(struct ath_hal *,
241 HAL_CHANNEL *, uint32_t);
242 int16_t (*ah_getNfAdjust)(struct ath_hal *,
243 const HAL_CHANNEL_INTERNAL*);
244 void (*ah_getNoiseFloor)(struct ath_hal *,
245 int16_t nfarray[]);
246
247 void *ah_eeprom; /* opaque EEPROM state */
248 uint16_t ah_eeversion; /* EEPROM version */
249 void (*ah_eepromDetach)(struct ath_hal *);
250 HAL_STATUS (*ah_eepromGet)(struct ath_hal *, int, void *);
251 HAL_BOOL (*ah_eepromSet)(struct ath_hal *, int, int);
252 uint16_t (*ah_getSpurChan)(struct ath_hal *, int, HAL_BOOL);
253 HAL_BOOL (*ah_eepromDiag)(struct ath_hal *, int request,
254 const void *args, uint32_t argsize,
255 void **result, uint32_t *resultsize);
256
257 /*
258 * Device revision information.
259 */
260 uint16_t ah_devid; /* PCI device ID */
261 uint16_t ah_subvendorid; /* PCI subvendor ID */
262 uint32_t ah_macVersion; /* MAC version id */
263 uint16_t ah_macRev; /* MAC revision */
264 uint16_t ah_phyRev; /* PHY revision */
265 uint16_t ah_analog5GhzRev; /* 2GHz radio revision */
266 uint16_t ah_analog2GhzRev; /* 5GHz radio revision */
267
268
269 HAL_OPMODE ah_opmode; /* operating mode from reset */
270 HAL_CAPABILITIES ah_caps; /* device capabilities */
271 uint32_t ah_diagreg; /* user-specified AR_DIAG_SW */
272 int16_t ah_powerLimit; /* tx power cap */
273 uint16_t ah_maxPowerLevel; /* calculated max tx power */
274 u_int ah_tpScale; /* tx power scale factor */
275 uint32_t ah_11nCompat; /* 11n compat controls */
276
277 /*
278 * State for regulatory domain handling.
279 */
280 HAL_REG_DOMAIN ah_currentRD; /* Current regulatory domain */
281 HAL_CTRY_CODE ah_countryCode; /* current country code */
282 HAL_CHANNEL_INTERNAL ah_channels[256]; /* calculated channel list */
283 u_int ah_nchan; /* valid channels in list */
284 HAL_CHANNEL_INTERNAL *ah_curchan; /* current channel */
285
286 uint8_t ah_coverageClass; /* coverage class */
287 HAL_BOOL ah_regdomainUpdate; /* regdomain is updated? */
288 /*
289 * RF Silent handling; setup according to the EEPROM.
290 */
291 uint16_t ah_rfsilent; /* GPIO pin + polarity */
292 HAL_BOOL ah_rfkillEnabled; /* enable/disable RfKill */
293 /*
294 * Diagnostic support for discriminating HIUERR reports.
295 */
296 uint32_t ah_fatalState[6]; /* AR_ISR+shadow regs */
297 int ah_rxornIsFatal; /* how to treat HAL_INT_RXORN */
298 };
299
300 #define AH_PRIVATE(_ah) ((struct ath_hal_private *)(_ah))
301
302 #define ath_hal_getChannelEdges(_ah, _cf, _lc, _hc) \
303 AH_PRIVATE(_ah)->ah_getChannelEdges(_ah, _cf, _lc, _hc)
304 #define ath_hal_getWirelessModes(_ah) \
305 AH_PRIVATE(_ah)->ah_getWirelessModes(_ah)
306 #define ath_hal_eepromRead(_ah, _off, _data) \
307 AH_PRIVATE(_ah)->ah_eepromRead(_ah, _off, _data)
308 #define ath_hal_eepromWrite(_ah, _off, _data) \
309 AH_PRIVATE(_ah)->ah_eepromWrite(_ah, _off, _data)
310 #define ath_hal_gpioCfgOutput(_ah, _gpio) \
311 AH_PRIVATE(_ah)->ah_gpioCfgOutput(_ah, _gpio)
312 #define ath_hal_gpioCfgInput(_ah, _gpio) \
313 AH_PRIVATE(_ah)->ah_gpioCfgInput(_ah, _gpio)
314 #define ath_hal_gpioGet(_ah, _gpio) \
315 AH_PRIVATE(_ah)->ah_gpioGet(_ah, _gpio)
316 #define ath_hal_gpioSet(_ah, _gpio, _val) \
317 AH_PRIVATE(_ah)->ah_gpioGet(_ah, _gpio, _val)
318 #define ath_hal_gpioSetIntr(_ah, _gpio, _ilevel) \
319 AH_PRIVATE(_ah)->ah_gpioSetIntr(_ah, _gpio, _ilevel)
320 #define ath_hal_getpowerlimits(_ah, _chans, _nchan) \
321 AH_PRIVATE(_ah)->ah_getChipPowerLimits(_ah, _chans, _nchan)
322 #define ath_hal_getNfAdjust(_ah, _c) \
323 AH_PRIVATE(_ah)->ah_getNfAdjust(_ah, _c)
324 #define ath_hal_getNoiseFloor(_ah, _nfArray) \
325 AH_PRIVATE(_ah)->ah_getNoiseFloor(_ah, _nfArray)
326
327 #define ath_hal_eepromDetach(_ah) \
328 AH_PRIVATE(_ah)->ah_eepromDetach(_ah)
329 #define ath_hal_eepromGet(_ah, _param, _val) \
330 AH_PRIVATE(_ah)->ah_eepromGet(_ah, _param, _val)
331 #define ath_hal_eepromSet(_ah, _param, _val) \
332 AH_PRIVATE(_ah)->ah_eepromSet(_ah, _param, _val)
333 #define ath_hal_eepromGetFlag(_ah, _param) \
334 (AH_PRIVATE(_ah)->ah_eepromGet(_ah, _param, AH_NULL) == HAL_OK)
335 #define ath_hal_getSpurChan(_ah, _ix, _is2G) \
336 AH_PRIVATE(_ah)->ah_getSpurChan(_ah, _ix, _is2G)
337 #define ath_hal_eepromDiag(_ah, _request, _a, _asize, _r, _rsize) \
338 AH_PRIVATE(_ah)->ah_eepromDiag(_ah, _request, _a, _asize, _r, _rsize)
339
340 #if !defined(_NET_IF_IEEE80211_H_) && !defined(_NET80211__IEEE80211_H_)
341 /*
342 * Stuff that would naturally come from _ieee80211.h
343 */
344 #define IEEE80211_ADDR_LEN 6
345
346 #define IEEE80211_WEP_KEYLEN 5 /* 40bit */
347 #define IEEE80211_WEP_IVLEN 3 /* 24bit */
348 #define IEEE80211_WEP_KIDLEN 1 /* 1 octet */
349 #define IEEE80211_WEP_CRCLEN 4 /* CRC-32 */
350
351 #define IEEE80211_CRC_LEN 4
352
353 #define IEEE80211_MTU 1500
354 #define IEEE80211_MAX_LEN (2300 + IEEE80211_CRC_LEN + \
355 (IEEE80211_WEP_IVLEN + IEEE80211_WEP_KIDLEN + IEEE80211_WEP_CRCLEN))
356
357 enum {
358 IEEE80211_T_DS, /* direct sequence spread spectrum */
359 IEEE80211_T_FH, /* frequency hopping */
360 IEEE80211_T_OFDM, /* frequency division multiplexing */
361 IEEE80211_T_TURBO, /* high rate DS */
362 IEEE80211_T_HT, /* HT - full GI */
363 };
364 #define IEEE80211_T_CCK IEEE80211_T_DS /* more common nomenclatur */
365 #endif /* _NET_IF_IEEE80211_H_ */
366
367 /* NB: these are defined privately until XR support is announced */
368 enum {
369 ATHEROS_T_XR = IEEE80211_T_HT+1, /* extended range */
370 };
371
372 #define HAL_TXQ_USE_LOCKOUT_BKOFF_DIS 0x00000001
373
374 #define INIT_AIFS 2
375 #define INIT_CWMIN 15
376 #define INIT_CWMIN_11B 31
377 #define INIT_CWMAX 1023
378 #define INIT_SH_RETRY 10
379 #define INIT_LG_RETRY 10
380 #define INIT_SSH_RETRY 32
381 #define INIT_SLG_RETRY 32
382
383 typedef struct {
384 uint32_t tqi_ver; /* HAL TXQ verson */
385 HAL_TX_QUEUE tqi_type; /* hw queue type*/
386 HAL_TX_QUEUE_SUBTYPE tqi_subtype; /* queue subtype, if applicable */
387 HAL_TX_QUEUE_FLAGS tqi_qflags; /* queue flags */
388 uint32_t tqi_priority;
389 uint32_t tqi_aifs; /* aifs */
390 uint32_t tqi_cwmin; /* cwMin */
391 uint32_t tqi_cwmax; /* cwMax */
392 uint16_t tqi_shretry; /* frame short retry limit */
393 uint16_t tqi_lgretry; /* frame long retry limit */
394 uint32_t tqi_cbrPeriod;
395 uint32_t tqi_cbrOverflowLimit;
396 uint32_t tqi_burstTime;
397 uint32_t tqi_readyTime;
398 uint32_t tqi_physCompBuf;
399 uint32_t tqi_intFlags; /* flags for internal use */
400 } HAL_TX_QUEUE_INFO;
401
402 extern HAL_BOOL ath_hal_setTxQProps(struct ath_hal *ah,
403 HAL_TX_QUEUE_INFO *qi, const HAL_TXQ_INFO *qInfo);
404 extern HAL_BOOL ath_hal_getTxQProps(struct ath_hal *ah,
405 HAL_TXQ_INFO *qInfo, const HAL_TX_QUEUE_INFO *qi);
406
407 typedef enum {
408 HAL_ANI_PRESENT, /* is ANI support present */
409 HAL_ANI_NOISE_IMMUNITY_LEVEL, /* set level */
410 HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION, /* enable/disable */
411 HAL_ANI_CCK_WEAK_SIGNAL_THR, /* enable/disable */
412 HAL_ANI_FIRSTEP_LEVEL, /* set level */
413 HAL_ANI_SPUR_IMMUNITY_LEVEL, /* set level */
414 HAL_ANI_MODE = 6, /* 0 => manual, 1 => auto (XXX do not change) */
415 HAL_ANI_PHYERR_RESET, /* reset phy error stats */
416 } HAL_ANI_CMD;
417
418 #define HAL_SPUR_VAL_MASK 0x3FFF
419 #define HAL_SPUR_CHAN_WIDTH 87
420 #define HAL_BIN_WIDTH_BASE_100HZ 3125
421 #define HAL_BIN_WIDTH_TURBO_100HZ 6250
422 #define HAL_MAX_BINS_ALLOWED 28
423
424 /*
425 * A = 5GHZ|OFDM
426 * T = 5GHZ|OFDM|TURBO
427 *
428 * IS_CHAN_A(T) will return TRUE. This is probably
429 * not the default behavior we want. We should migrate to a better mask --
430 * perhaps CHANNEL_ALL.
431 *
432 * For now, IS_CHAN_G() masks itself with CHANNEL_108G.
433 *
434 */
435
436 #define IS_CHAN_A(_c) (((_c)->channelFlags & CHANNEL_A) == CHANNEL_A)
437 #define IS_CHAN_B(_c) (((_c)->channelFlags & CHANNEL_B) == CHANNEL_B)
438 #define IS_CHAN_G(_c) (((_c)->channelFlags & (CHANNEL_108G|CHANNEL_G)) == CHANNEL_G)
439 #define IS_CHAN_108G(_c)(((_c)->channelFlags & CHANNEL_108G) == CHANNEL_108G)
440 #define IS_CHAN_T(_c) (((_c)->channelFlags & CHANNEL_T) == CHANNEL_T)
441 #define IS_CHAN_PUREG(_c) \
442 (((_c)->channelFlags & CHANNEL_PUREG) == CHANNEL_PUREG)
443
444 #define IS_CHAN_TURBO(_c) (((_c)->channelFlags & CHANNEL_TURBO) != 0)
445 #define IS_CHAN_CCK(_c) (((_c)->channelFlags & CHANNEL_CCK) != 0)
446 #define IS_CHAN_OFDM(_c) (((_c)->channelFlags & CHANNEL_OFDM) != 0)
447 #define IS_CHAN_5GHZ(_c) (((_c)->channelFlags & CHANNEL_5GHZ) != 0)
448 #define IS_CHAN_2GHZ(_c) (((_c)->channelFlags & CHANNEL_2GHZ) != 0)
449 #define IS_CHAN_PASSIVE(_c) (((_c)->channelFlags & CHANNEL_PASSIVE) != 0)
450 #define IS_CHAN_HALF_RATE(_c) (((_c)->channelFlags & CHANNEL_HALF) != 0)
451 #define IS_CHAN_QUARTER_RATE(_c) (((_c)->channelFlags & CHANNEL_QUARTER) != 0)
452
453 #define IS_CHAN_IN_PUBLIC_SAFETY_BAND(_c) ((_c) > 4940 && (_c) < 4990)
454
455 #define CHANNEL_HT40 (CHANNEL_HT40PLUS | CHANNEL_HT40MINUS)
456 #define CHANNEL_HT (CHANNEL_HT20 | CHANNEL_HT40)
457 #define IS_CHAN_HT(_c) (((_c)->channelFlags & CHANNEL_HT) != 0)
458 #define IS_CHAN_HT20(_c) (((_c)->channelFlags & CHANNEL_HT) == CHANNEL_HT20)
459 #define IS_CHAN_HT40(_c) (((_c)->channelFlags & CHANNEL_HT40) != 0)
460
461 /*
462 * Deduce if the host cpu has big- or litt-endian byte order.
463 */
464 static __inline__ int
465 isBigEndian(void)
466 {
467 union {
468 int32_t i;
469 char c[4];
470 } u;
471 u.i = 1;
472 return (u.c[0] == 0);
473 }
474
475 /* unalligned little endian access */
476 #define LE_READ_2(p) \
477 ((uint16_t) \
478 ((((const uint8_t *)(p))[0] ) | (((const uint8_t *)(p))[1]<< 8)))
479 #define LE_READ_4(p) \
480 ((uint32_t) \
481 ((((const uint8_t *)(p))[0] ) | (((const uint8_t *)(p))[1]<< 8) |\
482 (((const uint8_t *)(p))[2]<<16) | (((const uint8_t *)(p))[3]<<24)))
483
484 /*
485 * Register manipulation macros that expect bit field defines
486 * to follow the convention that an _S suffix is appended for
487 * a shift count, while the field mask has no suffix.
488 */
489 #define SM(_v, _f) (((_v) << _f##_S) & (_f))
490 #define MS(_v, _f) (((_v) & (_f)) >> _f##_S)
491 #define OS_REG_RMW_FIELD(_a, _r, _f, _v) \
492 OS_REG_WRITE(_a, _r, \
493 (OS_REG_READ(_a, _r) &~ (_f)) | (((_v) << _f##_S) & (_f)))
494 #define OS_REG_SET_BIT(_a, _r, _f) \
495 OS_REG_WRITE(_a, _r, OS_REG_READ(_a, _r) | (_f))
496 #define OS_REG_CLR_BIT(_a, _r, _f) \
497 OS_REG_WRITE(_a, _r, OS_REG_READ(_a, _r) &~ (_f))
498
499 /*
500 * Regulatory domain support.
501 */
502
503 /*
504 * Return the max allowed antenna gain based on the current
505 * regulatory domain.
506 */
507 extern u_int ath_hal_getantennareduction(struct ath_hal *,
508 HAL_CHANNEL *, u_int twiceGain);
509 /*
510 * Return the test group for the specific channel based on
511 * the current regulator domain.
512 */
513 extern u_int ath_hal_getctl(struct ath_hal *, HAL_CHANNEL *);
514 /*
515 * Return whether or not a noise floor check is required
516 * based on the current regulatory domain for the specified
517 * channel.
518 */
519 extern HAL_BOOL ath_hal_getnfcheckrequired(struct ath_hal *, HAL_CHANNEL *);
520
521 /*
522 * Map a public channel definition to the corresponding
523 * internal data structure. This implicitly specifies
524 * whether or not the specified channel is ok to use
525 * based on the current regulatory domain constraints.
526 */
527 extern HAL_CHANNEL_INTERNAL *ath_hal_checkchannel(struct ath_hal *,
528 const HAL_CHANNEL *);
529
530 /* system-configurable parameters */
531 extern int ath_hal_dma_beacon_response_time; /* in TU's */
532 extern int ath_hal_sw_beacon_response_time; /* in TU's */
533 extern int ath_hal_additional_swba_backoff; /* in TU's */
534
535 /* wait for the register contents to have the specified value */
536 extern HAL_BOOL ath_hal_wait(struct ath_hal *, u_int reg,
537 uint32_t mask, uint32_t val);
538
539 /* return the first n bits in val reversed */
540 extern uint32_t ath_hal_reverseBits(uint32_t val, uint32_t n);
541
542 /* printf interfaces */
543 extern void ath_hal_printf(struct ath_hal *, const char*, ...)
544 __printflike(2,3);
545 extern void ath_hal_vprintf(struct ath_hal *, const char*, va_list)
546 __printflike(2, 0);
547 extern const char* ath_hal_ether_sprintf(const uint8_t *mac);
548
549 /* allocate and free memory */
550 extern void *ath_hal_malloc(size_t);
551 extern void ath_hal_free(void *);
552
553 /* common debugging interfaces */
554 #ifdef AH_DEBUG
555 #include "ah_debug.h"
556 extern int ath_hal_debug;
557 extern void HALDEBUG(struct ath_hal *ah, u_int mask, const char* fmt, ...)
558 __printflike(3,4);
559 #else
560 #define HALDEBUG(_ah, __m, _fmt, ...)
561 #endif /* AH_DEBUG */
562
563 /*
564 * Register logging definitions shared with ardecode.
565 */
566 #include "ah_decode.h"
567
568 /*
569 * Common assertion interface. Note: it is a bad idea to generate
570 * an assertion failure for any recoverable event. Instead catch
571 * the violation and, if possible, fix it up or recover from it; either
572 * with an error return value or a diagnostic messages. System software
573 * does not panic unless the situation is hopeless.
574 */
575 #ifdef AH_ASSERT
576 extern void ath_hal_assert_failed(const char* filename,
577 int lineno, const char* msg);
578
579 #define HALASSERT(_x) do { \
580 if (!(_x)) { \
581 ath_hal_assert_failed(__FILE__, __LINE__, #_x); \
582 } \
583 } while (0)
584 #else
585 #define HALASSERT(_x)
586 #endif /* AH_ASSERT */
587
588 /*
589 * Convert between microseconds and core system clocks.
590 */
591 extern u_int ath_hal_mac_clks(struct ath_hal *ah, u_int usecs);
592 extern u_int ath_hal_mac_usec(struct ath_hal *ah, u_int clks);
593
594 /*
595 * Generic get/set capability support. Each chip overrides
596 * this routine to support chip-specific capabilities.
597 */
598 extern HAL_STATUS ath_hal_getcapability(struct ath_hal *ah,
599 HAL_CAPABILITY_TYPE type, uint32_t capability,
600 uint32_t *result);
601 extern HAL_BOOL ath_hal_setcapability(struct ath_hal *ah,
602 HAL_CAPABILITY_TYPE type, uint32_t capability,
603 uint32_t setting, HAL_STATUS *status);
604
605 /*
606 * Diagnostic interface. This is an open-ended interface that
607 * is opaque to applications. Diagnostic programs use this to
608 * retrieve internal data structures, etc. There is no guarantee
609 * that calling conventions for calls other than HAL_DIAG_REVS
610 * are stable between HAL releases; a diagnostic application must
611 * use the HAL revision information to deal with ABI/API differences.
612 *
613 * NB: do not renumber these, certain codes are publicly used.
614 */
615 enum {
616 HAL_DIAG_REVS = 0, /* MAC/PHY/Radio revs */
617 HAL_DIAG_EEPROM = 1, /* EEPROM contents */
618 HAL_DIAG_EEPROM_EXP_11A = 2, /* EEPROM 5112 power exp for 11a */
619 HAL_DIAG_EEPROM_EXP_11B = 3, /* EEPROM 5112 power exp for 11b */
620 HAL_DIAG_EEPROM_EXP_11G = 4, /* EEPROM 5112 power exp for 11g */
621 HAL_DIAG_ANI_CURRENT = 5, /* ANI current channel state */
622 HAL_DIAG_ANI_OFDM = 6, /* ANI OFDM timing error stats */
623 HAL_DIAG_ANI_CCK = 7, /* ANI CCK timing error stats */
624 HAL_DIAG_ANI_STATS = 8, /* ANI statistics */
625 HAL_DIAG_RFGAIN = 9, /* RfGain GAIN_VALUES */
626 HAL_DIAG_RFGAIN_CURSTEP = 10, /* RfGain GAIN_OPTIMIZATION_STEP */
627 HAL_DIAG_PCDAC = 11, /* PCDAC table */
628 HAL_DIAG_TXRATES = 12, /* Transmit rate table */
629 HAL_DIAG_REGS = 13, /* Registers */
630 HAL_DIAG_ANI_CMD = 14, /* ANI issue command (XXX do not change!) */
631 HAL_DIAG_SETKEY = 15, /* Set keycache backdoor */
632 HAL_DIAG_RESETKEY = 16, /* Reset keycache backdoor */
633 HAL_DIAG_EEREAD = 17, /* Read EEPROM word */
634 HAL_DIAG_EEWRITE = 18, /* Write EEPROM word */
635 /* 19 was HAL_DIAG_TXCONT, 20-23 were for radar */
636 HAL_DIAG_REGREAD = 24, /* Reg reads */
637 HAL_DIAG_REGWRITE = 25, /* Reg writes */
638 HAL_DIAG_GET_REGBASE = 26, /* Get register base */
639 HAL_DIAG_RDWRITE = 27, /* Write regulatory domain */
640 HAL_DIAG_RDREAD = 28, /* Get regulatory domain */
641 HAL_DIAG_FATALERR = 29, /* Read cached interrupt state */
642 HAL_DIAG_11NCOMPAT = 30, /* 11n compatibility tweaks */
643 HAL_DIAG_ANI_PARAMS = 31, /* ANI noise immunity parameters */
644 HAL_DIAG_CHECK_HANGS = 32, /* check h/w hangs */
645 };
646
647 enum {
648 HAL_BB_HANG_DFS = 0x0001,
649 HAL_BB_HANG_RIFS = 0x0002,
650 HAL_BB_HANG_RX_CLEAR = 0x0004,
651 HAL_BB_HANG_UNKNOWN = 0x0080,
652
653 HAL_MAC_HANG_SIG1 = 0x0100,
654 HAL_MAC_HANG_SIG2 = 0x0200,
655 HAL_MAC_HANG_UNKNOWN = 0x8000,
656
657 HAL_BB_HANGS = HAL_BB_HANG_DFS
658 | HAL_BB_HANG_RIFS
659 | HAL_BB_HANG_RX_CLEAR
660 | HAL_BB_HANG_UNKNOWN,
661 HAL_MAC_HANGS = HAL_MAC_HANG_SIG1
662 | HAL_MAC_HANG_SIG2
663 | HAL_MAC_HANG_UNKNOWN,
664 };
665
666 /*
667 * Device revision information.
668 */
669 typedef struct {
670 uint16_t ah_devid; /* PCI device ID */
671 uint16_t ah_subvendorid; /* PCI subvendor ID */
672 uint32_t ah_macVersion; /* MAC version id */
673 uint16_t ah_macRev; /* MAC revision */
674 uint16_t ah_phyRev; /* PHY revision */
675 uint16_t ah_analog5GhzRev; /* 2GHz radio revision */
676 uint16_t ah_analog2GhzRev; /* 5GHz radio revision */
677 } HAL_REVS;
678
679 /*
680 * Argument payload for HAL_DIAG_SETKEY.
681 */
682 typedef struct {
683 HAL_KEYVAL dk_keyval;
684 uint16_t dk_keyix; /* key index */
685 uint8_t dk_mac[IEEE80211_ADDR_LEN];
686 int dk_xor; /* XOR key data */
687 } HAL_DIAG_KEYVAL;
688
689 /*
690 * Argument payload for HAL_DIAG_EEWRITE.
691 */
692 typedef struct {
693 uint16_t ee_off; /* eeprom offset */
694 uint16_t ee_data; /* write data */
695 } HAL_DIAG_EEVAL;
696
697
698 typedef struct {
699 u_int offset; /* reg offset */
700 uint32_t val; /* reg value */
701 } HAL_DIAG_REGVAL;
702
703 /*
704 * 11n compatibility tweaks.
705 */
706 #define HAL_DIAG_11N_SERVICES 0x00000003
707 #define HAL_DIAG_11N_SERVICES_S 0
708 #define HAL_DIAG_11N_TXSTOMP 0x0000000c
709 #define HAL_DIAG_11N_TXSTOMP_S 2
710
711 typedef struct {
712 int maxNoiseImmunityLevel; /* [0..4] */
713 int totalSizeDesired[5];
714 int coarseHigh[5];
715 int coarseLow[5];
716 int firpwr[5];
717
718 int maxSpurImmunityLevel; /* [0..7] */
719 int cycPwrThr1[8];
720
721 int maxFirstepLevel; /* [0..2] */
722 int firstep[3];
723
724 uint32_t ofdmTrigHigh;
725 uint32_t ofdmTrigLow;
726 int32_t cckTrigHigh;
727 int32_t cckTrigLow;
728 int32_t rssiThrLow;
729 int32_t rssiThrHigh;
730
731 int period; /* update listen period */
732 } HAL_ANI_PARAMS;
733
734 extern HAL_BOOL ath_hal_getdiagstate(struct ath_hal *ah, int request,
735 const void *args, uint32_t argsize,
736 void **result, uint32_t *resultsize);
737
738 /*
739 * Setup a h/w rate table for use.
740 */
741 extern void ath_hal_setupratetable(struct ath_hal *ah, HAL_RATE_TABLE *rt);
742
743 /*
744 * Common routine for implementing getChanNoise api.
745 */
746 extern int16_t ath_hal_getChanNoise(struct ath_hal *ah, HAL_CHANNEL *chan);
747
748 /*
749 * Initialization support.
750 */
751 typedef struct {
752 const uint32_t *data;
753 int rows, cols;
754 } HAL_INI_ARRAY;
755
756 #define HAL_INI_INIT(_ia, _data, _cols) do { \
757 (_ia)->data = (const uint32_t *)(_data); \
758 (_ia)->rows = sizeof(_data) / sizeof((_data)[0]); \
759 (_ia)->cols = (_cols); \
760 } while (0)
761 #define HAL_INI_VAL(_ia, _r, _c) \
762 ((_ia)->data[((_r)*(_ia)->cols) + (_c)])
763
764 /*
765 * OS_DELAY() does a PIO READ on the PCI bus which allows
766 * other cards' DMA reads to complete in the middle of our reset.
767 */
768 #define DMA_YIELD(x) do { \
769 if ((++(x) % 64) == 0) \
770 OS_DELAY(1); \
771 } while (0)
772
773 #define HAL_INI_WRITE_ARRAY(ah, regArray, col, regWr) do { \
774 int r; \
775 for (r = 0; r < N(regArray); r++) { \
776 OS_REG_WRITE(ah, (regArray)[r][0], (regArray)[r][col]); \
777 DMA_YIELD(regWr); \
778 } \
779 } while (0)
780
781 #define HAL_INI_WRITE_BANK(ah, regArray, bankData, regWr) do { \
782 int r; \
783 for (r = 0; r < N(regArray); r++) { \
784 OS_REG_WRITE(ah, (regArray)[r][0], (bankData)[r]); \
785 DMA_YIELD(regWr); \
786 } \
787 } while (0)
788
789 extern int ath_hal_ini_write(struct ath_hal *ah, const HAL_INI_ARRAY *ia,
790 int col, int regWr);
791 extern void ath_hal_ini_bank_setup(uint32_t data[], const HAL_INI_ARRAY *ia,
792 int col);
793 extern int ath_hal_ini_bank_write(struct ath_hal *ah, const HAL_INI_ARRAY *ia,
794 const uint32_t data[], int regWr);
795
796 #define WLAN_CTRL_FRAME_SIZE (2+2+6+4) /* ACK+FCS */
797 #endif /* _ATH_AH_INTERAL_H_ */
NetBSD on the FriendlyARM MINI2440