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[netbsd-mini2440.git] / sys / external / isc / atheros_hal / dist / ar5212 / ar5212.h
blob2d63eb28efaffe124ff4951e886025e84a629c69
1 /*
2 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
3 * Copyright (c) 2002-2008 Atheros Communications, Inc.
4 *
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 *
17 * $Id: ar5212.h,v 1.1.1.1 2008/12/11 04:46:38 alc Exp $
18 */
19 #ifndef _ATH_AR5212_H_
20 #define _ATH_AR5212_H_
21
22 #include "ah_eeprom.h"
23
24 #define AR5212_MAGIC 0x19541014
25
26 /* DCU Transmit Filter macros */
27 #define CALC_MMR(dcu, idx) \
28 ( (4 * dcu) + (idx < 32 ? 0 : (idx < 64 ? 1 : (idx < 96 ? 2 : 3))) )
29 #define TXBLK_FROM_MMR(mmr) \
30 (AR_D_TXBLK_BASE + ((mmr & 0x1f) << 6) + ((mmr & 0x20) >> 3))
31 #define CALC_TXBLK_ADDR(dcu, idx) (TXBLK_FROM_MMR(CALC_MMR(dcu, idx)))
32 #define CALC_TXBLK_VALUE(idx) (1 << (idx & 0x1f))
33
34 /* MAC register values */
35
36 #define INIT_INTERRUPT_MASK \
37 ( AR_IMR_TXERR | AR_IMR_TXOK | AR_IMR_RXORN | \
38 AR_IMR_RXERR | AR_IMR_RXOK | AR_IMR_TXURN | \
39 AR_IMR_HIUERR )
40 #define INIT_BEACON_CONTROL \
41 ((INIT_RESET_TSF << 24) | (INIT_BEACON_EN << 23) | \
42 (INIT_TIM_OFFSET << 16) | INIT_BEACON_PERIOD)
43
44 #define INIT_CONFIG_STATUS 0x00000000
45 #define INIT_RSSI_THR 0x00000781 /* Missed beacon counter initialized to 0x7 (max is 0xff) */
46 #define INIT_IQCAL_LOG_COUNT_MAX 0xF
47 #define INIT_BCON_CNTRL_REG 0x00000000
48
49 #define INIT_USEC 40
50 #define HALF_RATE_USEC 19 /* ((40 / 2) - 1 ) */
51 #define QUARTER_RATE_USEC 9 /* ((40 / 4) - 1 ) */
52
53 #define RX_NON_FULL_RATE_LATENCY 63
54 #define TX_HALF_RATE_LATENCY 108
55 #define TX_QUARTER_RATE_LATENCY 216
56
57 #define IFS_SLOT_FULL_RATE 0x168 /* 9 us half, 40 MHz core clock (9*40) */
58 #define IFS_SLOT_HALF_RATE 0x104 /* 13 us half, 20 MHz core clock (13*20) */
59 #define IFS_SLOT_QUARTER_RATE 0xD2 /* 21 us quarter, 10 MHz core clock (21*10) */
60 #define IFS_EIFS_FULL_RATE 0xE60 /* (74 + (2 * 9)) * 40MHz core clock */
61 #define IFS_EIFS_HALF_RATE 0xDAC /* (149 + (2 * 13)) * 20MHz core clock */
62 #define IFS_EIFS_QUARTER_RATE 0xD48 /* (298 + (2 * 21)) * 10MHz core clock */
63
64 #define ACK_CTS_TIMEOUT_11A 0x3E8 /* ACK timeout in 11a core clocks */
65
66 /* Tx frame start to tx data start delay */
67 #define TX_FRAME_D_START_HALF_RATE 0xc
68 #define TX_FRAME_D_START_QUARTER_RATE 0xd
69
70 /*
71 * Various fifo fill before Tx start, in 64-byte units
72 * i.e. put the frame in the air while still DMAing
73 */
74 #define MIN_TX_FIFO_THRESHOLD 0x1
75 #define MAX_TX_FIFO_THRESHOLD ((IEEE80211_MAX_LEN / 64) + 1)
76 #define INIT_TX_FIFO_THRESHOLD MIN_TX_FIFO_THRESHOLD
77
78 #define HAL_DECOMP_MASK_SIZE 128 /* 1 byte per key */
79
80 /*
81 * Gain support.
82 */
83 #define NUM_CORNER_FIX_BITS 4
84 #define NUM_CORNER_FIX_BITS_5112 7
85 #define DYN_ADJ_UP_MARGIN 15
86 #define DYN_ADJ_LO_MARGIN 20
87 #define PHY_PROBE_CCK_CORRECTION 5
88 #define CCK_OFDM_GAIN_DELTA 15
89
90 enum GAIN_PARAMS {
91 GP_TXCLIP,
92 GP_PD90,
93 GP_PD84,
94 GP_GSEL,
95 };
96
97 enum GAIN_PARAMS_5112 {
98 GP_MIXGAIN_OVR,
99 GP_PWD_138,
100 GP_PWD_137,
101 GP_PWD_136,
102 GP_PWD_132,
103 GP_PWD_131,
104 GP_PWD_130,
105 };
106
107 typedef struct _gainOptStep {
108 int16_t paramVal[NUM_CORNER_FIX_BITS_5112];
109 int32_t stepGain;
110 int8_t stepName[16];
111 } GAIN_OPTIMIZATION_STEP;
112
113 typedef struct {
114 uint32_t numStepsInLadder;
115 uint32_t defaultStepNum;
116 GAIN_OPTIMIZATION_STEP optStep[10];
117 } GAIN_OPTIMIZATION_LADDER;
118
119 typedef struct {
120 uint32_t currStepNum;
121 uint32_t currGain;
122 uint32_t targetGain;
123 uint32_t loTrig;
124 uint32_t hiTrig;
125 uint32_t gainFCorrection;
126 uint32_t active;
127 const GAIN_OPTIMIZATION_STEP *currStep;
128 } GAIN_VALUES;
129
130 /* RF HAL structures */
131 typedef struct RfHalFuncs {
132 void *priv; /* private state */
133
134 void (*rfDetach)(struct ath_hal *ah);
135 void (*writeRegs)(struct ath_hal *,
136 u_int modeIndex, u_int freqIndex, int regWrites);
137 uint32_t *(*getRfBank)(struct ath_hal *ah, int bank);
138 HAL_BOOL (*setChannel)(struct ath_hal *, HAL_CHANNEL_INTERNAL *);
139 HAL_BOOL (*setRfRegs)(struct ath_hal *,
140 HAL_CHANNEL_INTERNAL *, uint16_t modesIndex,
141 uint16_t *rfXpdGain);
142 HAL_BOOL (*setPowerTable)(struct ath_hal *ah,
143 int16_t *minPower, int16_t *maxPower,
144 HAL_CHANNEL_INTERNAL *, uint16_t *rfXpdGain);
145 HAL_BOOL (*getChannelMaxMinPower)(struct ath_hal *ah, HAL_CHANNEL *,
146 int16_t *maxPow, int16_t *minPow);
147 int16_t (*getNfAdjust)(struct ath_hal *, const HAL_CHANNEL_INTERNAL*);
148 } RF_HAL_FUNCS;
149
150 struct ar5212AniParams {
151 int maxNoiseImmunityLevel; /* [0..4] */
152 int totalSizeDesired[5];
153 int coarseHigh[5];
154 int coarseLow[5];
155 int firpwr[5];
156
157 int maxSpurImmunityLevel; /* [0..7] */
158 int cycPwrThr1[8];
159
160 int maxFirstepLevel; /* [0..2] */
161 int firstep[3];
162
163 uint32_t ofdmTrigHigh;
164 uint32_t ofdmTrigLow;
165 uint32_t cckTrigHigh;
166 uint32_t cckTrigLow;
167 int32_t rssiThrLow;
168 uint32_t rssiThrHigh;
169
170 int period; /* update listen period */
171
172 /* NB: intentionally ordered so data exported to user space is first */
173 uint32_t ofdmPhyErrBase; /* Base value for ofdm err counter */
174 uint32_t cckPhyErrBase; /* Base value for cck err counters */
175 };
176
177 /*
178 * Per-channel ANI state private to the driver.
179 */
180 struct ar5212AniState {
181 uint8_t noiseImmunityLevel;
182 uint8_t spurImmunityLevel;
183 uint8_t firstepLevel;
184 uint8_t ofdmWeakSigDetectOff;
185 uint8_t cckWeakSigThreshold;
186 uint32_t listenTime;
187
188 /* NB: intentionally ordered so data exported to user space is first */
189 HAL_CHANNEL c;
190 HAL_BOOL isSetup; /* has state to do a restore */
191 uint32_t txFrameCount; /* Last txFrameCount */
192 uint32_t rxFrameCount; /* Last rx Frame count */
193 uint32_t cycleCount; /* Last cycleCount
194 (to detect wrap-around) */
195 uint32_t ofdmPhyErrCount;/* OFDM err count since last reset */
196 uint32_t cckPhyErrCount; /* CCK err count since last reset */
197
198 const struct ar5212AniParams *params;
199 };
200
201 #define HAL_ANI_ENA 0x00000001 /* ANI operation enabled */
202 #define HAL_RSSI_ANI_ENA 0x00000002 /* rssi-based processing ena'd*/
203
204 struct ar5212Stats {
205 uint32_t ast_ani_niup; /* ANI increased noise immunity */
206 uint32_t ast_ani_nidown; /* ANI decreased noise immunity */
207 uint32_t ast_ani_spurup; /* ANI increased spur immunity */
208 uint32_t ast_ani_spurdown;/* ANI descreased spur immunity */
209 uint32_t ast_ani_ofdmon; /* ANI OFDM weak signal detect on */
210 uint32_t ast_ani_ofdmoff;/* ANI OFDM weak signal detect off */
211 uint32_t ast_ani_cckhigh;/* ANI CCK weak signal threshold high */
212 uint32_t ast_ani_ccklow; /* ANI CCK weak signal threshold low */
213 uint32_t ast_ani_stepup; /* ANI increased first step level */
214 uint32_t ast_ani_stepdown;/* ANI decreased first step level */
215 uint32_t ast_ani_ofdmerrs;/* ANI cumulative ofdm phy err count */
216 uint32_t ast_ani_cckerrs;/* ANI cumulative cck phy err count */
217 uint32_t ast_ani_reset; /* ANI parameters zero'd for non-STA */
218 uint32_t ast_ani_lzero; /* ANI listen time forced to zero */
219 uint32_t ast_ani_lneg; /* ANI listen time calculated < 0 */
220 HAL_MIB_STATS ast_mibstats; /* MIB counter stats */
221 HAL_NODE_STATS ast_nodestats; /* Latest rssi stats from driver */
222 };
223
224 /*
225 * NF Cal history buffer
226 */
227 #define AR5212_CCA_MAX_GOOD_VALUE -95
228 #define AR5212_CCA_MAX_HIGH_VALUE -62
229 #define AR5212_CCA_MIN_BAD_VALUE -125
230
231 #define AR512_NF_CAL_HIST_MAX 5
232
233 struct ar5212NfCalHist {
234 int16_t nfCalBuffer[AR512_NF_CAL_HIST_MAX];
235 int16_t privNF;
236 uint8_t currIndex;
237 uint8_t first_run;
238 uint8_t invalidNFcount;
239 };
240
241 struct ath_hal_5212 {
242 struct ath_hal_private ah_priv; /* base class */
243
244 /*
245 * Per-chip common Initialization data.
246 * NB: RF backends have their own ini data.
247 */
248 HAL_INI_ARRAY ah_ini_modes;
249 HAL_INI_ARRAY ah_ini_common;
250
251 GAIN_VALUES ah_gainValues;
252
253 uint8_t ah_macaddr[IEEE80211_ADDR_LEN];
254 uint8_t ah_bssid[IEEE80211_ADDR_LEN];
255 uint8_t ah_bssidmask[IEEE80211_ADDR_LEN];
256
257 /*
258 * Runtime state.
259 */
260 uint32_t ah_maskReg; /* copy of AR_IMR */
261 struct ar5212Stats ah_stats; /* various statistics */
262 RF_HAL_FUNCS *ah_rfHal;
263 uint32_t ah_txDescMask; /* mask for TXDESC */
264 uint32_t ah_txOkInterruptMask;
265 uint32_t ah_txErrInterruptMask;
266 uint32_t ah_txDescInterruptMask;
267 uint32_t ah_txEolInterruptMask;
268 uint32_t ah_txUrnInterruptMask;
269 HAL_TX_QUEUE_INFO ah_txq[HAL_NUM_TX_QUEUES];
270 uint32_t ah_intrTxqs; /* tx q interrupt state */
271 /* decomp mask array */
272 uint8_t ah_decompMask[HAL_DECOMP_MASK_SIZE];
273 HAL_POWER_MODE ah_powerMode;
274 HAL_ANT_SETTING ah_antControl; /* antenna setting */
275 HAL_BOOL ah_diversity; /* fast diversity setting */
276 enum {
277 IQ_CAL_INACTIVE,
278 IQ_CAL_RUNNING,
279 IQ_CAL_DONE
280 } ah_bIQCalibration; /* IQ calibrate state */
281 HAL_RFGAIN ah_rfgainState; /* RF gain calibrartion state */
282 uint32_t ah_tx6PowerInHalfDbm; /* power output for 6Mb tx */
283 uint32_t ah_staId1Defaults; /* STA_ID1 default settings */
284 uint32_t ah_miscMode; /* MISC_MODE settings */
285 uint32_t ah_rssiThr; /* RSSI_THR settings */
286 HAL_BOOL ah_cwCalRequire; /* for ap51 */
287 HAL_BOOL ah_tpcEnabled; /* per-packet tpc enabled */
288 HAL_BOOL ah_phyPowerOn; /* PHY power state */
289 HAL_BOOL ah_isHb63; /* cached HB63 check */
290 uint32_t ah_macTPC; /* tpc register */
291 uint32_t ah_beaconInterval; /* XXX */
292 enum {
293 AUTO_32KHZ, /* use it if 32kHz crystal present */
294 USE_32KHZ, /* do it regardless */
295 DONT_USE_32KHZ, /* don't use it regardless */
296 } ah_enable32kHzClock; /* whether to sleep at 32kHz */
297 uint32_t ah_ofdmTxPower;
298 int16_t ah_txPowerIndexOffset;
299 /*
300 * Noise floor cal histogram support.
301 */
302 struct ar5212NfCalHist ah_nfCalHist;
303
304 u_int ah_slottime; /* user-specified slot time */
305 u_int ah_acktimeout; /* user-specified ack timeout */
306 u_int ah_ctstimeout; /* user-specified cts timeout */
307 u_int ah_sifstime; /* user-specified sifs time */
308 /*
309 * RF Silent handling; setup according to the EEPROM.
310 */
311 uint32_t ah_gpioSelect; /* GPIO pin to use */
312 uint32_t ah_polarity; /* polarity to disable RF */
313 uint32_t ah_gpioBit; /* after init, prev value */
314 /*
315 * ANI support.
316 */
317 uint32_t ah_procPhyErr; /* Process Phy errs */
318 HAL_BOOL ah_hasHwPhyCounters; /* Hardware has phy counters */
319 struct ar5212AniParams ah_aniParams24; /* 2.4GHz parameters */
320 struct ar5212AniParams ah_aniParams5; /* 5GHz parameters */
321 struct ar5212AniState *ah_curani; /* cached last reference */
322 struct ar5212AniState ah_ani[64]; /* per-channel state */
323
324 /*
325 * Transmit power state. Note these are maintained
326 * here so they can be retrieved by diagnostic tools.
327 */
328 uint16_t *ah_pcdacTable;
329 u_int ah_pcdacTableSize;
330 uint16_t ah_ratesArray[16];
331 };
332 #define AH5212(_ah) ((struct ath_hal_5212 *)(_ah))
333
334 /*
335 * IS_XXXX macros test the MAC version
336 * IS_RADXXX macros test the radio/RF version (matching both 2G-only and 2/5G)
337 *
338 * Some single chip radios have equivalent radio/RF (e.g. 5112)
339 * for those use IS_RADXXX_ANY macros.
340 */
341 #define IS_2317(ah) \
342 ((AH_PRIVATE(ah)->ah_devid == AR5212_AR2317_REV1) || \
343 (AH_PRIVATE(ah)->ah_devid == AR5212_AR2317_REV2))
344 #define IS_2316(ah) \
345 (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_2415)
346 #define IS_2413(ah) \
347 (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_2413 || IS_2316(ah))
348 #define IS_5424(ah) \
349 (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_5424 || \
350 (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_5413 && \
351 AH_PRIVATE(ah)->ah_macRev <= AR_SREV_D2PLUS_MS))
352 #define IS_5413(ah) \
353 (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_5413 || IS_5424(ah))
354 #define IS_2425(ah) \
355 (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_2425)
356 #define IS_2417(ah) \
357 ((AH_PRIVATE(ah)->ah_macVersion) == AR_SREV_2417)
358 #define IS_HB63(ah) (AH5212(ah)->ah_isHb63 == AH_TRUE)
359
360 #define IS_PCIE(ah) (IS_5424(ah) || IS_2425(ah))
361
362 #define AH_RADIO_MAJOR(ah) \
363 (AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR)
364 #define AH_RADIO_MINOR(ah) \
365 (AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MINOR)
366 #define IS_RAD5111(ah) \
367 (AH_RADIO_MAJOR(ah) == AR_RAD5111_SREV_MAJOR || \
368 AH_RADIO_MAJOR(ah) == AR_RAD2111_SREV_MAJOR)
369 #define IS_RAD5112(ah) \
370 (AH_RADIO_MAJOR(ah) == AR_RAD5112_SREV_MAJOR || \
371 AH_RADIO_MAJOR(ah) == AR_RAD2112_SREV_MAJOR)
372 /* NB: does not include 5413 as Atheros' IS_5112 macro does */
373 #define IS_RAD5112_ANY(ah) \
374 (AR_RAD5112_SREV_MAJOR <= AH_RADIO_MAJOR(ah) && \
375 AH_RADIO_MAJOR(ah) <= AR_RAD2413_SREV_MAJOR)
376 #define IS_RAD5112_REV1(ah) \
377 (IS_RAD5112(ah) && \
378 AH_RADIO_MINOR(ah) < (AR_RAD5112_SREV_2_0 & AR_RADIO_SREV_MINOR))
379 #define IS_RADX112_REV2(ah) \
380 (AH_PRIVATE(ah)->ah_analog5GhzRev == AR_RAD5112_SREV_2_0 || \
381 AH_PRIVATE(ah)->ah_analog5GhzRev == AR_RAD2112_SREV_2_0 || \
382 AH_PRIVATE(ah)->ah_analog5GhzRev == AR_RAD2112_SREV_2_1 || \
383 AH_PRIVATE(ah)->ah_analog5GhzRev == AR_RAD5112_SREV_2_1)
384
385 #define ar5212RfDetach(ah) do { \
386 if (AH5212(ah)->ah_rfHal != AH_NULL) \
387 AH5212(ah)->ah_rfHal->rfDetach(ah); \
388 } while (0)
389 #define ar5212GetRfBank(ah, b) \
390 AH5212(ah)->ah_rfHal->getRfBank(ah, b)
391
392 /*
393 * Hack macros for Nala/San: 11b is handled
394 * using 11g; flip the channel flags to accomplish this.
395 */
396 #define SAVE_CCK(_ah, _chan, _flag) do { \
397 if ((IS_2425(_ah) || IS_2417(_ah)) && \
398 (((_chan)->channelFlags) & CHANNEL_CCK)) { \
399 (_chan)->channelFlags &= ~CHANNEL_CCK; \
400 (_chan)->channelFlags |= CHANNEL_OFDM; \
401 (_flag) = AH_TRUE; \
402 } \
403 } while (0)
404 #define RESTORE_CCK(_ah, _chan, _flag) do { \
405 if ((IS_2425(_ah) || IS_2417(_ah)) && (_flag) == AH_TRUE) {\
406 (_chan)->channelFlags &= ~CHANNEL_OFDM; \
407 (_chan)->channelFlags |= CHANNEL_CCK; \
408 } \
409 } while (0)
410
411 struct ath_hal;
412
413 extern uint32_t ar5212GetRadioRev(struct ath_hal *ah);
414 extern void ar5212InitState(struct ath_hal_5212 *, uint16_t devid, HAL_SOFTC,
415 HAL_BUS_TAG st, HAL_BUS_HANDLE sh, HAL_STATUS *status);
416 extern void ar5212Detach(struct ath_hal *ah);
417 extern HAL_BOOL ar5212ChipTest(struct ath_hal *ah);
418 extern HAL_BOOL ar5212GetChannelEdges(struct ath_hal *ah,
419 uint16_t flags, uint16_t *low, uint16_t *high);
420 extern HAL_BOOL ar5212FillCapabilityInfo(struct ath_hal *ah);
421
422 extern void ar5212SetBeaconTimers(struct ath_hal *ah,
423 const HAL_BEACON_TIMERS *);
424 extern void ar5212BeaconInit(struct ath_hal *ah,
425 uint32_t next_beacon, uint32_t beacon_period);
426 extern void ar5212ResetStaBeaconTimers(struct ath_hal *ah);
427 extern void ar5212SetStaBeaconTimers(struct ath_hal *ah,
428 const HAL_BEACON_STATE *);
429
430 extern HAL_BOOL ar5212IsInterruptPending(struct ath_hal *ah);
431 extern HAL_BOOL ar5212GetPendingInterrupts(struct ath_hal *ah, HAL_INT *);
432 extern HAL_INT ar5212GetInterrupts(struct ath_hal *ah);
433 extern HAL_INT ar5212SetInterrupts(struct ath_hal *ah, HAL_INT ints);
434
435 extern uint32_t ar5212GetKeyCacheSize(struct ath_hal *);
436 extern HAL_BOOL ar5212IsKeyCacheEntryValid(struct ath_hal *, uint16_t entry);
437 extern HAL_BOOL ar5212ResetKeyCacheEntry(struct ath_hal *ah, uint16_t entry);
438 extern HAL_BOOL ar5212SetKeyCacheEntryMac(struct ath_hal *,
439 uint16_t entry, const uint8_t *mac);
440 extern HAL_BOOL ar5212SetKeyCacheEntry(struct ath_hal *ah, uint16_t entry,
441 const HAL_KEYVAL *k, const uint8_t *mac, int xorKey);
442
443 extern void ar5212GetMacAddress(struct ath_hal *ah, uint8_t *mac);
444 extern HAL_BOOL ar5212SetMacAddress(struct ath_hal *ah, const uint8_t *);
445 extern void ar5212GetBssIdMask(struct ath_hal *ah, uint8_t *mac);
446 extern HAL_BOOL ar5212SetBssIdMask(struct ath_hal *, const uint8_t *);
447 extern HAL_BOOL ar5212EepromRead(struct ath_hal *, u_int off, uint16_t *data);
448 extern HAL_BOOL ar5212EepromWrite(struct ath_hal *, u_int off, uint16_t data);
449 extern HAL_BOOL ar5212SetRegulatoryDomain(struct ath_hal *ah,
450 uint16_t regDomain, HAL_STATUS *stats);
451 extern u_int ar5212GetWirelessModes(struct ath_hal *ah);
452 extern void ar5212EnableRfKill(struct ath_hal *);
453 extern HAL_BOOL ar5212GpioCfgOutput(struct ath_hal *, uint32_t gpio);
454 extern HAL_BOOL ar5212GpioCfgInput(struct ath_hal *, uint32_t gpio);
455 extern HAL_BOOL ar5212GpioSet(struct ath_hal *, uint32_t gpio, uint32_t val);
456 extern uint32_t ar5212GpioGet(struct ath_hal *ah, uint32_t gpio);
457 extern void ar5212GpioSetIntr(struct ath_hal *ah, u_int, uint32_t ilevel);
458 extern void ar5212SetLedState(struct ath_hal *ah, HAL_LED_STATE state);
459 extern void ar5212WriteAssocid(struct ath_hal *ah, const uint8_t *bssid,
460 uint16_t assocId);
461 extern uint32_t ar5212GetTsf32(struct ath_hal *ah);
462 extern uint64_t ar5212GetTsf64(struct ath_hal *ah);
463 extern void ar5212ResetTsf(struct ath_hal *ah);
464 extern void ar5212SetBasicRate(struct ath_hal *ah, HAL_RATE_SET *pSet);
465 extern uint32_t ar5212GetRandomSeed(struct ath_hal *ah);
466 extern HAL_BOOL ar5212DetectCardPresent(struct ath_hal *ah);
467 extern void ar5212EnableMibCounters(struct ath_hal *);
468 extern void ar5212DisableMibCounters(struct ath_hal *);
469 extern void ar5212UpdateMibCounters(struct ath_hal *ah, HAL_MIB_STATS* stats);
470 extern HAL_BOOL ar5212IsJapanChannelSpreadSupported(struct ath_hal *ah);
471 extern uint32_t ar5212GetCurRssi(struct ath_hal *ah);
472 extern u_int ar5212GetDefAntenna(struct ath_hal *ah);
473 extern void ar5212SetDefAntenna(struct ath_hal *ah, u_int antenna);
474 extern HAL_ANT_SETTING ar5212GetAntennaSwitch(struct ath_hal *);
475 extern HAL_BOOL ar5212SetAntennaSwitch(struct ath_hal *, HAL_ANT_SETTING);
476 extern HAL_BOOL ar5212IsSleepAfterBeaconBroken(struct ath_hal *ah);
477 extern HAL_BOOL ar5212SetSifsTime(struct ath_hal *, u_int);
478 extern u_int ar5212GetSifsTime(struct ath_hal *);
479 extern HAL_BOOL ar5212SetSlotTime(struct ath_hal *, u_int);
480 extern u_int ar5212GetSlotTime(struct ath_hal *);
481 extern HAL_BOOL ar5212SetAckTimeout(struct ath_hal *, u_int);
482 extern u_int ar5212GetAckTimeout(struct ath_hal *);
483 extern HAL_BOOL ar5212SetAckCTSRate(struct ath_hal *, u_int);
484 extern u_int ar5212GetAckCTSRate(struct ath_hal *);
485 extern HAL_BOOL ar5212SetCTSTimeout(struct ath_hal *, u_int);
486 extern u_int ar5212GetCTSTimeout(struct ath_hal *);
487 extern HAL_BOOL ar5212SetDecompMask(struct ath_hal *, uint16_t, int);
488 void ar5212SetCoverageClass(struct ath_hal *, uint8_t, int);
489 extern void ar5212SetPCUConfig(struct ath_hal *);
490 extern HAL_BOOL ar5212Use32KHzclock(struct ath_hal *ah, HAL_OPMODE opmode);
491 extern void ar5212SetupClock(struct ath_hal *ah, HAL_OPMODE opmode);
492 extern void ar5212RestoreClock(struct ath_hal *ah, HAL_OPMODE opmode);
493 extern int16_t ar5212GetNfAdjust(struct ath_hal *,
494 const HAL_CHANNEL_INTERNAL *);
495 extern void ar5212SetCompRegs(struct ath_hal *ah);
496 extern HAL_STATUS ar5212GetCapability(struct ath_hal *, HAL_CAPABILITY_TYPE,
497 uint32_t, uint32_t *);
498 extern HAL_BOOL ar5212SetCapability(struct ath_hal *, HAL_CAPABILITY_TYPE,
499 uint32_t, uint32_t, HAL_STATUS *);
500 extern HAL_BOOL ar5212GetDiagState(struct ath_hal *ah, int request,
501 const void *args, uint32_t argsize,
502 void **result, uint32_t *resultsize);
503
504 extern HAL_BOOL ar5212SetPowerMode(struct ath_hal *ah, HAL_POWER_MODE mode,
505 int setChip);
506 extern HAL_POWER_MODE ar5212GetPowerMode(struct ath_hal *ah);
507 extern HAL_BOOL ar5212GetPowerStatus(struct ath_hal *ah);
508
509 extern uint32_t ar5212GetRxDP(struct ath_hal *ath);
510 extern void ar5212SetRxDP(struct ath_hal *ah, uint32_t rxdp);
511 extern void ar5212EnableReceive(struct ath_hal *ah);
512 extern HAL_BOOL ar5212StopDmaReceive(struct ath_hal *ah);
513 extern void ar5212StartPcuReceive(struct ath_hal *ah);
514 extern void ar5212StopPcuReceive(struct ath_hal *ah);
515 extern void ar5212SetMulticastFilter(struct ath_hal *ah,
516 uint32_t filter0, uint32_t filter1);
517 extern HAL_BOOL ar5212ClrMulticastFilterIndex(struct ath_hal *, uint32_t ix);
518 extern HAL_BOOL ar5212SetMulticastFilterIndex(struct ath_hal *, uint32_t ix);
519 extern uint32_t ar5212GetRxFilter(struct ath_hal *ah);
520 extern void ar5212SetRxFilter(struct ath_hal *ah, uint32_t bits);
521 extern HAL_BOOL ar5212SetupRxDesc(struct ath_hal *,
522 struct ath_desc *, uint32_t size, u_int flags);
523 extern HAL_STATUS ar5212ProcRxDesc(struct ath_hal *ah, struct ath_desc *,
524 uint32_t, struct ath_desc *, uint64_t,
525 struct ath_rx_status *);
526
527 extern HAL_BOOL ar5212Reset(struct ath_hal *ah, HAL_OPMODE opmode,
528 HAL_CHANNEL *chan, HAL_BOOL bChannelChange, HAL_STATUS *status);
529 extern HAL_BOOL ar5212SetChannel(struct ath_hal *, HAL_CHANNEL_INTERNAL *);
530 extern void ar5212SetOperatingMode(struct ath_hal *ah, int opmode);
531 extern HAL_BOOL ar5212PhyDisable(struct ath_hal *ah);
532 extern HAL_BOOL ar5212Disable(struct ath_hal *ah);
533 extern HAL_BOOL ar5212ChipReset(struct ath_hal *ah, HAL_CHANNEL *);
534 extern HAL_BOOL ar5212PerCalibration(struct ath_hal *ah, HAL_CHANNEL *chan,
535 HAL_BOOL *isIQdone);
536 extern HAL_BOOL ar5212PerCalibrationN(struct ath_hal *ah, HAL_CHANNEL *chan,
537 u_int chainMask, HAL_BOOL longCal, HAL_BOOL *isCalDone);
538 extern HAL_BOOL ar5212ResetCalValid(struct ath_hal *ah, HAL_CHANNEL *chan);
539 extern int16_t ar5212GetNoiseFloor(struct ath_hal *ah);
540 extern void ar5212InitNfCalHistBuffer(struct ath_hal *);
541 extern int16_t ar5212GetNfHistMid(const int16_t calData[]);
542 extern void ar5212SetSpurMitigation(struct ath_hal *, HAL_CHANNEL_INTERNAL *);
543 extern HAL_BOOL ar5212SetAntennaSwitchInternal(struct ath_hal *ah,
544 HAL_ANT_SETTING settings, const HAL_CHANNEL_INTERNAL *ichan);
545 extern HAL_BOOL ar5212SetTxPowerLimit(struct ath_hal *ah, uint32_t limit);
546 extern HAL_BOOL ar5212GetChipPowerLimits(struct ath_hal *ah,
547 HAL_CHANNEL *chans, uint32_t nchans);
548 extern void ar5212InitializeGainValues(struct ath_hal *);
549 extern HAL_RFGAIN ar5212GetRfgain(struct ath_hal *ah);
550 extern void ar5212RequestRfgain(struct ath_hal *);
551
552 extern HAL_BOOL ar5212UpdateTxTrigLevel(struct ath_hal *,
553 HAL_BOOL IncTrigLevel);
554 extern HAL_BOOL ar5212SetTxQueueProps(struct ath_hal *ah, int q,
555 const HAL_TXQ_INFO *qInfo);
556 extern HAL_BOOL ar5212GetTxQueueProps(struct ath_hal *ah, int q,
557 HAL_TXQ_INFO *qInfo);
558 extern int ar5212SetupTxQueue(struct ath_hal *ah, HAL_TX_QUEUE type,
559 const HAL_TXQ_INFO *qInfo);
560 extern HAL_BOOL ar5212ReleaseTxQueue(struct ath_hal *ah, u_int q);
561 extern HAL_BOOL ar5212ResetTxQueue(struct ath_hal *ah, u_int q);
562 extern uint32_t ar5212GetTxDP(struct ath_hal *ah, u_int q);
563 extern HAL_BOOL ar5212SetTxDP(struct ath_hal *ah, u_int q, uint32_t txdp);
564 extern HAL_BOOL ar5212StartTxDma(struct ath_hal *ah, u_int q);
565 extern uint32_t ar5212NumTxPending(struct ath_hal *ah, u_int q);
566 extern HAL_BOOL ar5212StopTxDma(struct ath_hal *ah, u_int q);
567 extern HAL_BOOL ar5212SetupTxDesc(struct ath_hal *ah, struct ath_desc *ds,
568 u_int pktLen, u_int hdrLen, HAL_PKT_TYPE type, u_int txPower,
569 u_int txRate0, u_int txTries0,
570 u_int keyIx, u_int antMode, u_int flags,
571 u_int rtsctsRate, u_int rtsctsDuration,
572 u_int compicvLen, u_int compivLen, u_int comp);
573 extern HAL_BOOL ar5212SetupXTxDesc(struct ath_hal *, struct ath_desc *,
574 u_int txRate1, u_int txRetries1,
575 u_int txRate2, u_int txRetries2,
576 u_int txRate3, u_int txRetries3);
577 extern HAL_BOOL ar5212FillTxDesc(struct ath_hal *ah, struct ath_desc *ds,
578 u_int segLen, HAL_BOOL firstSeg, HAL_BOOL lastSeg,
579 const struct ath_desc *ds0);
580 extern HAL_STATUS ar5212ProcTxDesc(struct ath_hal *ah,
581 struct ath_desc *, struct ath_tx_status *);
582 extern void ar5212GetTxIntrQueue(struct ath_hal *ah, uint32_t *);
583 extern void ar5212IntrReqTxDesc(struct ath_hal *ah, struct ath_desc *);
584
585 extern const HAL_RATE_TABLE *ar5212GetRateTable(struct ath_hal *, u_int mode);
586
587 extern void ar5212AniAttach(struct ath_hal *, const struct ar5212AniParams *,
588 const struct ar5212AniParams *, HAL_BOOL ena);
589 extern void ar5212AniDetach(struct ath_hal *);
590 extern struct ar5212AniState *ar5212AniGetCurrentState(struct ath_hal *);
591 extern struct ar5212Stats *ar5212AniGetCurrentStats(struct ath_hal *);
592 extern HAL_BOOL ar5212AniControl(struct ath_hal *, HAL_ANI_CMD cmd, int param);
593 extern HAL_BOOL ar5212AniSetParams(struct ath_hal *,
594 const struct ar5212AniParams *, const struct ar5212AniParams *);
595 struct ath_rx_status;
596 extern void ar5212AniPhyErrReport(struct ath_hal *ah,
597 const struct ath_rx_status *rs);
598 extern void ar5212ProcessMibIntr(struct ath_hal *, const HAL_NODE_STATS *);
599 extern void ar5212AniPoll(struct ath_hal *, const HAL_NODE_STATS *,
600 HAL_CHANNEL *);
601 extern void ar5212AniReset(struct ath_hal *, HAL_CHANNEL_INTERNAL *,
602 HAL_OPMODE, int);
603 #endif /* _ATH_AR5212_H_ */
NetBSD on the FriendlyARM MINI2440