sys/external/isc/atheros_hal/dist/ar5212/ar5212_interrupts.c

   1 /*
   2  * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
   3  * Copyright (c) 2002-2008 Atheros Communications, Inc.
   4  *
   5  * Permission to use, copy, modify, and/or distribute this software for any
   6  * purpose with or without fee is hereby granted, provided that the above
   7  * copyright notice and this permission notice appear in all copies.
   8  *
   9  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  10  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  11  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  12  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  13  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  14  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  15  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  16  *
  17  * $Id: ar5212_interrupts.c,v 1.1.1.1 2008/12/11 04:46:40 alc Exp $
  18  */
  19 #include "opt_ah.h"
  20
  21 #include "ah.h"
  22 #include "ah_internal.h"
  23
  24 #include "ar5212/ar5212.h"
  25 #include "ar5212/ar5212reg.h"
  26 #include "ar5212/ar5212phy.h"
  27
  28
  29 /*
  30  * Checks to see if an interrupt is pending on our NIC
  31  *
  32  * Returns: TRUE    if an interrupt is pending
  33  *          FALSE   if not
  34  */
  35 HAL_BOOL
  36 ar5212IsInterruptPending(struct ath_hal *ah)
  37 {
  38         /*
  39          * Some platforms trigger our ISR before applying power to
  40          * the card, so make sure the INTPEND is really 1, not 0xffffffff.
  41          */
  42         return (OS_REG_READ(ah, AR_INTPEND) == AR_INTPEND_TRUE);
  43 }
  44
  45 /*
  46  * Reads the Interrupt Status Register value from the NIC, thus deasserting
  47  * the interrupt line, and returns both the masked and unmasked mapped ISR
  48  * values.  The value returned is mapped to abstract the hw-specific bit
  49  * locations in the Interrupt Status Register.
  50  *
  51  * Returns: A hardware-abstracted bitmap of all non-masked-out
  52  *          interrupts pending, as well as an unmasked value
  53  */
  54 HAL_BOOL
  55 ar5212GetPendingInterrupts(struct ath_hal *ah, HAL_INT *masked)
  56 {
  57         uint32_t isr, isr0, isr1;
  58         uint32_t mask2=0;
  59         struct ath_hal_5212 *ahp = AH5212(ah);
  60
  61         isr = OS_REG_READ(ah, AR_ISR);
  62         if (isr & AR_ISR_BCNMISC) {
  63                 uint32_t isr2;
  64                 isr2 = OS_REG_READ(ah, AR_ISR_S2);
  65                 if (isr2 & AR_ISR_S2_TIM)
  66                         mask2 |= HAL_INT_TIM;
  67                 if (isr2 & AR_ISR_S2_DTIM)
  68                         mask2 |= HAL_INT_DTIM;
  69                 if (isr2 & AR_ISR_S2_DTIMSYNC)
  70                         mask2 |= HAL_INT_DTIMSYNC;
  71                 if (isr2 & (AR_ISR_S2_CABEND ))
  72                         mask2 |= HAL_INT_CABEND;
  73         }
  74         isr = OS_REG_READ(ah, AR_ISR_RAC);
  75         if (isr == 0xffffffff) {
  76                 *masked = 0;
  77                 return AH_FALSE;;
  78         }
  79
  80         *masked = isr & HAL_INT_COMMON;
  81
  82         if (isr & AR_ISR_HIUERR)
  83                 *masked |= HAL_INT_FATAL;
  84         if (isr & (AR_ISR_RXOK | AR_ISR_RXERR))
  85                 *masked |= HAL_INT_RX;
  86         if (isr & (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR | AR_ISR_TXEOL)) {
  87                 *masked |= HAL_INT_TX;
  88                 isr0 = OS_REG_READ(ah, AR_ISR_S0_S);
  89                 ahp->ah_intrTxqs |= MS(isr0, AR_ISR_S0_QCU_TXOK);
  90                 ahp->ah_intrTxqs |= MS(isr0, AR_ISR_S0_QCU_TXDESC);
  91                 isr1 = OS_REG_READ(ah, AR_ISR_S1_S);
  92                 ahp->ah_intrTxqs |= MS(isr1, AR_ISR_S1_QCU_TXERR);
  93                 ahp->ah_intrTxqs |= MS(isr1, AR_ISR_S1_QCU_TXEOL);
  94         }
  95
  96         /*
  97          * Receive overrun is usually non-fatal on Oahu/Spirit.
  98          * BUT on some parts rx could fail and the chip must be reset.
  99          * So we force a hardware reset in all cases.
 100          */
 101         if ((isr & AR_ISR_RXORN) && AH_PRIVATE(ah)->ah_rxornIsFatal) {
 102                 HALDEBUG(ah, HAL_DEBUG_ANY,
 103                     "%s: receive FIFO overrun interrupt\n", __func__);
 104                 *masked |= HAL_INT_FATAL;
 105         }
 106         *masked |= mask2;
 107
 108         /*
 109          * On fatal errors collect ISR state for debugging.
 110          */
 111         if (*masked & HAL_INT_FATAL) {
 112                 AH_PRIVATE(ah)->ah_fatalState[0] = isr;
 113                 AH_PRIVATE(ah)->ah_fatalState[1] = OS_REG_READ(ah, AR_ISR_S0_S);
 114                 AH_PRIVATE(ah)->ah_fatalState[2] = OS_REG_READ(ah, AR_ISR_S1_S);
 115                 AH_PRIVATE(ah)->ah_fatalState[3] = OS_REG_READ(ah, AR_ISR_S2_S);
 116                 AH_PRIVATE(ah)->ah_fatalState[4] = OS_REG_READ(ah, AR_ISR_S3_S);
 117                 AH_PRIVATE(ah)->ah_fatalState[5] = OS_REG_READ(ah, AR_ISR_S4_S);
 118                 HALDEBUG(ah, HAL_DEBUG_ANY,
 119                     "%s: fatal error, ISR_RAC=0x%x ISR_S2_S=0x%x\n",
 120                     __func__, isr, AH_PRIVATE(ah)->ah_fatalState[3]);
 121         }
 122         return AH_TRUE;
 123 }
 124
 125 HAL_INT
 126 ar5212GetInterrupts(struct ath_hal *ah)
 127 {
 128         return AH5212(ah)->ah_maskReg;
 129 }
 130
 131 /*
 132  * Atomically enables NIC interrupts.  Interrupts are passed in
 133  * via the enumerated bitmask in ints.
 134  */
 135 HAL_INT
 136 ar5212SetInterrupts(struct ath_hal *ah, HAL_INT ints)
 137 {
 138         struct ath_hal_5212 *ahp = AH5212(ah);
 139         uint32_t omask = ahp->ah_maskReg;
 140         uint32_t mask,mask2;
 141
 142         HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: 0x%x => 0x%x\n",
 143             __func__, omask, ints);
 144
 145         if (omask & HAL_INT_GLOBAL) {
 146                 HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: disable IER\n", __func__);
 147                 OS_REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
 148                 (void) OS_REG_READ(ah, AR_IER);   /* flush write to HW */
 149         }
 150
 151         mask = ints & HAL_INT_COMMON;
 152         mask2 = 0;
 153         if (ints & HAL_INT_TX) {
 154                 if (ahp->ah_txOkInterruptMask)
 155                         mask |= AR_IMR_TXOK;
 156                 if (ahp->ah_txErrInterruptMask)
 157                         mask |= AR_IMR_TXERR;
 158                 if (ahp->ah_txDescInterruptMask)
 159                         mask |= AR_IMR_TXDESC;
 160                 if (ahp->ah_txEolInterruptMask)
 161                         mask |= AR_IMR_TXEOL;
 162         }
 163         if (ints & HAL_INT_RX)
 164                 mask |= AR_IMR_RXOK | AR_IMR_RXERR | AR_IMR_RXDESC;
 165         if (ints & (HAL_INT_BMISC)) {
 166                 mask |= AR_IMR_BCNMISC;
 167                 if (ints & HAL_INT_TIM)
 168                         mask2 |= AR_IMR_S2_TIM;
 169                 if (ints & HAL_INT_DTIM)
 170                         mask2 |= AR_IMR_S2_DTIM;
 171                 if (ints & HAL_INT_DTIMSYNC)
 172                         mask2 |= AR_IMR_S2_DTIMSYNC;
 173                 if (ints & HAL_INT_CABEND)
 174                         mask2 |= (AR_IMR_S2_CABEND );
 175         }
 176         if (ints & HAL_INT_FATAL) {
 177                 /*
 178                  * NB: ar5212Reset sets MCABT+SSERR+DPERR in AR_IMR_S2
 179                  *     so enabling HIUERR enables delivery.
 180                  */
 181                 mask |= AR_IMR_HIUERR;
 182         }
 183
 184         /* Write the new IMR and store off our SW copy. */
 185         HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: new IMR 0x%x\n", __func__, mask);
 186         OS_REG_WRITE(ah, AR_IMR, mask);
 187         OS_REG_WRITE(ah, AR_IMR_S2,
 188                                  (OS_REG_READ(ah, AR_IMR_S2) &
 189                                   ~(AR_IMR_S2_TIM |
 190                                         AR_IMR_S2_DTIM |
 191                                         AR_IMR_S2_DTIMSYNC |
 192                                         AR_IMR_S2_CABEND |
 193                                         AR_IMR_S2_CABTO  |
 194                                         AR_IMR_S2_TSFOOR ) )
 195                                  | mask2);
 196         ahp->ah_maskReg = ints;
 197
 198         /* Re-enable interrupts if they were enabled before. */
 199         if (ints & HAL_INT_GLOBAL) {
 200                 HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: enable IER\n", __func__);
 201                 OS_REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
 202         }
 203
 204
 205         return omask;
 206 }