No empty .Rs/.Re
[netbsd-mini2440.git] / sys / external / isc / atheros_hal / dist / ar5312 / ar5312phy.h
blob57ed48b71fa8186272318d031906f13abb9fe07c
1 /*
2 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
3 * Copyright (c) 2002-2008 Atheros Communications, Inc.
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 * $Id: ar5312phy.h,v 1.1.1.1 2008/12/11 04:46:46 alc Exp $
19 #ifndef _DEV_ATH_AR5312PHY_H_
20 #define _DEV_ATH_AR5312PHY_H_
22 #include "ar5212/ar5212phy.h"
24 /* PHY registers */
26 #define AR_PHY_PLL_CTL_44_5312 0x14d6 /* 44 MHz for 11b, 11g */
27 #define AR_PHY_PLL_CTL_40_5312 0x14d4 /* 40 MHz for 11a, turbos */
28 #define AR_PHY_PLL_CTL_40_5312_HALF 0x15d4 /* 40 MHz for 11a, turbos (Half)*/
29 #define AR_PHY_PLL_CTL_40_5312_QUARTER 0x16d4 /* 40 MHz for 11a, turbos (Quarter)*/
31 #endif /* _DEV_ATH_AR5312PHY_H_ */