| blob | f645a7e7e59b2c2df9e7e7beaf5983b9337459ce |
1 2013-10-14 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
3 * mips.h (mips_operand_type): Add OP_IMM_INDEX and OP_REG_INDEX.
4 (mips_reg_operand_type): Add OP_REG_MSA and OP_REG_MSA_CTRL.
5 For MIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
6 +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
7 For MIPS, update extension character sequences after +.
8 (ASE_MSA): New define.
9 (ASE_MSA64): New define.
10 For microMIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
11 +x, +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
12 For microMIPS, update extension character sequences after +.
14 2013-08-23 Yuri Chornoivan <yurchor@ukr.net>
16 PR binutils/15834
17 * i960.h: Fix typos.
19 2013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
21 * mips.h: Remove references to "+I" and imm2_expr.
23 2013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
25 * mips.h (M_DEXT, M_DINS): Delete.
27 2013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
29 * mips.h (OP_OPTIONAL_REG): New mips_operand_type.
30 (mips_optional_operand_p): New function.
32 2013-08-04 Jürgen Urban <JuergenUrban@gmx.de>
33 Richard Sandiford <rdsandiford@googlemail.com>
35 * mips.h: Document new VU0 operand characters.
36 (OP_VU0_SUFFIX, OP_VU0_MATCH_SUFFIX): New mips_operand_types.
37 (OP_REG_VF, OP_REG_VI, OP_REG_R5900_I, OP_REG_R5900_Q, OP_REG_R5900_R)
38 (OP_REG_R5900_ACC): New mips_reg_operand_types.
39 (INSN2_VU0_CHANNEL_SUFFIX): New macro.
40 (mips_vu0_channel_mask): Declare.
42 2013-08-03 Richard Sandiford <rdsandiford@googlemail.com>
44 * mips.h (mips_pcrel_operand): Inherit from mips_int_operand.
45 (mips_int_operand_min, mips_int_operand_max): New functions.
46 (mips_decode_pcrel_operand): Use mips_decode_int_operand.
48 2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
50 * mips.h (mips_decode_reg_operand): New function.
51 (INSN_WRITE_SHIFT, INSN_WRITE_1, INSN_WRITE_2, INSN_WRITE_ALL)
52 (INSN_READ_SHIFT, INSN_READ_1, INSN_READ_2, INSN_READ_3, INSN_READ_4)
53 (INSN_READ_ALL, INSN_READ_GPR_24, INSN_WRITE_GPR_24, INSN_UDI):
54 New macros.
55 (INSN_WRITE_GPR_D, INSN_WRITE_GPR_T, INSN_WRITE_FPR_D)
56 (INSN_WRITE_FPR_S, INSN_WRITE_FPR_T, INSN_READ_GPR_S, INSN_READ_GPR_T)
57 (INSN_READ_FPR_S, INSN_READ_FPR_T, INSN_READ_FPR_R, INSN_WRITE_GPR_S)
58 (INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z, INSN2_READ_GPR_Z)
59 (INSN2_READ_FPR_Z, INSN2_READ_GPR_D, INSN2_READ_FPR_D)
60 (INSN2_WRITE_GPR_MB, INSN2_READ_GPR_MC, INSN2_MOD_GPR_MD)
61 (INSN2_READ_GPR_ME, INSN2_MOD_GPR_MF, INSN2_READ_GPR_MG)
62 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ, INSN2_READ_GPR_MP)
63 (INSN2_WRITE_GPR_MP, INSN2_READ_GPR_MQ, INSN2_READ_GP)
64 (INSN2_WRITE_GPR_MH, INSN2_READ_GPR_MMN): Delete. Renumber other
65 macros to cover the gaps.
66 (INSN2_MOD_SP): Replace with...
67 (INSN2_WRITE_SP, INSN2_READ_SP): ...these new macros.
68 (MIPS16_INSN_WRITE_X, MIPS16_INSN_WRITE_Y, MIPS16_INSN_WRITE_Z)
69 (MIPS16_INSN_WRITE_T, MIPS16_INSN_WRITE_31, MIPS16_INSN_WRITE_GPR_Y)
70 (MIPS16_INSN_READ_X, MIPS16_INSN_READ_Y, MIPS16_INSN_READ_Z)
71 (MIPS16_INSN_READ_T, MIPS16_INSN_READ_SP, MIPS16_INSN_READ_GPR_X):
72 Delete.
74 2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
76 * mips.h (MIPS16_INSN_WRITE_SP, MIPS16_INSN_READ_31)
77 (MIPS16_INSN_READ_PC, MIPS16_INSN_UNCOND_BRANCH)
78 (MIPS16_INSN_COND_BRANCH): Delete.
80 2013-07-24 Anna Tikhonova <anna.tikhonova@intel.com>
81 Kirill Yukhin <kirill.yukhin@intel.com>
82 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
84 * i386.h (BND_PREFIX_OPCODE): New.
86 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
88 * mips.h (mips_operand_type): Add OP_ENTRY_EXIT_LIST and
89 OP_SAVE_RESTORE_LIST.
90 (decode_mips16_operand): Declare.
92 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
94 * mips.h (mips_operand_type, mips_reg_operand_type): New enums.
95 (mips_operand, mips_int_operand, mips_mapped_int_operand)
96 (mips_msb_operand, mips_reg_operand, mips_reg_pair_operand)
97 (mips_pcrel_operand): New structures.
98 (mips_insert_operand, mips_extract_operand, mips_signed_operand)
99 (mips_decode_int_operand, mips_decode_pcrel_operand): New functions.
100 (decode_mips_operand, decode_micromips_operand): Declare.
102 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
104 * mips.h: Document MIPS16 "I" opcode.
106 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
108 * mips.h (M_ACLR_OB, M_ASET_OB, M_CACHE_OB, M_CACHEE_OB, M_L_DOB)
109 (M_LB_A, M_LBE_OB, M_LBU_A, M_LBUE_OB, M_LD_A, M_LD_OB, M_LDC2_OB)
110 (M_LDL_OB, M_LDM_OB, M_LDP_OB, M_LDR_OB, M_LH_A, M_LHE_OB, M_LHU_A)
111 (M_LHUE_OB, M_LL_OB, M_LLD_OB, M_LLE_OB, M_LS_A, M_LW_A, M_LWE_OB)
112 (M_LWC0_A, M_LWC1_A, M_LWC2_A, M_LWC2_OB, M_LWC3_A, M_LWL_A, M_LWL_OB)
113 (M_LWLE_OB, M_LWM_OB, M_LWP_OB, M_LWR_A, M_LWR_OB, M_LWRE_OB, M_LWU_OB)
114 (M_PREF_OB, M_PREFE_OB, M_S_DOB, M_SAA_OB, M_SAAD_OB, M_SC_OB)
115 (M_SCD_OB, M_SCE_OB, M_SD_A, M_SD_OB, M_SDC2_OB, M_SDL_OB, M_SDM_OB)
116 (M_SDP_OB, M_SDR_OB, M_SB_A, M_SBE_OB, M_SH_A, M_SHE_OB, M_SW_A)
117 (M_SWE_OB, M_SWC0_A, M_SWC1_A, M_SWC2_A, M_SWC2_OB, M_SWC3_A, M_SWL_A)
118 (M_SWL_OB, M_SWLE_OB, M_SWM_OB, M_SWP_OB, M_SWR_A, M_SWR_OB, M_SWRE_OB)
119 (M_ULD, M_ULH, M_ULHU, M_ULW, M_USH, M_USW, M_USD): Delete.
120 (M_ULD_A, M_ULH_A, M_ULHU_A, M_ULW_A, M_USH_A, M_USW_A, M_USD_A):
121 Rename to...
122 (M_ULD_AB, M_ULH_AB, M_ULHU_AB, M_ULW_AB, M_USH_AB, M_USW_AB)
123 (M_USD_AB): ...these.
125 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
127 * mips.h: Remove documentation of "[" and "]". Update documentation
128 of "k" and the MDMX formats.
130 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
132 * mips.h: Update documentation of "+s" and "+S".
134 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
136 * mips.h: Document "+i".
138 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
140 * mips.h: Remove "mi" documentation. Update "mh" documentation.
141 (OP_MASK_MI, OP_SH_MI, MICROMIPSOP_MASK_MI, MICROMIPSOP_MASK_MI):
142 Delete.
143 (INSN2_WRITE_GPR_MHI): Rename to...
144 (INSN2_WRITE_GPR_MH): ...this.
146 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
148 * mips.h: Remove documentation of "+D" and "+T".
150 2013-06-26 Richard Sandiford <rdsandiford@googlemail.com>
152 * mips.h: Fix comment for "1": it is now STYPE rather than SHAMT.
153 Use "source" rather than "destination" for microMIPS "G".
155 2013-06-25 Maciej W. Rozycki <macro@codesourcery.com>
157 * mips.h: Add M_JRADDIUSP, M_JRC and M_MOVEP anonymous enum
158 values.
160 2013-06-23 Richard Sandiford <rdsandiford@googlemail.com>
162 * mips.h: Fix comment typo: "G" is _RS rather than _RD for microMIPS.
164 2013-06-17 Catherine Moore <clm@codesourcery.com>
165 Maciej W. Rozycki <macro@codesourcery.com>
166 Chao-Ying Fu <fu@mips.com>
168 * mips.h (OP_SH_EVAOFFSET): Define.
169 (OP_MASK_EVAOFFSET): Define.
170 (INSN_ASE_MASK): Delete.
171 (ASE_EVA): Define.
172 (M_CACHEE_AB, M_CACHEE_OB): New.
173 (M_LBE_OB, M_LBE_AB): New.
174 (M_LBUE_OB, M_LBUE_AB): New.
175 (M_LHE_OB, M_LHE_AB): New.
176 (M_LHUE_OB, M_LHUE_AB): New.
177 (M_LLE_AB, M_LLE_OB): New.
178 (M_LWE_OB, M_LWE_AB): New.
179 (M_LWLE_AB, M_LWLE_OB): New.
180 (M_LWRE_AB, M_LWRE_OB): New.
181 (M_PREFE_AB, M_PREFE_OB): New.
182 (M_SCE_AB, M_SCE_OB): New.
183 (M_SBE_OB, M_SBE_AB): New.
184 (M_SHE_OB, M_SHE_AB): New.
185 (M_SWE_OB, M_SWE_AB): New.
186 (M_SWLE_AB, M_SWLE_OB): New.
187 (M_SWRE_AB, M_SWRE_OB): New.
188 (MICROMIPSOP_SH_EVAOFFSET): Define.
189 (MICROMIPSOP_MASK_EVAOFFSET): Define.
191 2013-06-12 Sandra Loosemore <sandra@codesourcery.com>
193 * nios2.h (OP_MATCH_ERET): Correct eret encoding.
195 2013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
197 * mips.h (M_LQC2_AB, M_SQC2_AB): New macros.
199 2013-05-09 Andrew Pinski <apinski@cavium.com>
201 * mips.h (OP_MASK_CODE10): Correct definition.
202 (OP_SH_CODE10): Likewise.
203 Add a comment that "+J" is used now for OP_*CODE10.
204 (INSN_ASE_MASK): Update.
205 (INSN_VIRT): New macro.
206 (INSN_VIRT64): New macro
208 2013-05-02 Nick Clifton <nickc@redhat.com>
210 * msp430.h: Add patterns for MSP430X instructions.
212 2013-04-06 David S. Miller <davem@davemloft.net>
214 * sparc.h (F_PREFERRED): Define.
215 (F_PREF_ALIAS): Define.
217 2013-04-03 Nick Clifton <nickc@redhat.com>
219 * v850.h (V850_INVERSE_PCREL): Define.
221 2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
223 PR binutils/15068
224 * tic6x-opcode-table.h: Fix patterns for add, ldnw and xor.
226 2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
228 PR binutils/15068
229 * tic6xc-insn-formats.h (FLD): Add use of bitfield array.
230 Add 16-bit opcodes.
231 * tic6xc-opcode-table.h: Add 16-bit insns.
232 * tic6x.h: Add support for 16-bit insns.
234 2013-03-21 Michael Schewe <michael.schewe@gmx.net>
236 * h8300.h: Add MEMRELAX flag for mov.b/w/l @(d:32,ERs),Rd
237 and mov.b/w/l Rs,@(d:32,ERd).
239 2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
241 PR gas/15082
242 * tic6x-opcode-table.h: Rename mpydp's specific operand type macro
243 from ORREGD1324 to ORXREGD1324 and make it cross-path-able through
244 tic6x_operand_xregpair operand coding type.
245 Make mpydp instruction cross-path-able, ie: remove the FIXed 'x'
246 opcode field, usu ORXREGD1324 for the src2 operand and remove the
247 TIC6X_FLAG_NO_CROSS.
249 2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
251 PR gas/15095
252 * tic6x.h (enum tic6x_coding_method): Add
253 tic6x_coding_dreg_(msb|lsb) field coding type in order to encode
254 separately the msb and lsb of a register pair. This is needed to
255 encode the opcodes in the same way as TI assembler does.
256 * tic6x-opcode-table.h: Modify absdp, dpint, dpsp, dptrunc, rcpdp
257 and rsqrdp opcodes to use the new field coding types.
259 2013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
261 * arm.h (CRC_EXT_ARMV8): New constant.
262 (ARCH_CRC_ARMV8): New macro.
264 2013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
266 * aarch64.h (AARCH64_FEATURE_CRC): New macro.
268 2013-02-06 Sandra Loosemore <sandra@codesourcery.com>
269 Andrew Jenner <andrew@codesourcery.com>
271 Based on patches from Altera Corporation.
273 * nios2.h: New file.
275 2013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
277 * aarch64.h (aarch64_op): Add OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2.
279 2013-01-28 Alexis Deruelle <alexis.deruelle@gmail.com>
281 PR gas/15069
282 * tic6x-opcode-table.h: Fix encoding of BNOP instruction.
284 2013-01-24 Nick Clifton <nickc@redhat.com>
286 * v850.h: Add e3v5 support.
288 2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
290 * aarch64.h (aarch64_op): Remove OP_V_MOVI_B.
292 2013-01-10 Peter Bergner <bergner@vnet.ibm.com>
294 * ppc.h (PPC_OPCODE_POWER8): New define.
295 (PPC_OPCODE_HTM): Likewise.
297 2013-01-10 Will Newton <will.newton@imgtec.com>
299 * metag.h: New file.
301 2013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
303 * cr16.h (make_instruction): Rename to cr16_make_instruction.
304 (match_opcode): Rename to cr16_match_opcode.
306 2013-01-04 Juergen Urban <JuergenUrban@gmx.de>
308 * mips.h: Add support for r5900 instructions including lq and sq.
310 2013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
312 * cr16.h (dwordU,wordU): Moved typedefs from cr16-dis.c
313 (make_instruction,match_opcode): Added function prototypes.
314 (cr16_words,cr16_allWords,cr16_currInsn): Declare as extern.
316 2012-11-23 Alan Modra <amodra@gmail.com>
318 * ppc.h (ppc_parse_cpu): Update prototype.
320 2012-10-14 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
322 * hppa.h (pa_opcodes): Use "cX" completer instead of "cx" in fstqx
323 opcodes. Likewise, use "cM" instead of "cm" in fstqs opcodes.
325 2012-10-04 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
327 * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_ZEC12.
329 2012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com>
331 * ia64.h (ia64_opnd): Add new operand types.
333 2012-08-21 David S. Miller <davem@davemloft.net>
335 * sparc.h (F3F4): New macro.
337 2012-08-13 Ian Bolton <ian.bolton@arm.com>
338 Laurent Desnogues <laurent.desnogues@arm.com>
339 Jim MacArthur <jim.macarthur@arm.com>
340 Marcus Shawcroft <marcus.shawcroft@arm.com>
341 Nigel Stephens <nigel.stephens@arm.com>
342 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
343 Richard Earnshaw <rearnsha@arm.com>
344 Sofiane Naci <sofiane.naci@arm.com>
345 Tejas Belagod <tejas.belagod@arm.com>
346 Yufeng Zhang <yufeng.zhang@arm.com>
348 * aarch64.h: New file.
350 2012-08-13 Richard Sandiford <rdsandiford@googlemail.com>
351 Maciej W. Rozycki <macro@codesourcery.com>
353 * mips.h (mips_opcode): Add the exclusions field.
354 (OPCODE_IS_MEMBER): Remove macro.
355 (cpu_is_member): New inline function.
356 (opcode_is_member): Likewise.
358 2012-07-31 Chao-Ying Fu <fu@mips.com>
359 Catherine Moore <clm@codesourcery.com>
360 Maciej W. Rozycki <macro@codesourcery.com>
362 * mips.h: Document microMIPS DSP ASE usage.
363 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Update for
364 microMIPS DSP ASE support.
365 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
366 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
367 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
368 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
369 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
370 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
371 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
373 2012-07-06 Maciej W. Rozycki <macro@codesourcery.com>
375 * mips.h: Fix a typo in description.
377 2012-06-07 Georg-Johann Lay <avr@gjlay.de>
379 * avr.h: (AVR_ISA_XCH): New define.
380 (AVR_ISA_XMEGA): Use it.
381 (XCH, LAS, LAT, LAC): New XMEGA opcodes.
383 2012-05-15 James Murray <jsm@jsm-net.demon.co.uk>
385 * m68hc11.h: Add XGate definitions.
386 (struct m68hc11_opcode): Add xg_mask field.
388 2012-05-14 Catherine Moore <clm@codesourcery.com>
389 Maciej W. Rozycki <macro@codesourcery.com>
390 Rhonda Wittels <rhonda@codesourcery.com>
392 * ppc.h (PPC_OPCODE_VLE): New definition.
393 (PPC_OP_SA): New macro.
394 (PPC_OP_SE_VLE): New macro.
395 (PPC_OP): Use a variable shift amount.
396 (powerpc_operand): Update comments.
397 (PPC_OPSHIFT_INV): New macro.
398 (PPC_OPERAND_CR): Replace with...
399 (PPC_OPERAND_CR_BIT): ...this and
400 (PPC_OPERAND_CR_REG): ...this.
403 2012-05-03 Sean Keys <skeys@ipdatasys.com>
405 * xgate.h: Header file for XGATE assembler.
407 2012-04-27 David S. Miller <davem@davemloft.net>
409 * sparc.h: Document new arg code' )' for crypto RS3
410 immediates.
412 * sparc.h (struct sparc_opcode): New field 'hwcaps'.
413 F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
414 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
415 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
416 (HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
417 HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
418 HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
419 HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
420 HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
421 HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
422 HWCAP_CBCOND, HWCAP_CRC32): New defines.
424 2012-03-10 Edmar Wienskoski <edmar@freescale.com>
426 * ppc.h: Add PPC_OPCODE_ALTIVEC2, PPC_OPCODE_E6500, PPC_OPCODE_TMR.
428 2012-02-27 Alan Modra <amodra@gmail.com>
430 * crx.h (cst4_map): Update declaration.
432 2012-02-25 Walter Lee <walt@tilera.com>
434 * tilegx.h (tilegx_mnemonic): Add TILEGX_OPC_LD4S_TLS,
435 TILEGX_OPC_LD_TLS.
436 * tilepro.h (tilepro_mnemonic): Add TILEPRO_OPC_LW_TLS,
437 TILEPRO_OPC_LW_TLS_SN.
439 2012-02-08 H.J. Lu <hongjiu.lu@intel.com>
441 * i386.h (XACQUIRE_PREFIX_OPCODE): New.
442 (XRELEASE_PREFIX_OPCODE): Likewise.
444 2011-12-08 Andrew Pinski <apinski@cavium.com>
445 Adam Nemet <anemet@caviumnetworks.com>
447 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2.
448 (INSN_OCTEON2): New macro.
449 (CPU_OCTEON2): New macro.
450 (OPCODE_IS_MEMBER): Add Octeon2.
452 2011-11-29 Andrew Pinski <apinski@cavium.com>
454 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP.
455 (INSN_OCTEONP): New macro.
456 (CPU_OCTEONP): New macro.
457 (OPCODE_IS_MEMBER): Add Octeon+.
458 (M_SAA_AB, M_SAAD_AB, M_SAA_OB, M_SAAD_OB): New enum values.
460 2011-11-01 DJ Delorie <dj@redhat.com>
462 * rl78.h: New file.
464 2011-10-24 Maciej W. Rozycki <macro@codesourcery.com>
466 * mips.h: Fix a typo in description.
468 2011-09-21 David S. Miller <davem@davemloft.net>
470 * sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int.
471 (F_MUL32, F_DIV32, F_FSMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
472 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
473 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits.
475 2011-08-09 Chao-ying Fu <fu@mips.com>
476 Maciej W. Rozycki <macro@codesourcery.com>
478 * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros.
479 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine.
480 (INSN_ASE_MASK): Add the MCU bit.
481 (INSN_MCU): New macro.
482 (M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values.
483 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros.
485 2011-08-09 Maciej W. Rozycki <macro@codesourcery.com>
487 * mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros.
488 (INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise.
489 (INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise.
490 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise.
491 (INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise.
492 (INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise.
493 (INSN2_READ_GPR_MMN): Likewise.
494 (INSN2_READ_FPR_D): Change the bit used.
495 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise.
496 (INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise.
497 (INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise.
498 (INSN2_COND_BRANCH): Likewise.
499 (INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros.
500 (INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise.
501 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise.
502 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise.
503 (INSN2_MOD_GPR_MN): Likewise.
505 2011-08-05 David S. Miller <davem@davemloft.net>
507 * sparc.h: Document new format codes '4', '5', and '('.
508 (OPF_LOW4, RS3): New macros.
510 2011-08-03 Maciej W. Rozycki <macro@codesourcery.com>
512 * mips.h: Document the use of FP_D in MIPS16 mode. Adjust the
513 order of flags documented.
515 2011-07-29 Maciej W. Rozycki <macro@codesourcery.com>
517 * mips.h: Clarify the description of microMIPS instruction
518 manipulation macros.
519 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros.
521 2011-07-24 Chao-ying Fu <fu@mips.com>
522 Maciej W. Rozycki <macro@codesourcery.com>
524 * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
525 (OP_MASK_STYPE, OP_SH_STYPE): Likewise.
526 (OP_MASK_CODE10, OP_SH_CODE10): Likewise.
527 (OP_MASK_TRAP, OP_SH_TRAP): Likewise.
528 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
529 (OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
530 (OP_MASK_RS3, OP_SH_RS3): Likewise.
531 (OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
532 (OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
533 (OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
534 (OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
535 (OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
536 (OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
537 (OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
538 (OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
539 (OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
540 (OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
541 (OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
542 (OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
543 (OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
544 (OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
545 (INSN_WRITE_GPR_S): New macro.
546 (INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise.
547 (INSN2_READ_FPR_D): Likewise.
548 (INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise.
549 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise.
550 (INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
551 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise.
552 (INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise.
553 (INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise.
554 (INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise.
555 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
556 (CPU_MICROMIPS): New macro.
557 (M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values.
558 (M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise.
559 (M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise.
560 (M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise.
561 (M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
562 (M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
563 (M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise.
564 (M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise.
565 (M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
566 (M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise.
567 (M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise.
568 (M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise.
569 (M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
570 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
571 (MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
572 (MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
573 (MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
574 (MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
575 (MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
576 (MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
577 (MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
578 (MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
579 (MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
580 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
581 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
582 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
583 (MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
584 (MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
585 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
586 (MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
587 (MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
588 (MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
589 (MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
590 (MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
591 (MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
592 (MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
593 (MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
594 (MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
595 (MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
596 (MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
597 (MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
598 (MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
599 (MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
600 (MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
601 (MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
602 (MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
603 (MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
604 (MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
605 (MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
606 (MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
607 (MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
608 (MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
609 (MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
610 (MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
611 (MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
612 (MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
613 (MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
614 (MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
615 (MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
616 (MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
617 (MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
618 (MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
619 (MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
620 (MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
621 (MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
622 (MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
623 (MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
624 (MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
625 (MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
626 (MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
627 (MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
628 (MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
629 (MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
630 (MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
631 (MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
632 (MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
633 (MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
634 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
635 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
636 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
637 (MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
638 (MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
639 (MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
640 (MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
641 (MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
642 (MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
643 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
644 (MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
645 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
646 (MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
647 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
648 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
649 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
650 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
651 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
652 (MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
653 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
654 (MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
655 (MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
656 (MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
657 (MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
658 (MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
659 (MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
660 (MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
661 (MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
662 (micromips_opcodes): New declaration.
663 (bfd_micromips_num_opcodes): Likewise.
665 2011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
667 * mips.h (INSN_TRAP): Rename to...
668 (INSN_NO_DELAY_SLOT): ... this.
669 (INSN_SYNC): Remove macro.
671 2011-07-01 Eric B. Weddington <eric.weddington@atmel.com>
673 * avr.h (AVR_ISA_AVR6): Remove AVR_ISA_SPMX as it was actually
674 a duplicate of AVR_ISA_SPM.
676 2011-07-01 Nick Clifton <nickc@redhat.com>
678 * avr.h (AVR_ISA_AVR6): Fix typo, adding AVR_ISA_SPMX.
680 2011-06-18 Robin Getz <robin.getz@analog.com>
682 * bfin.h (is_macmod_signed): New func
684 2011-06-18 Mike Frysinger <vapier@gentoo.org>
686 * bfin.h (is_macmod_pmove): Add missing space before func args.
687 (is_macmod_hmove): Likewise.
689 2011-06-13 Walter Lee <walt@tilera.com>
691 * tilegx.h: New file.
692 * tilepro.h: New file.
694 2011-05-31 Paul Brook <paul@codesourcery.com>
696 * arm.h (ARM_ARCH_V7R_IDIV): Define.
698 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
700 * s390.h: Replace S390_OPERAND_REG_EVEN with
701 S390_OPERAND_REG_PAIR.
703 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
705 * s390.h: Add S390_OPCODE_REG_EVEN flag.
707 2011-04-18 Julian Brown <julian@codesourcery.com>
709 * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
711 2011-04-11 Dan McDonald <dan@wellkeeper.com>
713 PR gas/12296
714 * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS.
716 2011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
718 * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
719 New instruction set flags.
720 (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
722 2011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
724 * mips.h (M_PREF_AB): New enum value.
726 2011-02-12 Mike Frysinger <vapier@gentoo.org>
728 * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
729 M_IU): Define.
730 (is_macmod_pmove, is_macmod_hmove): New functions.
732 2011-02-11 Mike Frysinger <vapier@gentoo.org>
734 * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
736 2011-02-04 Bernd Schmidt <bernds@codesourcery.com>
738 * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
739 * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
741 2010-12-31 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
743 PR gas/11395
744 * hppa.h (pa_opcodes): Revert last change. Exchange 32 and 64-bit
745 "bb" entries.
747 2010-12-26 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
749 PR gas/11395
750 * hppa.h: Clear "d" bit in "add" and "sub" patterns.
752 2010-12-18 Richard Sandiford <rdsandiford@googlemail.com>
754 * mips.h: Update commentary after last commit.
756 2010-12-18 Mingjie Xing <mingjie.xing@gmail.com>
758 * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
759 (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
760 (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
762 2010-11-25 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
764 * s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU.
766 2010-11-23 Richard Sandiford <rdsandiford@googlemail.com>
768 * mips.h: Fix previous commit.
770 2010-11-23 Maciej W. Rozycki <macro@linux-mips.org>
772 * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
773 (INSN_LOONGSON_3A): Clear bit 31.
775 2010-11-15 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
777 PR gas/12198
778 * arm.h (ARM_AEXT_V6M_ONLY): New define.
779 (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
780 (ARM_ARCH_V6M_ONLY): New define.
782 2010-11-11 Mingming Sun <mingm.sun@gmail.com>
784 * mips.h (INSN_LOONGSON_3A): Defined.
785 (CPU_LOONGSON_3A): Defined.
786 (OPCODE_IS_MEMBER): Add LOONGSON_3A.
788 2010-10-09 Matt Rice <ratmice@gmail.com>
790 * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
791 (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
793 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
795 * arm.h (ARM_EXT_VIRT): New define.
796 (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
797 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
798 Extensions.
800 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
802 * arm.h (ARM_AEXT_ADIV): New define.
803 (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
805 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
807 * arm.h (ARM_EXT_OS): New define.
808 (ARM_AEXT_V6SM): Likewise.
809 (ARM_ARCH_V6SM): Likewise.
811 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
813 * arm.h (ARM_EXT_MP): Add.
814 (ARM_ARCH_V7A_MP): Likewise.
816 2010-09-22 Mike Frysinger <vapier@gentoo.org>
818 * bfin.h: Declare pseudoChr structs/defines.
820 2010-09-21 Mike Frysinger <vapier@gentoo.org>
822 * bfin.h: Strip trailing whitespace.
824 2010-07-29 DJ Delorie <dj@redhat.com>
826 * rx.h (RX_Operand_Type): Add TwoReg.
827 (RX_Opcode_ID): Remove ediv and ediv2.
829 2010-07-27 DJ Delorie <dj@redhat.com>
831 * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
833 2010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
834 Ina Pandit <ina.pandit@kpitcummins.com>
836 * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
837 PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
838 PROCESSOR_V850E2_ALL.
839 Remove PROCESSOR_V850EA support.
840 (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
841 V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
842 V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
843 V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
844 V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
845 V850_OPERAND_PERCENT.
846 Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
847 V850_NOT_R0.
848 Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
849 and V850E_PUSH_POP
851 2010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
853 * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
854 (MIPS16_INSN_BRANCH): Rename to...
855 (MIPS16_INSN_COND_BRANCH): ... this.
857 2010-07-03 Alan Modra <amodra@gmail.com>
859 * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
860 Renumber other PPC_OPCODE defines.
862 2010-07-03 Alan Modra <amodra@gmail.com>
864 * ppc.h (PPC_OPCODE_COMMON): Expand comment.
866 2010-06-29 Alan Modra <amodra@gmail.com>
868 * maxq.h: Delete file.
870 2010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
872 * ppc.h (PPC_OPCODE_E500): Define.
874 2010-05-26 Catherine Moore <clm@codesourcery.com>
876 * opcode/mips.h (INSN_MIPS16): Remove.
878 2010-04-21 Joseph Myers <joseph@codesourcery.com>
880 * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
882 2010-04-15 Nick Clifton <nickc@redhat.com>
884 * alpha.h: Update copyright notice to use GPLv3.
885 * arc.h: Likewise.
886 * arm.h: Likewise.
887 * avr.h: Likewise.
888 * bfin.h: Likewise.
889 * cgen.h: Likewise.
890 * convex.h: Likewise.
891 * cr16.h: Likewise.
892 * cris.h: Likewise.
893 * crx.h: Likewise.
894 * d10v.h: Likewise.
895 * d30v.h: Likewise.
896 * dlx.h: Likewise.
897 * h8300.h: Likewise.
898 * hppa.h: Likewise.
899 * i370.h: Likewise.
900 * i386.h: Likewise.
901 * i860.h: Likewise.
902 * i960.h: Likewise.
903 * ia64.h: Likewise.
904 * m68hc11.h: Likewise.
905 * m68k.h: Likewise.
906 * m88k.h: Likewise.
907 * maxq.h: Likewise.
908 * mips.h: Likewise.
909 * mmix.h: Likewise.
910 * mn10200.h: Likewise.
911 * mn10300.h: Likewise.
912 * msp430.h: Likewise.
913 * np1.h: Likewise.
914 * ns32k.h: Likewise.
915 * or32.h: Likewise.
916 * pdp11.h: Likewise.
917 * pj.h: Likewise.
918 * pn.h: Likewise.
919 * ppc.h: Likewise.
920 * pyr.h: Likewise.
921 * rx.h: Likewise.
922 * s390.h: Likewise.
923 * score-datadep.h: Likewise.
924 * score-inst.h: Likewise.
925 * sparc.h: Likewise.
926 * spu-insns.h: Likewise.
927 * spu.h: Likewise.
928 * tic30.h: Likewise.
929 * tic4x.h: Likewise.
930 * tic54x.h: Likewise.
931 * tic80.h: Likewise.
932 * v850.h: Likewise.
933 * vax.h: Likewise.
935 2010-03-25 Joseph Myers <joseph@codesourcery.com>
937 * tic6x-control-registers.h, tic6x-insn-formats.h,
938 tic6x-opcode-table.h, tic6x.h: New.
940 2010-02-25 Wu Zhangjin <wuzhangjin@gmail.com>
942 * mips.h: (LOONGSON2F_NOP_INSN): New macro.
944 2010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
946 * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
948 2010-01-14 H.J. Lu <hongjiu.lu@intel.com>
950 * ia64.h (ia64_find_opcode): Remove argument name.
951 (ia64_find_next_opcode): Likewise.
952 (ia64_dis_opcode): Likewise.
953 (ia64_free_opcode): Likewise.
954 (ia64_find_dependency): Likewise.
956 2009-11-22 Doug Evans <dje@sebabeach.org>
958 * cgen.h: Include bfd_stdint.h.
959 (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
961 2009-11-18 Paul Brook <paul@codesourcery.com>
963 * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
965 2009-11-17 Paul Brook <paul@codesourcery.com>
966 Daniel Jacobowitz <dan@codesourcery.com>
968 * arm.h (ARM_EXT_V6_DSP): Define.
969 (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
970 (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
972 2009-11-04 DJ Delorie <dj@redhat.com>
974 * rx.h (rx_decode_opcode) (mvtipl): Add.
975 (mvtcp, mvfcp, opecp): Remove.
977 2009-11-02 Paul Brook <paul@codesourcery.com>
979 * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
980 FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
981 (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
982 FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
983 FPU_ARCH_NEON_VFP_V4): Define.
985 2009-10-23 Doug Evans <dje@sebabeach.org>
987 * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
988 * cgen.h: Update. Improve multi-inclusion macro name.
990 2009-10-02 Peter Bergner <bergner@vnet.ibm.com>
992 * ppc.h (PPC_OPCODE_476): Define.
994 2009-10-01 Peter Bergner <bergner@vnet.ibm.com>
996 * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
998 2009-09-29 DJ Delorie <dj@redhat.com>
1000 * rx.h: New file.
1002 2009-09-22 Peter Bergner <bergner@vnet.ibm.com>
1004 * ppc.h (ppc_cpu_t): Typedef to uint64_t.
1006 2009-09-21 Ben Elliston <bje@au.ibm.com>
1008 * ppc.h (PPC_OPCODE_PPCA2): New.
1010 2009-09-05 Martin Thuresson <martin@mtme.org>
1012 * ia64.h (struct ia64_operand): Renamed member class to op_class.
1014 2009-08-29 Martin Thuresson <martin@mtme.org>
1016 * tic30.h (template): Rename type template to
1017 insn_template. Updated code to use new name.
1018 * tic54x.h (template): Rename type template to
1019 insn_template.
1021 2009-08-20 Nick Hudson <nick.hudson@gmx.co.uk>
1023 * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
1025 2009-06-11 Anthony Green <green@moxielogic.com>
1027 * moxie.h (MOXIE_F3_PCREL): Define.
1028 (moxie_form3_opc_info): Grow.
1030 2009-06-06 Anthony Green <green@moxielogic.com>
1032 * moxie.h (MOXIE_F1_M): Define.
1034 2009-04-15 Anthony Green <green@moxielogic.com>
1036 * moxie.h: Created.
1038 2009-04-06 DJ Delorie <dj@redhat.com>
1040 * h8300.h: Add relaxation attributes to MOVA opcodes.
1042 2009-03-10 Alan Modra <amodra@bigpond.net.au>
1044 * ppc.h (ppc_parse_cpu): Declare.
1046 2009-03-02 Qinwei <qinwei@sunnorth.com.cn>
1048 * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
1049 and _IMM11 for mbitclr and mbitset.
1050 * score-datadep.h: Update dependency information.
1052 2009-02-26 Peter Bergner <bergner@vnet.ibm.com>
1054 * ppc.h (PPC_OPCODE_POWER7): New.
1056 2009-02-06 Doug Evans <dje@google.com>
1058 * i386.h: Add comment regarding sse* insns and prefixes.
1060 2009-02-03 Sandip Matte <sandip@rmicorp.com>
1062 * mips.h (INSN_XLR): Define.
1063 (INSN_CHIP_MASK): Update.
1064 (CPU_XLR): Define.
1065 (OPCODE_IS_MEMBER): Update.
1066 (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
1068 2009-01-28 Doug Evans <dje@google.com>
1070 * opcode/i386.h: Add multiple inclusion protection.
1071 (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
1072 (EDI_REG_NUM): New macros.
1073 (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
1074 (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
1075 (REX_PREFIX_P): New macro.
1077 2009-01-09 Peter Bergner <bergner@vnet.ibm.com>
1079 * ppc.h (struct powerpc_opcode): New field "deprecated".
1080 (PPC_OPCODE_NOPOWER4): Delete.
1082 2008-11-28 Joshua Kinard <kumba@gentoo.org>
1084 * mips.h: Define CPU_R14000, CPU_R16000.
1085 (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
1087 2008-11-18 Catherine Moore <clm@codesourcery.com>
1089 * arm.h (FPU_NEON_FP16): New.
1090 (FPU_ARCH_NEON_FP16): New.
1092 2008-11-06 Chao-ying Fu <fu@mips.com>
1094 * mips.h: Doucument '1' for 5-bit sync type.
1096 2008-08-28 H.J. Lu <hongjiu.lu@intel.com>
1098 * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update
1099 IA64_RS_CR.
1101 2008-08-01 Peter Bergner <bergner@vnet.ibm.com>
1103 * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
1105 2008-07-30 Michael J. Eager <eager@eagercon.com>
1107 * ppc.h (PPC_OPCODE_405): Define.
1108 (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
1110 2008-06-13 Peter Bergner <bergner@vnet.ibm.com>
1112 * ppc.h (ppc_cpu_t): New typedef.
1113 (struct powerpc_opcode <flags>): Use it.
1114 (struct powerpc_operand <insert, extract>): Likewise.
1115 (struct powerpc_macro <flags>): Likewise.
1117 2008-06-12 Adam Nemet <anemet@caviumnetworks.com>
1119 * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
1120 Update comment before MIPS16 field descriptors to mention MIPS16.
1121 (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
1122 BBIT.
1123 (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
1124 New bit masks and shift counts for cins and exts.
1126 * mips.h: Document new field descriptors +Q.
1127 (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
1129 2008-04-28 Adam Nemet <anemet@caviumnetworks.com>
1131 * mips.h (INSN_MACRO): Move it up to the pinfo macros.
1132 (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
1134 2008-04-14 Edmar Wienskoski <edmar@freescale.com>
1136 * ppc.h: (PPC_OPCODE_E500MC): New.
1138 2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
1140 * i386.h (MAX_OPERANDS): Set to 5.
1141 (MAX_MNEM_SIZE): Changed to 20.
1143 2008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
1145 * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
1147 2008-03-09 Paul Brook <paul@codesourcery.com>
1149 * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
1151 2008-03-04 Paul Brook <paul@codesourcery.com>
1153 * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
1154 (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
1155 (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
1157 2008-02-27 Denis Vlasenko <vda.linux@googlemail.com>
1158 Nick Clifton <nickc@redhat.com>
1160 PR 3134
1161 * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
1162 with a 32-bit displacement but without the top bit of the 4th byte
1163 set.
1165 2008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
1167 * cr16.h (cr16_num_optab): Declared.
1169 2008-02-14 Hakan Ardo <hakan@debian.org>
1171 PR gas/2626
1172 * avr.h (AVR_ISA_2xxe): Define.
1174 2008-02-04 Adam Nemet <anemet@caviumnetworks.com>
1176 * mips.h: Update copyright.
1177 (INSN_CHIP_MASK): New macro.
1178 (INSN_OCTEON): New macro.
1179 (CPU_OCTEON): New macro.
1180 (OPCODE_IS_MEMBER): Handle Octeon instructions.
1182 2008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
1184 * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
1186 2008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
1188 * avr.h (AVR_ISA_USB162): Add new opcode set.
1189 (AVR_ISA_AVR3): Likewise.
1191 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1193 * mips.h (INSN_LOONGSON_2E): New.
1194 (INSN_LOONGSON_2F): New.
1195 (CPU_LOONGSON_2E): New.
1196 (CPU_LOONGSON_2F): New.
1197 (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
1199 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1201 * mips.h (INSN_ISA*): Redefine certain values as an
1202 enumeration. Update comments.
1203 (mips_isa_table): New.
1204 (ISA_MIPS*): Redefine to match enumeration.
1205 (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
1206 values.
1208 2007-08-08 Ben Elliston <bje@au.ibm.com>
1210 * ppc.h (PPC_OPCODE_PPCPS): New.
1212 2007-07-03 Nathan Sidwell <nathan@codesourcery.com>
1214 * m68k.h: Document j K & E.
1216 2007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
1218 * cr16.h: New file for CR16 target.
1220 2007-05-02 Alan Modra <amodra@bigpond.net.au>
1222 * ppc.h (PPC_OPERAND_PLUS1): Update comment.
1224 2007-04-23 Nathan Sidwell <nathan@codesourcery.com>
1226 * m68k.h (mcfisa_c): New.
1227 (mcfusp, mcf_mask): Adjust.
1229 2007-04-20 Alan Modra <amodra@bigpond.net.au>
1231 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
1232 (num_powerpc_operands): Declare.
1233 (PPC_OPERAND_SIGNED et al): Redefine as hex.
1234 (PPC_OPERAND_PLUS1): Define.
1236 2007-03-21 H.J. Lu <hongjiu.lu@intel.com>
1238 * i386.h (REX_MODE64): Renamed to ...
1239 (REX_W): This.
1240 (REX_EXTX): Renamed to ...
1241 (REX_R): This.
1242 (REX_EXTY): Renamed to ...
1243 (REX_X): This.
1244 (REX_EXTZ): Renamed to ...
1245 (REX_B): This.
1247 2007-03-15 H.J. Lu <hongjiu.lu@intel.com>
1249 * i386.h: Add entries from config/tc-i386.h and move tables
1250 to opcodes/i386-opc.h.
1252 2007-03-13 H.J. Lu <hongjiu.lu@intel.com>
1254 * i386.h (FloatDR): Removed.
1255 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
1257 2007-03-01 Alan Modra <amodra@bigpond.net.au>
1259 * spu-insns.h: Add soma double-float insns.
1261 2007-02-20 Thiemo Seufer <ths@mips.com>
1262 Chao-Ying Fu <fu@mips.com>
1264 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
1265 (INSN_DSPR2): Add flag for DSP R2 instructions.
1266 (M_BALIGN): New macro.
1268 2007-02-14 Alan Modra <amodra@bigpond.net.au>
1270 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
1271 and Seg3ShortFrom with Shortform.
1273 2007-02-11 H.J. Lu <hongjiu.lu@intel.com>
1275 PR gas/4027
1276 * i386.h (i386_optab): Put the real "test" before the pseudo
1277 one.
1279 2007-01-08 Kazu Hirata <kazu@codesourcery.com>
1281 * m68k.h (m68010up): OR fido_a.
1283 2006-12-25 Kazu Hirata <kazu@codesourcery.com>
1285 * m68k.h (fido_a): New.
1287 2006-12-24 Kazu Hirata <kazu@codesourcery.com>
1289 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
1290 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
1291 values.
1293 2006-11-08 H.J. Lu <hongjiu.lu@intel.com>
1295 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
1297 2006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
1299 * score-inst.h (enum score_insn_type): Add Insn_internal.
1301 2006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
1302 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
1303 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
1304 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
1305 Alan Modra <amodra@bigpond.net.au>
1307 * spu-insns.h: New file.
1308 * spu.h: New file.
1310 2006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
1312 * ppc.h (PPC_OPCODE_CELL): Define.
1314 2006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1316 * i386.h : Modify opcode to support for the change in POPCNT opcode
1317 in amdfam10 architecture.
1319 2006-09-28 H.J. Lu <hongjiu.lu@intel.com>
1321 * i386.h: Replace CpuMNI with CpuSSSE3.
1323 2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
1324 Joseph Myers <joseph@codesourcery.com>
1325 Ian Lance Taylor <ian@wasabisystems.com>
1326 Ben Elliston <bje@wasabisystems.com>
1328 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
1330 2006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
1332 * score-datadep.h: New file.
1333 * score-inst.h: New file.
1335 2006-07-14 H.J. Lu <hongjiu.lu@intel.com>
1337 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
1338 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
1339 movdq2q and movq2dq.
1341 2006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1342 Michael Meissner <michael.meissner@amd.com>
1344 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
1346 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1348 * i386.h (i386_optab): Add "nop" with memory reference.
1350 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1352 * i386.h (i386_optab): Update comment for 64bit NOP.
1354 2006-06-06 Ben Elliston <bje@au.ibm.com>
1355 Anton Blanchard <anton@samba.org>
1357 * ppc.h (PPC_OPCODE_POWER6): Define.
1358 Adjust whitespace.
1360 2006-06-05 Thiemo Seufer <ths@mips.com>
1362 * mips.h: Improve description of MT flags.
1364 2006-05-25 Richard Sandiford <richard@codesourcery.com>
1366 * m68k.h (mcf_mask): Define.
1368 2006-05-05 Thiemo Seufer <ths@mips.com>
1369 David Ung <davidu@mips.com>
1371 * mips.h (enum): Add macro M_CACHE_AB.
1373 2006-05-04 Thiemo Seufer <ths@mips.com>
1374 Nigel Stephens <nigel@mips.com>
1375 David Ung <davidu@mips.com>
1377 * mips.h: Add INSN_SMARTMIPS define.
1379 2006-04-30 Thiemo Seufer <ths@mips.com>
1380 David Ung <davidu@mips.com>
1382 * mips.h: Defines udi bits and masks. Add description of
1383 characters which may appear in the args field of udi
1384 instructions.
1386 2006-04-26 Thiemo Seufer <ths@networkno.de>
1388 * mips.h: Improve comments describing the bitfield instruction
1389 fields.
1391 2006-04-26 Julian Brown <julian@codesourcery.com>
1393 * arm.h (FPU_VFP_EXT_V3): Define constant.
1394 (FPU_NEON_EXT_V1): Likewise.
1395 (FPU_VFP_HARD): Update.
1396 (FPU_VFP_V3): Define macro.
1397 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
1399 2006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
1401 * avr.h (AVR_ISA_PWMx): New.
1403 2006-03-28 Nathan Sidwell <nathan@codesourcery.com>
1405 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
1406 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
1407 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
1408 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
1409 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
1411 2006-03-10 Paul Brook <paul@codesourcery.com>
1413 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
1415 2006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1417 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
1418 first. Correct mask of bb "B" opcode.
1420 2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
1422 * i386.h (i386_optab): Support Intel Merom New Instructions.
1424 2006-02-24 Paul Brook <paul@codesourcery.com>
1426 * arm.h: Add V7 feature bits.
1428 2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
1430 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
1432 2006-01-31 Paul Brook <paul@codesourcery.com>
1433 Richard Earnshaw <rearnsha@arm.com>
1435 * arm.h: Use ARM_CPU_FEATURE.
1436 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
1437 (arm_feature_set): Change to a structure.
1438 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
1439 ARM_FEATURE): New macros.
1441 2005-12-07 Hans-Peter Nilsson <hp@axis.com>
1443 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
1444 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
1445 (ADD_PC_INCR_OPCODE): Don't define.
1447 2005-12-06 H.J. Lu <hongjiu.lu@intel.com>
1449 PR gas/1874
1450 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
1452 2005-11-14 David Ung <davidu@mips.com>
1454 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
1455 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
1456 save/restore encoding of the args field.
1458 2005-10-28 Dave Brolley <brolley@redhat.com>
1460 Contribute the following changes:
1461 2005-02-16 Dave Brolley <brolley@redhat.com>
1463 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
1464 cgen_isa_mask_* to cgen_bitset_*.
1465 * cgen.h: Likewise.
1467 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
1469 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
1470 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
1471 (CGEN_CPU_TABLE): Make isas a ponter.
1473 2003-09-29 Dave Brolley <brolley@redhat.com>
1475 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
1476 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
1477 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
1479 2002-12-13 Dave Brolley <brolley@redhat.com>
1481 * cgen.h (symcat.h): #include it.
1482 (cgen-bitset.h): #include it.
1483 (CGEN_ATTR_VALUE_TYPE): Now a union.
1484 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
1485 (CGEN_ATTR_ENTRY): 'value' now unsigned.
1486 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
1487 * cgen-bitset.h: New file.
1489 2005-09-30 Catherine Moore <clm@cm00re.com>
1491 * bfin.h: New file.
1493 2005-10-24 Jan Beulich <jbeulich@novell.com>
1495 * ia64.h (enum ia64_opnd): Move memory operand out of set of
1496 indirect operands.
1498 2005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1500 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
1501 Add FLAG_STRICT to pa10 ftest opcode.
1503 2005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1505 * hppa.h (pa_opcodes): Remove lha entries.
1507 2005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1509 * hppa.h (FLAG_STRICT): Revise comment.
1510 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
1511 before corresponding pa11 opcodes. Add strict pa10 register-immediate
1512 entries for "fdc".
1514 2005-09-30 Catherine Moore <clm@cm00re.com>
1516 * bfin.h: New file.
1518 2005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1520 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
1522 2005-09-06 Chao-ying Fu <fu@mips.com>
1524 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
1525 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
1526 define.
1527 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
1528 (INSN_ASE_MASK): Update to include INSN_MT.
1529 (INSN_MT): New define for MT ASE.
1531 2005-08-25 Chao-ying Fu <fu@mips.com>
1533 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
1534 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
1535 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
1536 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
1537 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
1538 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
1539 instructions.
1540 (INSN_DSP): New define for DSP ASE.
1542 2005-08-18 Alan Modra <amodra@bigpond.net.au>
1544 * a29k.h: Delete.
1546 2005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
1548 * ppc.h (PPC_OPCODE_E300): Define.
1550 2005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
1552 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
1554 2005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1556 PR gas/336
1557 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
1558 and pitlb.
1560 2005-07-27 Jan Beulich <jbeulich@novell.com>
1562 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
1563 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
1564 Add movq-s as 64-bit variants of movd-s.
1566 2005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1568 * hppa.h: Fix punctuation in comment.
1570 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
1571 implicit space-register addressing. Set space-register bits on opcodes
1572 using implicit space-register addressing. Add various missing pa20
1573 long-immediate opcodes. Remove various opcodes using implicit 3-bit
1574 space-register addressing. Use "fE" instead of "fe" in various
1575 fstw opcodes.
1577 2005-07-18 Jan Beulich <jbeulich@novell.com>
1579 * i386.h (i386_optab): Operands of aam and aad are unsigned.
1581 2007-07-15 H.J. Lu <hongjiu.lu@intel.com>
1583 * i386.h (i386_optab): Support Intel VMX Instructions.
1585 2005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1587 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
1589 2005-07-05 Jan Beulich <jbeulich@novell.com>
1591 * i386.h (i386_optab): Add new insns.
1593 2005-07-01 Nick Clifton <nickc@redhat.com>
1595 * sparc.h: Add typedefs to structure declarations.
1597 2005-06-20 H.J. Lu <hongjiu.lu@intel.com>
1599 PR 1013
1600 * i386.h (i386_optab): Update comments for 64bit addressing on
1601 mov. Allow 64bit addressing for mov and movq.
1603 2005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1605 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
1606 respectively, in various floating-point load and store patterns.
1608 2005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1610 * hppa.h (FLAG_STRICT): Correct comment.
1611 (pa_opcodes): Update load and store entries to allow both PA 1.X and
1612 PA 2.0 mneumonics when equivalent. Entries with cache control
1613 completers now require PA 1.1. Adjust whitespace.
1615 2005-05-19 Anton Blanchard <anton@samba.org>
1617 * ppc.h (PPC_OPCODE_POWER5): Define.
1619 2005-05-10 Nick Clifton <nickc@redhat.com>
1621 * Update the address and phone number of the FSF organization in
1622 the GPL notices in the following files:
1623 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
1624 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
1625 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
1626 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
1627 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
1628 tic54x.h, tic80.h, v850.h, vax.h
1630 2005-05-09 Jan Beulich <jbeulich@novell.com>
1632 * i386.h (i386_optab): Add ht and hnt.
1634 2005-04-18 Mark Kettenis <kettenis@gnu.org>
1636 * i386.h: Insert hyphens into selected VIA PadLock extensions.
1637 Add xcrypt-ctr. Provide aliases without hyphens.
1639 2005-04-13 H.J. Lu <hongjiu.lu@intel.com>
1641 Moved from ../ChangeLog
1643 2005-04-12 Paul Brook <paul@codesourcery.com>
1644 * m88k.h: Rename psr macros to avoid conflicts.
1646 2005-03-12 Zack Weinberg <zack@codesourcery.com>
1647 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
1648 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
1649 and ARM_ARCH_V6ZKT2.
1651 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
1652 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
1653 Remove redundant instruction types.
1654 (struct argument): X_op - new field.
1655 (struct cst4_entry): Remove.
1656 (no_op_insn): Declare.
1658 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
1659 * crx.h (enum argtype): Rename types, remove unused types.
1661 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
1662 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
1663 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
1664 (enum operand_type): Rearrange operands, edit comments.
1665 replace us<N> with ui<N> for unsigned immediate.
1666 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
1667 displacements (respectively).
1668 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
1669 (instruction type): Add NO_TYPE_INS.
1670 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
1671 (operand_entry): New field - 'flags'.
1672 (operand flags): New.
1674 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
1675 * crx.h (operand_type): Remove redundant types i3, i4,
1676 i5, i8, i12.
1677 Add new unsigned immediate types us3, us4, us5, us16.
1679 2005-04-12 Mark Kettenis <kettenis@gnu.org>
1681 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
1682 adjust them accordingly.
1684 2005-04-01 Jan Beulich <jbeulich@novell.com>
1686 * i386.h (i386_optab): Add rdtscp.
1688 2005-03-29 H.J. Lu <hongjiu.lu@intel.com>
1690 * i386.h (i386_optab): Don't allow the `l' suffix for moving
1691 between memory and segment register. Allow movq for moving between
1692 general-purpose register and segment register.
1694 2005-02-09 Jan Beulich <jbeulich@novell.com>
1696 PR gas/707
1697 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
1698 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
1699 fnstsw.
1701 2006-02-07 Nathan Sidwell <nathan@codesourcery.com>
1703 * m68k.h (m68008, m68ec030, m68882): Remove.
1704 (m68k_mask): New.
1705 (cpu_m68k, cpu_cf): New.
1706 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
1707 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
1709 2005-01-25 Alexandre Oliva <aoliva@redhat.com>
1711 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
1712 * cgen.h (enum cgen_parse_operand_type): Add
1713 CGEN_PARSE_OPERAND_SYMBOLIC.
1715 2005-01-21 Fred Fish <fnf@specifixinc.com>
1717 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
1718 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
1719 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
1721 2005-01-19 Fred Fish <fnf@specifixinc.com>
1723 * mips.h (struct mips_opcode): Add new pinfo2 member.
1724 (INSN_ALIAS): New define for opcode table entries that are
1725 specific instances of another entry, such as 'move' for an 'or'
1726 with a zero operand.
1727 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
1728 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
1730 2004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
1732 * mips.h (CPU_RM9000): Define.
1733 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
1735 2004-11-25 Jan Beulich <jbeulich@novell.com>
1737 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
1738 to/from test registers are illegal in 64-bit mode. Add missing
1739 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
1740 (previously one had to explicitly encode a rex64 prefix). Re-enable
1741 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
1742 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
1744 2004-11-23 Jan Beulich <jbeulich@novell.com>
1746 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
1747 available only with SSE2. Change the MMX additions introduced by SSE
1748 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
1749 instructions by their now designated identifier (since combining i686
1750 and 3DNow! does not really imply 3DNow!A).
1752 2004-11-19 Alan Modra <amodra@bigpond.net.au>
1754 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
1755 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
1757 2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
1758 Vineet Sharma <vineets@noida.hcltech.com>
1760 * maxq.h: New file: Disassembly information for the maxq port.
1762 2004-11-05 H.J. Lu <hongjiu.lu@intel.com>
1764 * i386.h (i386_optab): Put back "movzb".
1766 2004-11-04 Hans-Peter Nilsson <hp@axis.com>
1768 * cris.h (enum cris_insn_version_usage): Tweak formatting and
1769 comments. Remove member cris_ver_sim. Add members
1770 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
1771 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
1772 (struct cris_support_reg, struct cris_cond15): New types.
1773 (cris_conds15): Declare.
1774 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
1775 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
1776 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
1777 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
1778 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
1779 SIZE_FIELD_UNSIGNED.
1781 2004-11-04 Jan Beulich <jbeulich@novell.com>
1783 * i386.h (sldx_Suf): Remove.
1784 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
1785 (q_FP): Define, implying no REX64.
1786 (x_FP, sl_FP): Imply FloatMF.
1787 (i386_optab): Split reg and mem forms of moving from segment registers
1788 so that the memory forms can ignore the 16-/32-bit operand size
1789 distinction. Adjust a few others for Intel mode. Remove *FP uses from
1790 all non-floating-point instructions. Unite 32- and 64-bit forms of
1791 movsx, movzx, and movd. Adjust floating point operations for the above
1792 changes to the *FP macros. Add DefaultSize to floating point control
1793 insns operating on larger memory ranges. Remove left over comments
1794 hinting at certain insns being Intel-syntax ones where the ones
1795 actually meant are already gone.
1797 2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
1799 * crx.h: Add COPS_REG_INS - Coprocessor Special register
1800 instruction type.
1802 2004-09-30 Paul Brook <paul@codesourcery.com>
1804 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
1805 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
1807 2004-09-11 Theodore A. Roth <troth@openavr.org>
1809 * avr.h: Add support for
1810 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
1812 2004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
1814 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
1816 2004-08-24 Dmitry Diky <diwil@spec.ru>
1818 * msp430.h (msp430_opc): Add new instructions.
1819 (msp430_rcodes): Declare new instructions.
1820 (msp430_hcodes): Likewise..
1822 2004-08-13 Nick Clifton <nickc@redhat.com>
1824 PR/301
1825 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
1826 processors.
1828 2004-08-30 Michal Ludvig <mludvig@suse.cz>
1830 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
1832 2004-07-22 H.J. Lu <hongjiu.lu@intel.com>
1834 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
1836 2004-07-21 Jan Beulich <jbeulich@novell.com>
1838 * i386.h: Adjust instruction descriptions to better match the
1839 specification.
1841 2004-07-16 Richard Earnshaw <rearnsha@arm.com>
1843 * arm.h: Remove all old content. Replace with architecture defines
1844 from gas/config/tc-arm.c.
1846 2004-07-09 Andreas Schwab <schwab@suse.de>
1848 * m68k.h: Fix comment.
1850 2004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
1852 * crx.h: New file.
1854 2004-06-24 Alan Modra <amodra@bigpond.net.au>
1856 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
1858 2004-05-24 Peter Barada <peter@the-baradas.com>
1860 * m68k.h: Add 'size' to m68k_opcode.
1862 2004-05-05 Peter Barada <peter@the-baradas.com>
1864 * m68k.h: Switch from ColdFire chip name to core variant.
1866 2004-04-22 Peter Barada <peter@the-baradas.com>
1868 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
1869 descriptions for new EMAC cases.
1870 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
1871 handle Motorola MAC syntax.
1872 Allow disassembly of ColdFire V4e object files.
1874 2004-03-16 Alan Modra <amodra@bigpond.net.au>
1876 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
1878 2004-03-12 Jakub Jelinek <jakub@redhat.com>
1880 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
1882 2004-03-12 Michal Ludvig <mludvig@suse.cz>
1884 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
1886 2004-03-12 Michal Ludvig <mludvig@suse.cz>
1888 * i386.h (i386_optab): Added xstore/xcrypt insns.
1890 2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
1892 * h8300.h (32bit ldc/stc): Add relaxing support.
1894 2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
1896 * h8300.h (BITOP): Pass MEMRELAX flag.
1898 2004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
1900 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
1901 except for the H8S.
1903 For older changes see ChangeLog-9103
1904 \f
1905 Copyright (C) 2004-2012 Free Software Foundation, Inc.
1907 Copying and distribution of this file, with or without modification,
1908 are permitted in any medium without royalty provided the copyright
1909 notice and this notice are preserved.
1911 Local Variables:
1912 mode: change-log
1913 left-margin: 8
1914 fill-column: 74
1915 version-control: never
1916 End: