include/opcode/i370.h

   1 /* i370.h -- Header file for S/390 opcode table
   2    Copyright 1994, 1995, 1998, 1999, 2000, 2003, 2010
   3    Free Software Foundation, Inc.
   4    PowerPC version written by Ian Lance Taylor, Cygnus Support
   5    Rewritten for i370 ESA/390 support, Linas Vepstas <linas@linas.org>
   6
   7    This file is part of GDB, GAS, and the GNU binutils.
   8
   9    GDB, GAS, and the GNU binutils are free software; you can redistribute
  10    them and/or modify them under the terms of the GNU General Public
  11    License as published by the Free Software Foundation; either version 3,
  12    or (at your option) any later version.
  13
  14    GDB, GAS, and the GNU binutils are distributed in the hope that they
  15    will be useful, but WITHOUT ANY WARRANTY; without even the implied
  16    warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
  17    the GNU General Public License for more details.
  18
  19    You should have received a copy of the GNU General Public License
  20    along with this file; see the file COPYING3.  If not, write to the Free
  21    Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
  22    MA 02110-1301, USA.  */
  23
  24 #ifndef I370_H
  25 #define I370_H
  26
  27 /* The opcode table is an array of struct i370_opcode.  */
  28 typedef union
  29 {
  30    unsigned int   i[2];
  31    unsigned short s[4];
  32    unsigned char  b[8];
  33 }  i370_insn_t;
  34
  35 struct i370_opcode
  36 {
  37   /* The opcode name.  */
  38   const char *name;
  39
  40   /* the length of the instruction */
  41   char len;
  42
  43   /* The opcode itself.  Those bits which will be filled in with
  44      operands are zeroes.  */
  45   i370_insn_t opcode;
  46
  47   /* The opcode mask.  This is used by the disassembler.  This is a
  48      mask containing ones indicating those bits which must match the
  49      opcode field, and zeroes indicating those bits which need not
  50      match (and are presumably filled in by operands).  */
  51   i370_insn_t mask;
  52
  53   /* One bit flags for the opcode.  These are used to indicate which
  54      specific processors support the instructions.  The defined values
  55      are listed below.  */
  56   unsigned long flags;
  57
  58   /* An array of operand codes.  Each code is an index into the
  59      operand table.  They appear in the order which the operands must
  60      appear in assembly code, and are terminated by a zero.  */
  61   unsigned char operands[8];
  62 };
  63
  64 /* The table itself is sorted by major opcode number, and is otherwise
  65    in the order in which the disassembler should consider
  66    instructions.  */
  67 extern const struct i370_opcode i370_opcodes[];
  68 extern const int i370_num_opcodes;
  69
  70 /* Values defined for the flags field of a struct i370_opcode.  */
  71
  72 /* Opcode is defined for the original 360 architecture.  */
  73 #define I370_OPCODE_360 (0x01)
  74
  75 /* Opcode is defined for the 370 architecture.  */
  76 #define I370_OPCODE_370 (0x02)
  77
  78 /* Opcode is defined for the 370-XA architecture.  */
  79 #define I370_OPCODE_370_XA (0x04)
  80
  81 /* Opcode is defined for the ESA/370 architecture.  */
  82 #define I370_OPCODE_ESA370 (0x08)
  83
  84 /* Opcode is defined for the ESA/390 architecture.  */
  85 #define I370_OPCODE_ESA390 (0x10)
  86
  87 /* Opcode is defined for the ESA/390 w/ BFP facility.  */
  88 #define I370_OPCODE_ESA390_BF (0x20)
  89
  90 /* Opcode is defined for the ESA/390 w/ branch & set authority facility.  */
  91 #define I370_OPCODE_ESA390_BS (0x40)
  92
  93 /* Opcode is defined for the ESA/390 w/ checksum facility.  */
  94 #define I370_OPCODE_ESA390_CK (0x80)
  95
  96 /* Opcode is defined for the ESA/390 w/ compare & move extended facility.  */
  97 #define I370_OPCODE_ESA390_CM (0x100)
  98
  99 /* Opcode is defined for the ESA/390 w/ flt.pt. support extensions facility. */
 100 #define I370_OPCODE_ESA390_FX (0x200)
 101
 102 /* Opcode is defined for the ESA/390 w/ HFP facility. */
 103 #define I370_OPCODE_ESA390_HX (0x400)
 104
 105 /* Opcode is defined for the ESA/390 w/ immediate & relative facility.  */
 106 #define I370_OPCODE_ESA390_IR (0x800)
 107
 108 /* Opcode is defined for the ESA/390 w/ move-inverse facility.  */
 109 #define I370_OPCODE_ESA390_MI (0x1000)
 110
 111 /* Opcode is defined for the ESA/390 w/ program-call-fast facility.  */
 112 #define I370_OPCODE_ESA390_PC (0x2000)
 113
 114 /* Opcode is defined for the ESA/390 w/ perform-locked-op facility.  */
 115 #define I370_OPCODE_ESA390_PL (0x4000)
 116
 117 /* Opcode is defined for the ESA/390 w/ square-root facility.  */
 118 #define I370_OPCODE_ESA390_QR (0x8000)
 119
 120 /* Opcode is defined for the ESA/390 w/ resume-program facility.  */
 121 #define I370_OPCODE_ESA390_RP (0x10000)
 122
 123 /* Opcode is defined for the ESA/390 w/ set-address-space-fast facility.  */
 124 #define I370_OPCODE_ESA390_SA (0x20000)
 125
 126 /* Opcode is defined for the ESA/390 w/ subspace group facility.  */
 127 #define I370_OPCODE_ESA390_SG (0x40000)
 128
 129 /* Opcode is defined for the ESA/390 w/ string facility.  */
 130 #define I370_OPCODE_ESA390_SR (0x80000)
 131
 132 /* Opcode is defined for the ESA/390 w/ trap facility.  */
 133 #define I370_OPCODE_ESA390_TR (0x100000)
 134
 135 #define I370_OPCODE_ESA390_SUPERSET (0x1fffff)
 136
 137 \f
 138 /* The operands table is an array of struct i370_operand.  */
 139
 140 struct i370_operand
 141 {
 142   /* The number of bits in the operand.  */
 143   int bits;
 144
 145   /* How far the operand is left shifted in the instruction.  */
 146   int shift;
 147
 148   /* Insertion function.  This is used by the assembler.  To insert an
 149      operand value into an instruction, check this field.
 150
 151      If it is NULL, execute
 152          i |= (op & ((1 << o->bits) - 1)) << o->shift;
 153      (i is the instruction which we are filling in, o is a pointer to
 154      this structure, and op is the opcode value; this assumes twos
 155      complement arithmetic).
 156
 157      If this field is not NULL, then simply call it with the
 158      instruction and the operand value.  It will return the new value
 159      of the instruction.  If the ERRMSG argument is not NULL, then if
 160      the operand value is illegal, *ERRMSG will be set to a warning
 161      string (the operand will be inserted in any case).  If the
 162      operand value is legal, *ERRMSG will be unchanged (most operands
 163      can accept any value).  */
 164   i370_insn_t (*insert)
 165     (i370_insn_t instruction, long op, const char **errmsg);
 166
 167   /* Extraction function.  This is used by the disassembler.  To
 168      extract this operand type from an instruction, check this field.
 169
 170      If it is NULL, compute
 171          op = ((i) >> o->shift) & ((1 << o->bits) - 1);
 172          if ((o->flags & I370_OPERAND_SIGNED) != 0
 173            && (op & (1 << (o->bits - 1))) != 0)
 174            op -= 1 << o->bits;
 175      (i is the instruction, o is a pointer to this structure, and op
 176      is the result; this assumes twos complement arithmetic).
 177
 178      If this field is not NULL, then simply call it with the
 179      instruction value.  It will return the value of the operand.  If
 180      the INVALID argument is not NULL, *INVALID will be set to
 181      non-zero if this operand type can not actually be extracted from
 182      this operand (i.e., the instruction does not match).  If the
 183      operand is valid, *INVALID will not be changed.  */
 184   long (*extract) (i370_insn_t instruction, int *invalid);
 185
 186   /* One bit syntax flags.  */
 187   unsigned long flags;
 188
 189   /* name -- handy for debugging, otherwise pointless */
 190   char * name;
 191 };
 192
 193 /* Elements in the table are retrieved by indexing with values from
 194    the operands field of the i370_opcodes table.  */
 195
 196 extern const struct i370_operand i370_operands[];
 197
 198 /* Values defined for the flags field of a struct i370_operand.  */
 199
 200 /* This operand should be wrapped in parentheses rather than
 201    separated from the previous by a comma.  This is used for S, RS and
 202    SS form instructions which want their operands to look like
 203    reg,displacement(basereg) */
 204 #define I370_OPERAND_SBASE (0x01)
 205
 206 /* This operand is a base register.  It may or may not appear next
 207    to an index register, i.e. either of the two forms
 208    reg,displacement(basereg)
 209    reg,displacement(index,basereg) */
 210 #define I370_OPERAND_BASE (0x02)
 211
 212 /* This pair of operands should be wrapped in parentheses rather than
 213    separated from the last by a comma.  This is used for the RX form
 214    instructions which want their operands to look like
 215    reg,displacement(index,basereg) */
 216 #define I370_OPERAND_INDEX (0x04)
 217
 218 /* This operand names a register.  The disassembler uses this to print
 219    register names with a leading 'r'.  */
 220 #define I370_OPERAND_GPR (0x08)
 221
 222 /* This operand names a floating point register.  The disassembler
 223    prints these with a leading 'f'.  */
 224 #define I370_OPERAND_FPR (0x10)
 225
 226 /* This operand is a displacement.  */
 227 #define I370_OPERAND_RELATIVE (0x20)
 228
 229 /* This operand is a length, such as that in SS form instructions.  */
 230 #define I370_OPERAND_LENGTH (0x40)
 231
 232 /* This operand is optional, and is zero if omitted.  This is used for
 233    the optional B2 field in the shift-left, shift-right instructions.  The
 234    assembler must count the number of operands remaining on the line,
 235    and the number of operands remaining for the opcode, and decide
 236    whether this operand is present or not.  The disassembler should
 237    print this operand out only if it is not zero.  */
 238 #define I370_OPERAND_OPTIONAL (0x80)
 239
 240 \f
 241 /* Define some misc macros.  We keep them with the operands table
 242    for simplicity.  The macro table is an array of struct i370_macro.  */
 243
 244 struct i370_macro
 245 {
 246   /* The macro name.  */
 247   const char *name;
 248
 249   /* The number of operands the macro takes.  */
 250   unsigned int operands;
 251
 252   /* One bit flags for the opcode.  These are used to indicate which
 253      specific processors support the instructions.  The values are the
 254      same as those for the struct i370_opcode flags field.  */
 255   unsigned long flags;
 256
 257   /* A format string to turn the macro into a normal instruction.
 258      Each %N in the string is replaced with operand number N (zero
 259      based).  */
 260   const char *format;
 261 };
 262
 263 extern const struct i370_macro i370_macros[];
 264 extern const int i370_num_macros;
 265
 266
 267 #endif /* I370_H */