2 * Macros for asm code. AArch64 version.
4 * Copyright (c) 2019-2023, Arm Limited.
5 * SPDX-License-Identifier: MIT OR Apache-2.0 WITH LLVM-exception
11 /* Branch Target Identitication support. */
14 /* Return address signing support (pac-ret). */
15 #define PACIASP hint 25; .cfi_window_save
16 #define AUTIASP hint 29; .cfi_window_save
18 /* GNU_PROPERTY_AARCH64_* macros from elf.h. */
19 #define FEATURE_1_AND 0xc0000000
20 #define FEATURE_1_BTI 1
21 #define FEATURE_1_PAC 2
23 /* Add a NT_GNU_PROPERTY_TYPE_0 note. */
25 #define GNU_PROPERTY(type, value) \
26 .section .note.gnu.property, "a"; \
37 #define GNU_PROPERTY(type, value) \
38 .section .note.gnu.property, "a"; \
51 /* If set then the GNU Property Note section will be added to
52 mark objects to support BTI and PAC-RET. */
53 #ifndef WANT_GNU_PROPERTY
54 #define WANT_GNU_PROPERTY 1
58 /* Add property note with supported features to all asm files. */
59 GNU_PROPERTY (FEATURE_1_AND
, FEATURE_1_BTI
|FEATURE_1_PAC
)
62 #define ENTRY_ALIGN(name, alignment) \
64 .type name,%function; \
70 #define ENTRY(name) ENTRY_ALIGN(name, 6)
72 #define ENTRY_ALIAS(name) \
74 .type name,%function; \
84 /* Sanitize padding bits of pointer arguments as per aapcs64 */
85 #define PTR_ARG(n) mov w##n, w##n
91 /* Sanitize padding bits of size arguments as per aapcs64 */
92 #define SIZE_ARG(n) mov w##n, w##n
97 /* Compiler supports SVE instructions */
99 # if __aarch64__ && (__GNUC__ >= 8 || __clang_major__ >= 5)