newlib/libc/sys/arm/arm.h

   1 /*
   2  * Copyright (c) 2011 ARM Ltd
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright
  11  *    notice, this list of conditions and the following disclaimer in the
  12  *    documentation and/or other materials provided with the distribution.
  13  * 3. The name of the company may not be used to endorse or promote
  14  *    products derived from this software without specific prior written
  15  *    permission.
  16  *
  17  * THIS SOFTWARE IS PROVIDED BY ARM LTD ``AS IS'' AND ANY EXPRESS OR IMPLIED
  18  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  19  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  20  * IN NO EVENT SHALL ARM LTD BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
  22  * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
  23  * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
  24  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
  25  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  26  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 #ifndef _LIBGLOSS_ARM_H
  30 #define _LIBGLOSS_ARM_H
  31
  32 #include "arm-acle-compat.h"
  33
  34 /* Checking for targets supporting only Thumb instructions (eg. ARMv6-M) or
  35    supporting Thumb-2 instructions, whether ARM instructions are available or
  36    not, is done many times in libgloss/arm.  So factor it out and use
  37    PREFER_THUMB instead.  */
  38 #if __thumb2__ || (__thumb__ && !__ARM_ARCH_ISA_ARM)
  39 # define PREFER_THUMB
  40 #endif
  41
  42 /* Processor only capable of executing Thumb-1 instructions.  */
  43 #if __ARM_ARCH_ISA_THUMB == 1 && !__ARM_ARCH_ISA_ARM
  44 # define THUMB1_ONLY
  45 #endif
  46
  47 /* M profile architectures.  This is a different set of architectures than
  48    those not having ARM ISA because it does not contain ARMv7.  This macro is
  49    necessary to test which architectures use bkpt as semihosting interface from
  50    architectures using svc.  */
  51 #if !__ARM_ARCH_ISA_ARM && !__ARM_ARCH_7__
  52 # define THUMB_VXM
  53 #endif
  54
  55 /* Defined if this target supports the BLX Rm instruction.  */
  56 #if  !defined(__ARM_ARCH_2__)   \
  57   && !defined(__ARM_ARCH_3__)   \
  58   && !defined(__ARM_ARCH_3M__)  \
  59   && !defined(__ARM_ARCH_4__)   \
  60   && !defined(__ARM_ARCH_4T__)
  61 # define HAVE_CALL_INDIRECT
  62 #endif
  63
  64 /* A and R profiles (and legacy Arm).
  65         Current Program Status Register (CPSR)
  66         M[4:0]          Mode bits. M[4] is always 1 for 32-bit modes.
  67         T[5]                    1: Thumb, 0: ARM instruction set
  68         F[6]                    1: disables FIQ
  69         I[7]                    1: disables IRQ
  70         A[8]                    1: disables imprecise aborts
  71         E[9]                    0: Little-endian, 1: Big-endian
  72         J[24]                   1: Jazelle instruction set
  73  */
  74 #define CPSR_M_USR                      0x00    /* User mode.  */
  75 #define CPSR_M_FIQ                      0x01    /* Fast Interrupt mode.  */
  76 #define CPSR_M_IRQ                      0x02    /* Interrupt mode.  */
  77 #define CPSR_M_SVR                      0x03    /* Supervisor mode.  */
  78 #define CPSR_M_MON                      0x06    /* Monitor mode.  */
  79 #define CPSR_M_ABT                      0x07    /* Abort mode.  */
  80 #define CPSR_M_HYP                      0x0A    /* Hypervisor mode.  */
  81 #define CPSR_M_UND                      0x0B    /* Undefined mode.  */
  82 #define CPSR_M_SYS                      0x0F    /* System mode.  */
  83 #define CPSR_M_32BIT            0x10    /* 32-bit mode.  */
  84 #define CPSR_T_BIT                      0x20    /* Thumb bit.  */
  85 #define CPSR_F_MASK                     0x40    /* FIQ bit.  */
  86 #define CPSR_I_MASK                     0x80    /* IRQ bit.  */
  87
  88 #define CPSR_M_MASK                     0x0F    /* Mode mask except M[4].  */
  89
  90 #endif /* _LIBGLOSS_ARM_H */