newlib/libm/machine/riscv/feclearexcept.c

   1 /*
   2   (c) Copyright 2017 Michael R. Neilly
   3   All rights reserved.
   4
   5   Redistribution and use in source and binary forms, with or without
   6   modification, are permitted provided that the following conditions
   7   are met:
   8
   9   * Redistributions of source code must retain the above copyright
  10   notice, this list of conditions and the following disclaimer.
  11
  12   * Redistributions in binary form must reproduce the above copyright
  13   notice, this list of conditions and the following disclaimer in the
  14   documentation and/or other materials provided with the distribution.
  15
  16   * Neither the names of the copyright holders nor the names of their
  17   contributors may be used to endorse or promote products derived from
  18   this software without specific prior written permission.
  19
  20   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  21   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  22   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
  23   FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
  24   COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
  25   INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
  26   BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  27   LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  28   CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  29   LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
  30   ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  31   POSSIBILITY OF SUCH DAMAGE.
  32 */
  33
  34 #include <fenv.h>
  35 #include <stddef.h>
  36 #include "riscv_math.h"
  37
  38 /* This implementation is intended to comply with the following
  39  * specification:
  40  *
  41  * http://pubs.opengroup.org/onlinepubs/009695399/functions/feclearexcept.html
  42  * Referred to as 'feclearexcept.html below.
  43  *
  44  * "The feclearexcept() function shall attempt to clear the supported
  45  * floating-point exceptions represented by excepts."
  46  */
  47
  48 int feclearexcept(int excepts)
  49 {
  50
  51 #if __RISCV_HARD_FLOAT
  52
  53   /* Mask excepts to be sure only supported flag bits are set */
  54
  55   excepts &= FE_ALL_EXCEPT;
  56
  57   /* Per "The RISC-V Instruction Set Manual: Volume I: User-Level ISA:
  58    * Version 2.1":
  59    *
  60    * "The CSRRC (Atomic Read and Clear Bits in CSR) instruction reads
  61    * the value of the CSR, zeroextends the value to XLEN bits, and
  62    * writes it to integer register rd. The initial value in integer
  63    * register rs1 is treated as a bit mask that specifies bit
  64    * positions to be cleared in the CSR. Any bit that is high in rs1
  65    * will cause the corresponding bit to be cleared in the CSR, if
  66    * that CSR bit is writable. Other bits in the CSR are unaffected."
  67    */
  68
  69   /* Clear the requested flags */
  70
  71   asm volatile("csrrc zero, fflags, %0" : : "r"(excepts));
  72
  73   /* Per 'feclearexcept.html
  74    * "If the argument is zero or if all the specified exceptions were
  75    * successfully cleared, feclearexcept() shall return zero. Otherwise,
  76    * it shall return a non-zero value."
  77    */
  78
  79 #endif
  80
  81   return 0;
  82 }