2 ** Copyright 2002, Travis Geiselbrecht. All rights reserved.
3 ** Distributed under the terms of the NewOS License.
5 #include "stage2_priv.h"
10 #define MG_pagesize 10
11 #define MG_mon_stack 14
14 #define MG_inetntoa 54
15 #define MG_inputline 72
17 #define MG_alloc_base 232
18 #define MG_alloc_brk 236
19 #define MG_boot_dev 240
20 #define MG_boot_arg 244
21 #define MG_boot_info 248
22 #define MG_boot_file 252
23 #define MG_bootfile 256
24 #define MG_boot_how 320
26 #define MG_km_flags 368
27 #define MG_mon_init 370
36 #define MG_dmachip 404
37 #define MG_diskchip 408
38 #define MG_intrstat 412
39 #define MG_intrmask 416
40 #define MG_nofault 420
46 #define MG_cursor_save 470
48 #define MG_try_getc 730
51 #define MG_alert_confirm 742
53 #define MG_boot_slider 750
55 #define MG_event_high 758
56 #define MG_animate 762
57 #define MG_anim_time 766
58 #define MG_scsi_intr 770
59 #define MG_scsi_intrarg 774
62 #define MG_anim_run 782
64 #define MG_con_slot 844
65 #define MG_con_fbnum 845
66 #define MG_con_map_vaddr0 860
67 #define MG_con_map_vaddr1 872
68 #define MG_con_map_vaddr2 884
69 #define MG_con_map_vaddr3 896
70 #define MG_con_map_vaddr4 908
71 #define MG_con_map_vaddr5 920
73 #define MG_clientetheraddr 788
74 #define MG_machine_type 936
75 #define MG_board_rev 937
77 #define N_SIMM 4 /* number of SIMMs in machine */
80 #define SIMM_SIZE 0x03
81 #define SIMM_SIZE_EMPTY 0x00
82 #define SIMM_SIZE_16MB 0x01
83 #define SIMM_SIZE_4MB 0x02
84 #define SIMM_SIZE_1MB 0x03
85 #define SIMM_PAGE_MODE 0x04
86 #define SIMM_PARITY 0x08 /* ?? */
88 #define NEXT_RAMBASE 0x4000000
96 #define NeXT_TURBO_COLOR 5
98 typedef int (*getcptr
)(void);
99 typedef int (*putcptr
)(int);
101 #define MON(type, off) (*(type *)((unsigned int) (mg) + off))
105 int init_nextmon(char *monitor
)
112 int probe_memory(kernel_args
*ka
)
115 char machine_type
= MON(char,MG_machine_type
);
116 int msize1
, msize4
, msize16
;
118 /* depending on the machine, the bank layout is different */
119 dprintf("machine type: 0x%x\n", machine_type
);
120 switch(machine_type
) {
123 msize16
= 0x10000000;
133 case NeXT_TURBO_COLOR
:
144 /* start probing ram */
145 dprintf("memory probe:\n");
146 ka
->num_phys_mem_ranges
= 0;
147 for(i
=0; i
<N_SIMM
; i
++) {
148 char probe
= MON(char,MG_simm
+i
);
150 if((probe
& SIMM_SIZE
) != SIMM_SIZE_EMPTY
) {
151 ka
->phys_mem_range
[ka
->num_phys_mem_ranges
].start
= NEXT_RAMBASE
+ (msize16
* i
);
153 switch(probe
& SIMM_SIZE
) {
155 ka
->phys_mem_range
[ka
->num_phys_mem_ranges
].size
= msize16
;
158 ka
->phys_mem_range
[ka
->num_phys_mem_ranges
].size
= msize4
;
161 ka
->phys_mem_range
[ka
->num_phys_mem_ranges
].size
= msize1
;
164 dprintf("bank %i: start 0x%x, size 0x%x\n", i
,
165 ka
->phys_mem_range
[ka
->num_phys_mem_ranges
].start
, ka
->phys_mem_range
[ka
->num_phys_mem_ranges
].size
);
166 ka
->num_phys_mem_ranges
++;
169 dprintf("alloc_base: 0x%x\n", MON(int, MG_alloc_base
));
170 dprintf("alloc_brk: 0x%x\n", MON(int, MG_alloc_brk
));
171 dprintf("mon_stack: 0x%x\n", MON(int, MG_mon_stack
));
173 /* record allocated ram */
174 ka
->num_phys_alloc_ranges
= 1;
175 ka
->phys_alloc_range
[0].start
= ROUNDOWN(MON(int, MG_alloc_base
), PAGE_SIZE
);
182 MON(putcptr
,MG_putc
)(c
);
187 return(MON(getcptr
,MG_getc
)());