eth_ocm/eth_receivecontrol.v

   1 //////////////////////////////////////////////////////////////////////
   2 ////                                                              ////
   3 ////  eth_receivecontrol.v                                        ////
   4 ////                                                              ////
   5 ////  This file is part of the Ethernet IP core project           ////
   6 ////  http://www.opencores.org/projects/ethmac/                   ////
   7 ////                                                              ////
   8 ////  Author(s):                                                  ////
   9 ////      - Igor Mohor (igorM@opencores.org)                      ////
  10 ////                                                              ////
  11 ////  All additional information is avaliable in the Readme.txt   ////
  12 ////  file.                                                       ////
  13 ////                                                              ////
  14 //////////////////////////////////////////////////////////////////////
  15 ////                                                              ////
  16 //// Copyright (C) 2001 Authors                                   ////
  17 ////                                                              ////
  18 //// This source file may be used and distributed without         ////
  19 //// restriction provided that this copyright statement is not    ////
  20 //// removed from the file and that any derivative work contains  ////
  21 //// the original copyright notice and the associated disclaimer. ////
  22 ////                                                              ////
  23 //// This source file is free software; you can redistribute it   ////
  24 //// and/or modify it under the terms of the GNU Lesser General   ////
  25 //// Public License as published by the Free Software Foundation; ////
  26 //// either version 2.1 of the License, or (at your option) any   ////
  27 //// later version.                                               ////
  28 ////                                                              ////
  29 //// This source is distributed in the hope that it will be       ////
  30 //// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
  31 //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
  32 //// PURPOSE.  See the GNU Lesser General Public License for more ////
  33 //// details.                                                     ////
  34 ////                                                              ////
  35 //// You should have received a copy of the GNU Lesser General    ////
  36 //// Public License along with this source; if not, download it   ////
  37 //// from http://www.opencores.org/lgpl.shtml                     ////
  38 ////                                                              ////
  39 //////////////////////////////////////////////////////////////////////
  40 //
  41 // CVS Revision History
  42 //
  43 // $Log: eth_receivecontrol.v,v $
  44 // Revision 1.5  2003/01/22 13:49:26  tadejm
  45 // When control packets were received, they were ignored in some cases.
  46 //
  47 // Revision 1.4  2002/11/22 01:57:06  mohor
  48 // Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
  49 // synchronized.
  50 //
  51 // Revision 1.3  2002/01/23 10:28:16  mohor
  52 // Link in the header changed.
  53 //
  54 // Revision 1.2  2001/10/19 08:43:51  mohor
  55 // eth_timescale.v changed to timescale.v This is done because of the
  56 // simulation of the few cores in a one joined project.
  57 //
  58 // Revision 1.1  2001/08/06 14:44:29  mohor
  59 // A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
  60 // Include files fixed to contain no path.
  61 // File names and module names changed ta have a eth_ prologue in the name.
  62 // File eth_timescale.v is used to define timescale
  63 // All pin names on the top module are changed to contain _I, _O or _OE at the end.
  64 // Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
  65 // and Mdo_OE. The bidirectional signal must be created on the top level. This
  66 // is done due to the ASIC tools.
  67 //
  68 // Revision 1.1  2001/07/30 21:23:42  mohor
  69 // Directory structure changed. Files checked and joind together.
  70 //
  71 // Revision 1.1  2001/07/03 12:51:54  mohor
  72 // Initial release of the MAC Control module.
  73 //
  74 //
  75 //
  76 //
  77 //
  78
  79
  80 `include "timescale.v"
  81
  82
  83 module eth_receivecontrol (MTxClk, MRxClk, TxReset, RxReset, RxData, RxValid, RxStartFrm,
  84                            RxEndFrm, RxFlow, ReceiveEnd, MAC, DlyCrcEn, TxDoneIn,
  85                            TxAbortIn, TxStartFrmOut, ReceivedLengthOK, ReceivedPacketGood,
  86                            TxUsedDataOutDetected, Pause, ReceivedPauseFrm, AddressOK,
  87                            RxStatusWriteLatched_sync2, r_PassAll, SetPauseTimer
  88                           );
  89
  90 parameter Tp = 1;
  91
  92
  93 input       MTxClk;
  94 input       MRxClk;
  95 input       TxReset;
  96 input       RxReset;
  97 input [7:0] RxData;
  98 input       RxValid;
  99 input       RxStartFrm;
 100 input       RxEndFrm;
 101 input       RxFlow;
 102 input       ReceiveEnd;
 103 input [47:0]MAC;
 104 input       DlyCrcEn;
 105 input       TxDoneIn;
 106 input       TxAbortIn;
 107 input       TxStartFrmOut;
 108 input       ReceivedLengthOK;
 109 input       ReceivedPacketGood;
 110 input       TxUsedDataOutDetected;
 111 input       RxStatusWriteLatched_sync2;
 112 input       r_PassAll;
 113
 114 output      Pause;
 115 output      ReceivedPauseFrm;
 116 output      AddressOK;
 117 output      SetPauseTimer;
 118
 119
 120 reg         Pause;
 121 reg         AddressOK;                // Multicast or unicast address detected
 122 reg         TypeLengthOK;             // Type/Length field contains 0x8808
 123 reg         DetectionWindow;          // Detection of the PAUSE frame is possible within this window
 124 reg         OpCodeOK;                 // PAUSE opcode detected (0x0001)
 125 reg  [2:0]  DlyCrcCnt;
 126 reg  [4:0]  ByteCnt;
 127 reg [15:0]  AssembledTimerValue;
 128 reg [15:0]  LatchedTimerValue;
 129 reg         ReceivedPauseFrm;
 130 reg         ReceivedPauseFrmWAddr;
 131 reg         PauseTimerEq0_sync1;
 132 reg         PauseTimerEq0_sync2;
 133 reg [15:0]  PauseTimer;
 134 reg         Divider2;
 135 reg  [5:0]  SlotTimer;
 136
 137 wire [47:0] ReservedMulticast;        // 0x0180C2000001
 138 wire [15:0] TypeLength;               // 0x8808
 139 wire        ResetByteCnt;             //
 140 wire        IncrementByteCnt;         //
 141 wire        ByteCntEq0;               // ByteCnt = 0
 142 wire        ByteCntEq1;               // ByteCnt = 1
 143 wire        ByteCntEq2;               // ByteCnt = 2
 144 wire        ByteCntEq3;               // ByteCnt = 3
 145 wire        ByteCntEq4;               // ByteCnt = 4
 146 wire        ByteCntEq5;               // ByteCnt = 5
 147 wire        ByteCntEq12;              // ByteCnt = 12
 148 wire        ByteCntEq13;              // ByteCnt = 13
 149 wire        ByteCntEq14;              // ByteCnt = 14
 150 wire        ByteCntEq15;              // ByteCnt = 15
 151 wire        ByteCntEq16;              // ByteCnt = 16
 152 wire        ByteCntEq17;              // ByteCnt = 17
 153 wire        ByteCntEq18;              // ByteCnt = 18
 154 wire        DecrementPauseTimer;      //
 155 wire        PauseTimerEq0;            //
 156 wire        ResetSlotTimer;           //
 157 wire        IncrementSlotTimer;       //
 158 wire        SlotFinished;             //
 159
 160
 161
 162 // Reserved multicast address and Type/Length for PAUSE control
 163 assign ReservedMulticast = 48'h0180C2000001;
 164 assign TypeLength = 16'h8808;
 165
 166
 167 // Address Detection (Multicast or unicast)
 168 always @ (posedge MRxClk or posedge RxReset)
 169 begin
 170   if(RxReset)
 171     AddressOK <= #Tp 1'b0;
 172   else
 173   if(DetectionWindow & ByteCntEq0)
 174     AddressOK <= #Tp  RxData[7:0] == ReservedMulticast[47:40] | RxData[7:0] == MAC[47:40];
 175   else
 176   if(DetectionWindow & ByteCntEq1)
 177     AddressOK <= #Tp (RxData[7:0] == ReservedMulticast[39:32] | RxData[7:0] == MAC[39:32]) & AddressOK;
 178   else
 179   if(DetectionWindow & ByteCntEq2)
 180     AddressOK <= #Tp (RxData[7:0] == ReservedMulticast[31:24] | RxData[7:0] == MAC[31:24]) & AddressOK;
 181   else
 182   if(DetectionWindow & ByteCntEq3)
 183     AddressOK <= #Tp (RxData[7:0] == ReservedMulticast[23:16] | RxData[7:0] == MAC[23:16]) & AddressOK;
 184   else
 185   if(DetectionWindow & ByteCntEq4)
 186     AddressOK <= #Tp (RxData[7:0] == ReservedMulticast[15:8]  | RxData[7:0] == MAC[15:8])  & AddressOK;
 187   else
 188   if(DetectionWindow & ByteCntEq5)
 189     AddressOK <= #Tp (RxData[7:0] == ReservedMulticast[7:0]   | RxData[7:0] == MAC[7:0])   & AddressOK;
 190   else
 191   if(ReceiveEnd)
 192     AddressOK <= #Tp 1'b0;
 193 end
 194
 195
 196
 197 // TypeLengthOK (Type/Length Control frame detected)
 198 always @ (posedge MRxClk or posedge RxReset )
 199 begin
 200   if(RxReset)
 201     TypeLengthOK <= #Tp 1'b0;
 202   else
 203   if(DetectionWindow & ByteCntEq12)
 204     TypeLengthOK <= #Tp ByteCntEq12 & (RxData[7:0] == TypeLength[15:8]);
 205   else
 206   if(DetectionWindow & ByteCntEq13)
 207     TypeLengthOK <= #Tp ByteCntEq13 & (RxData[7:0] == TypeLength[7:0]) & TypeLengthOK;
 208   else
 209   if(ReceiveEnd)
 210     TypeLengthOK <= #Tp 1'b0;
 211 end
 212
 213
 214
 215 // Latch Control Frame Opcode
 216 always @ (posedge MRxClk or posedge RxReset )
 217 begin
 218   if(RxReset)
 219     OpCodeOK <= #Tp 1'b0;
 220   else
 221   if(ByteCntEq16)
 222     OpCodeOK <= #Tp 1'b0;
 223   else
 224     begin
 225       if(DetectionWindow & ByteCntEq14)
 226         OpCodeOK <= #Tp ByteCntEq14 & RxData[7:0] == 8'h00;
 227
 228       if(DetectionWindow & ByteCntEq15)
 229         OpCodeOK <= #Tp ByteCntEq15 & RxData[7:0] == 8'h01 & OpCodeOK;
 230     end
 231 end
 232
 233
 234 // ReceivedPauseFrmWAddr (+Address Check)
 235 always @ (posedge MRxClk or posedge RxReset )
 236 begin
 237   if(RxReset)
 238     ReceivedPauseFrmWAddr <= #Tp 1'b0;
 239   else
 240   if(ReceiveEnd)
 241     ReceivedPauseFrmWAddr <= #Tp 1'b0;
 242   else
 243   if(ByteCntEq16 & TypeLengthOK & OpCodeOK & AddressOK)
 244     ReceivedPauseFrmWAddr <= #Tp 1'b1;
 245 end
 246
 247
 248
 249 // Assembling 16-bit timer value from two 8-bit data
 250 always @ (posedge MRxClk or posedge RxReset )
 251 begin
 252   if(RxReset)
 253     AssembledTimerValue[15:0] <= #Tp 16'h0;
 254   else
 255   if(RxStartFrm)
 256     AssembledTimerValue[15:0] <= #Tp 16'h0;
 257   else
 258     begin
 259       if(DetectionWindow & ByteCntEq16)
 260         AssembledTimerValue[15:8] <= #Tp RxData[7:0];
 261       if(DetectionWindow & ByteCntEq17)
 262         AssembledTimerValue[7:0] <= #Tp RxData[7:0];
 263     end
 264 end
 265
 266
 267 // Detection window (while PAUSE detection is possible)
 268 always @ (posedge MRxClk or posedge RxReset )
 269 begin
 270   if(RxReset)
 271     DetectionWindow <= #Tp 1'b1;
 272   else
 273   if(ByteCntEq18)
 274     DetectionWindow <= #Tp 1'b0;
 275   else
 276   if(ReceiveEnd)
 277     DetectionWindow <= #Tp 1'b1;
 278 end
 279
 280
 281
 282 // Latching Timer Value
 283 always @ (posedge MRxClk or posedge RxReset )
 284 begin
 285   if(RxReset)
 286     LatchedTimerValue[15:0] <= #Tp 16'h0;
 287   else
 288   if(DetectionWindow &  ReceivedPauseFrmWAddr &  ByteCntEq18)
 289     LatchedTimerValue[15:0] <= #Tp AssembledTimerValue[15:0];
 290   else
 291   if(ReceiveEnd)
 292     LatchedTimerValue[15:0] <= #Tp 16'h0;
 293 end
 294
 295
 296
 297 // Delayed CEC counter
 298 always @ (posedge MRxClk or posedge RxReset)
 299 begin
 300   if(RxReset)
 301     DlyCrcCnt <= #Tp 3'h0;
 302   else
 303   if(RxValid & RxEndFrm)
 304     DlyCrcCnt <= #Tp 3'h0;
 305   else
 306   if(RxValid & ~RxEndFrm & ~DlyCrcCnt[2])
 307     DlyCrcCnt <= #Tp DlyCrcCnt + 1'b1;
 308 end
 309
 310
 311 assign ResetByteCnt = RxEndFrm;
 312 assign IncrementByteCnt = RxValid & DetectionWindow & ~ByteCntEq18 & (~DlyCrcEn | DlyCrcEn & DlyCrcCnt[2]);
 313
 314
 315 // Byte counter
 316 always @ (posedge MRxClk or posedge RxReset)
 317 begin
 318   if(RxReset)
 319     ByteCnt[4:0] <= #Tp 5'h0;
 320   else
 321   if(ResetByteCnt)
 322     ByteCnt[4:0] <= #Tp 5'h0;
 323   else
 324   if(IncrementByteCnt)
 325     ByteCnt[4:0] <= #Tp ByteCnt[4:0] + 1'b1;
 326 end
 327
 328
 329 assign ByteCntEq0 = RxValid & ByteCnt[4:0] == 5'h0;
 330 assign ByteCntEq1 = RxValid & ByteCnt[4:0] == 5'h1;
 331 assign ByteCntEq2 = RxValid & ByteCnt[4:0] == 5'h2;
 332 assign ByteCntEq3 = RxValid & ByteCnt[4:0] == 5'h3;
 333 assign ByteCntEq4 = RxValid & ByteCnt[4:0] == 5'h4;
 334 assign ByteCntEq5 = RxValid & ByteCnt[4:0] == 5'h5;
 335 assign ByteCntEq12 = RxValid & ByteCnt[4:0] == 5'h0C;
 336 assign ByteCntEq13 = RxValid & ByteCnt[4:0] == 5'h0D;
 337 assign ByteCntEq14 = RxValid & ByteCnt[4:0] == 5'h0E;
 338 assign ByteCntEq15 = RxValid & ByteCnt[4:0] == 5'h0F;
 339 assign ByteCntEq16 = RxValid & ByteCnt[4:0] == 5'h10;
 340 assign ByteCntEq17 = RxValid & ByteCnt[4:0] == 5'h11;
 341 assign ByteCntEq18 = RxValid & ByteCnt[4:0] == 5'h12 & DetectionWindow;
 342
 343
 344 assign SetPauseTimer = ReceiveEnd & ReceivedPauseFrmWAddr & ReceivedPacketGood & ReceivedLengthOK & RxFlow;
 345 assign DecrementPauseTimer = SlotFinished & |PauseTimer;
 346
 347
 348 // PauseTimer[15:0]
 349 always @ (posedge MRxClk or posedge RxReset)
 350 begin
 351   if(RxReset)
 352     PauseTimer[15:0] <= #Tp 16'h0;
 353   else
 354   if(SetPauseTimer)
 355     PauseTimer[15:0] <= #Tp LatchedTimerValue[15:0];
 356   else
 357   if(DecrementPauseTimer)
 358     PauseTimer[15:0] <= #Tp PauseTimer[15:0] - 1'b1;
 359 end
 360
 361 assign PauseTimerEq0 = ~(|PauseTimer[15:0]);
 362
 363
 364
 365 // Synchronization of the pause timer
 366 always @ (posedge MTxClk or posedge TxReset)
 367 begin
 368   if(TxReset)
 369     begin
 370       PauseTimerEq0_sync1 <= #Tp 1'b1;
 371       PauseTimerEq0_sync2 <= #Tp 1'b1;
 372     end
 373   else
 374     begin
 375       PauseTimerEq0_sync1 <= #Tp PauseTimerEq0;
 376       PauseTimerEq0_sync2 <= #Tp PauseTimerEq0_sync1;
 377     end
 378 end
 379
 380
 381 // Pause signal generation
 382 always @ (posedge MTxClk or posedge TxReset)
 383 begin
 384   if(TxReset)
 385     Pause <= #Tp 1'b0;
 386   else
 387   if((TxDoneIn | TxAbortIn | ~TxUsedDataOutDetected) & ~TxStartFrmOut)
 388     Pause <= #Tp RxFlow & ~PauseTimerEq0_sync2;
 389 end
 390
 391
 392 // Divider2 is used for incrementing the Slot timer every other clock
 393 always @ (posedge MRxClk or posedge RxReset)
 394 begin
 395   if(RxReset)
 396     Divider2 <= #Tp 1'b0;
 397   else
 398   if(|PauseTimer[15:0] & RxFlow)
 399     Divider2 <= #Tp ~Divider2;
 400   else
 401     Divider2 <= #Tp 1'b0;
 402 end
 403
 404
 405 assign ResetSlotTimer = RxReset;
 406 assign IncrementSlotTimer =  Pause & RxFlow & Divider2;
 407
 408
 409 // SlotTimer
 410 always @ (posedge MRxClk or posedge RxReset)
 411 begin
 412   if(RxReset)
 413     SlotTimer[5:0] <= #Tp 6'h0;
 414   else
 415   if(ResetSlotTimer)
 416     SlotTimer[5:0] <= #Tp 6'h0;
 417   else
 418   if(IncrementSlotTimer)
 419     SlotTimer[5:0] <= #Tp SlotTimer[5:0] + 1'b1;
 420 end
 421
 422
 423 assign SlotFinished = &SlotTimer[5:0] & IncrementSlotTimer;  // Slot is 512 bits (64 bytes)
 424
 425
 426
 427 // Pause Frame received
 428 always @ (posedge MRxClk or posedge RxReset)
 429 begin
 430   if(RxReset)
 431     ReceivedPauseFrm <=#Tp 1'b0;
 432   else
 433   if(RxStatusWriteLatched_sync2 & r_PassAll | ReceivedPauseFrm & (~r_PassAll))
 434     ReceivedPauseFrm <=#Tp 1'b0;
 435   else
 436   if(ByteCntEq16 & TypeLengthOK & OpCodeOK)
 437     ReceivedPauseFrm <=#Tp 1'b1;
 438 end
 439
 440
 441 endmodule